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82b4737fd0
Remove dev_err() messages after platform_get_irq*() failures. platform_get_irq() already prints an error. Generated by: scripts/coccinelle/api/platform_get_irq.cocci Signed-off-by: Yihao Han <hanyihao@vivo.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Sean Young <sean@mess.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
405 lines
9.3 KiB
C
405 lines
9.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* meson-ir-tx.c - Amlogic Meson IR TX driver
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*
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* Copyright (c) 2021, SberDevices. All Rights Reserved.
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*
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* Author: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
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*/
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/of_irq.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <media/rc-core.h>
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#define DEVICE_NAME "Meson IR TX"
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#define DRIVER_NAME "meson-ir-tx"
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#define MIRTX_DEFAULT_CARRIER 38000
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#define MIRTX_DEFAULT_DUTY_CYCLE 50
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#define MIRTX_FIFO_THD 32
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#define IRB_MOD_1US_CLK_RATE 1000000
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#define IRB_FIFO_LEN 128
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#define IRB_ADDR0 0x0
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#define IRB_ADDR1 0x4
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#define IRB_ADDR2 0x8
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#define IRB_ADDR3 0xc
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#define IRB_MAX_DELAY (1 << 10)
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#define IRB_DELAY_MASK (IRB_MAX_DELAY - 1)
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/* IRCTRL_IR_BLASTER_ADDR0 */
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#define IRB_MOD_CLK(x) ((x) << 12)
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#define IRB_MOD_SYS_CLK 0
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#define IRB_MOD_XTAL3_CLK 1
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#define IRB_MOD_1US_CLK 2
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#define IRB_MOD_10US_CLK 3
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#define IRB_INIT_HIGH BIT(2)
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#define IRB_ENABLE BIT(0)
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/* IRCTRL_IR_BLASTER_ADDR2 */
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#define IRB_MOD_COUNT(lo, hi) ((((lo) - 1) << 16) | ((hi) - 1))
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/* IRCTRL_IR_BLASTER_ADDR2 */
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#define IRB_WRITE_FIFO BIT(16)
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#define IRB_MOD_ENABLE BIT(12)
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#define IRB_TB_1US (0x0 << 10)
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#define IRB_TB_10US (0x1 << 10)
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#define IRB_TB_100US (0x2 << 10)
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#define IRB_TB_MOD_CLK (0x3 << 10)
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/* IRCTRL_IR_BLASTER_ADDR3 */
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#define IRB_FIFO_THD_PENDING BIT(16)
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#define IRB_FIFO_IRQ_ENABLE BIT(8)
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struct meson_irtx {
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struct device *dev;
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void __iomem *reg_base;
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u32 *buf;
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unsigned int buf_len;
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unsigned int buf_head;
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unsigned int carrier;
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unsigned int duty_cycle;
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/* Locks buf */
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spinlock_t lock;
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struct completion completion;
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unsigned long clk_rate;
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};
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static void meson_irtx_set_mod(struct meson_irtx *ir)
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{
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unsigned int cnt = DIV_ROUND_CLOSEST(ir->clk_rate, ir->carrier);
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unsigned int pulse_cnt = DIV_ROUND_CLOSEST(cnt * ir->duty_cycle, 100);
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unsigned int space_cnt = cnt - pulse_cnt;
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dev_dbg(ir->dev, "F_mod = %uHz, T_mod = %luns, duty_cycle = %u%%\n",
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ir->carrier, NSEC_PER_SEC / ir->clk_rate * cnt,
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100 * pulse_cnt / cnt);
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writel(IRB_MOD_COUNT(pulse_cnt, space_cnt),
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ir->reg_base + IRB_ADDR1);
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}
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static void meson_irtx_setup(struct meson_irtx *ir, unsigned int clk_nr)
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{
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/*
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* Disable the TX, set modulator clock tick and set initialize
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* output to be high. Set up carrier frequency and duty cycle. Then
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* unset initialize output. Enable FIFO interrupt, set FIFO interrupt
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* threshold. Finally, enable the transmitter back.
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*/
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writel(~IRB_ENABLE & (IRB_MOD_CLK(clk_nr) | IRB_INIT_HIGH),
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ir->reg_base + IRB_ADDR0);
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meson_irtx_set_mod(ir);
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writel(readl(ir->reg_base + IRB_ADDR0) & ~IRB_INIT_HIGH,
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ir->reg_base + IRB_ADDR0);
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writel(IRB_FIFO_IRQ_ENABLE | MIRTX_FIFO_THD,
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ir->reg_base + IRB_ADDR3);
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writel(readl(ir->reg_base + IRB_ADDR0) | IRB_ENABLE,
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ir->reg_base + IRB_ADDR0);
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}
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static u32 meson_irtx_prepare_pulse(struct meson_irtx *ir, unsigned int time)
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{
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unsigned int delay;
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unsigned int tb = IRB_TB_MOD_CLK;
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unsigned int tb_us = DIV_ROUND_CLOSEST(USEC_PER_SEC, ir->carrier);
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delay = (DIV_ROUND_CLOSEST(time, tb_us) - 1) & IRB_DELAY_MASK;
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return ((IRB_WRITE_FIFO | IRB_MOD_ENABLE) | tb | delay);
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}
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static u32 meson_irtx_prepare_space(struct meson_irtx *ir, unsigned int time)
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{
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unsigned int delay;
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unsigned int tb = IRB_TB_100US;
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unsigned int tb_us = 100;
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if (time <= IRB_MAX_DELAY) {
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tb = IRB_TB_1US;
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tb_us = 1;
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} else if (time <= 10 * IRB_MAX_DELAY) {
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tb = IRB_TB_10US;
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tb_us = 10;
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} else if (time <= 100 * IRB_MAX_DELAY) {
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tb = IRB_TB_100US;
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tb_us = 100;
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}
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delay = (DIV_ROUND_CLOSEST(time, tb_us) - 1) & IRB_DELAY_MASK;
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return ((IRB_WRITE_FIFO & ~IRB_MOD_ENABLE) | tb | delay);
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}
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static void meson_irtx_send_buffer(struct meson_irtx *ir)
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{
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unsigned int nr = 0;
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unsigned int max_fifo_level = IRB_FIFO_LEN - MIRTX_FIFO_THD;
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while (ir->buf_head < ir->buf_len && nr < max_fifo_level) {
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writel(ir->buf[ir->buf_head], ir->reg_base + IRB_ADDR2);
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ir->buf_head++;
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nr++;
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}
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}
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static bool meson_irtx_check_buf(struct meson_irtx *ir,
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unsigned int *buf, unsigned int len)
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{
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unsigned int i;
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for (i = 0; i < len; i++) {
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unsigned int max_tb_us;
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/*
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* Max space timebase is 100 us.
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* Pulse timebase equals to carrier period.
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*/
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if (i % 2 == 0)
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max_tb_us = USEC_PER_SEC / ir->carrier;
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else
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max_tb_us = 100;
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if (buf[i] >= max_tb_us * IRB_MAX_DELAY)
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return false;
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}
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return true;
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}
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static void meson_irtx_fill_buf(struct meson_irtx *ir, u32 *dst_buf,
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unsigned int *src_buf, unsigned int len)
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{
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unsigned int i;
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for (i = 0; i < len; i++) {
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if (i % 2 == 0)
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dst_buf[i] = meson_irtx_prepare_pulse(ir, src_buf[i]);
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else
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dst_buf[i] = meson_irtx_prepare_space(ir, src_buf[i]);
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}
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}
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static irqreturn_t meson_irtx_irqhandler(int irq, void *data)
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{
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unsigned long flags;
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struct meson_irtx *ir = data;
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writel(readl(ir->reg_base + IRB_ADDR3) & ~IRB_FIFO_THD_PENDING,
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ir->reg_base + IRB_ADDR3);
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if (completion_done(&ir->completion))
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return IRQ_HANDLED;
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spin_lock_irqsave(&ir->lock, flags);
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if (ir->buf_head < ir->buf_len)
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meson_irtx_send_buffer(ir);
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else
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complete(&ir->completion);
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spin_unlock_irqrestore(&ir->lock, flags);
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return IRQ_HANDLED;
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}
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static int meson_irtx_set_carrier(struct rc_dev *rc, u32 carrier)
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{
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struct meson_irtx *ir = rc->priv;
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if (carrier == 0)
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return -EINVAL;
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ir->carrier = carrier;
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meson_irtx_set_mod(ir);
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return 0;
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}
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static int meson_irtx_set_duty_cycle(struct rc_dev *rc, u32 duty_cycle)
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{
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struct meson_irtx *ir = rc->priv;
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ir->duty_cycle = duty_cycle;
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meson_irtx_set_mod(ir);
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return 0;
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}
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static void meson_irtx_update_buf(struct meson_irtx *ir, u32 *buf,
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unsigned int len, unsigned int head)
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{
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ir->buf = buf;
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ir->buf_len = len;
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ir->buf_head = head;
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}
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static int meson_irtx_transmit(struct rc_dev *rc, unsigned int *buf,
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unsigned int len)
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{
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unsigned long flags;
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struct meson_irtx *ir = rc->priv;
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u32 *tx_buf;
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int ret = len;
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if (!meson_irtx_check_buf(ir, buf, len))
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return -EINVAL;
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tx_buf = kmalloc_array(len, sizeof(u32), GFP_KERNEL);
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if (!tx_buf)
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return -ENOMEM;
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meson_irtx_fill_buf(ir, tx_buf, buf, len);
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dev_dbg(ir->dev, "TX buffer filled, length = %u\n", len);
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spin_lock_irqsave(&ir->lock, flags);
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meson_irtx_update_buf(ir, tx_buf, len, 0);
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reinit_completion(&ir->completion);
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meson_irtx_send_buffer(ir);
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spin_unlock_irqrestore(&ir->lock, flags);
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if (!wait_for_completion_timeout(&ir->completion,
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usecs_to_jiffies(IR_MAX_DURATION)))
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ret = -ETIMEDOUT;
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spin_lock_irqsave(&ir->lock, flags);
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kfree(ir->buf);
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meson_irtx_update_buf(ir, NULL, 0, 0);
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spin_unlock_irqrestore(&ir->lock, flags);
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return ret;
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}
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static int meson_irtx_mod_clock_probe(struct meson_irtx *ir,
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unsigned int *clk_nr)
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{
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struct device_node *np = ir->dev->of_node;
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struct clk *clock;
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if (!np)
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return -ENODEV;
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clock = devm_clk_get(ir->dev, "xtal");
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if (IS_ERR(clock) || clk_prepare_enable(clock))
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return -ENODEV;
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*clk_nr = IRB_MOD_XTAL3_CLK;
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ir->clk_rate = clk_get_rate(clock) / 3;
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if (ir->clk_rate < IRB_MOD_1US_CLK_RATE) {
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*clk_nr = IRB_MOD_1US_CLK;
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ir->clk_rate = IRB_MOD_1US_CLK_RATE;
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}
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dev_info(ir->dev, "F_clk = %luHz\n", ir->clk_rate);
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return 0;
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}
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static int __init meson_irtx_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct meson_irtx *ir;
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struct rc_dev *rc;
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int irq;
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unsigned int clk_nr;
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int ret;
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ir = devm_kzalloc(dev, sizeof(*ir), GFP_KERNEL);
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if (!ir)
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return -ENOMEM;
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ir->reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(ir->reg_base))
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return PTR_ERR(ir->reg_base);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return -ENODEV;
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ir->dev = dev;
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ir->carrier = MIRTX_DEFAULT_CARRIER;
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ir->duty_cycle = MIRTX_DEFAULT_DUTY_CYCLE;
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init_completion(&ir->completion);
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spin_lock_init(&ir->lock);
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ret = meson_irtx_mod_clock_probe(ir, &clk_nr);
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if (ret) {
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dev_err(dev, "modulator clock setup failed\n");
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return ret;
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}
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meson_irtx_setup(ir, clk_nr);
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ret = devm_request_irq(dev, irq,
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meson_irtx_irqhandler,
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IRQF_TRIGGER_RISING,
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DRIVER_NAME, ir);
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if (ret) {
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dev_err(dev, "irq request failed\n");
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return ret;
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}
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rc = rc_allocate_device(RC_DRIVER_IR_RAW_TX);
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if (!rc)
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return -ENOMEM;
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rc->driver_name = DRIVER_NAME;
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rc->device_name = DEVICE_NAME;
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rc->priv = ir;
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rc->tx_ir = meson_irtx_transmit;
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rc->s_tx_carrier = meson_irtx_set_carrier;
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rc->s_tx_duty_cycle = meson_irtx_set_duty_cycle;
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ret = rc_register_device(rc);
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if (ret < 0) {
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dev_err(dev, "rc_dev registration failed\n");
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rc_free_device(rc);
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return ret;
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}
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platform_set_drvdata(pdev, rc);
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return 0;
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}
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static int meson_irtx_remove(struct platform_device *pdev)
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{
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struct rc_dev *rc = platform_get_drvdata(pdev);
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rc_unregister_device(rc);
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return 0;
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}
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static const struct of_device_id meson_irtx_dt_match[] = {
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{
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.compatible = "amlogic,meson-g12a-ir-tx",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, meson_irtx_dt_match);
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static struct platform_driver meson_irtx_pd = {
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.remove = meson_irtx_remove,
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = meson_irtx_dt_match,
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},
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};
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module_platform_driver_probe(meson_irtx_pd, meson_irtx_probe);
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MODULE_DESCRIPTION("Meson IR TX driver");
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MODULE_AUTHOR("Viktor Prutyanov <viktor.prutyanov@phystech.edu>");
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MODULE_LICENSE("GPL");
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