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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
588 lines
17 KiB
C
588 lines
17 KiB
C
/*
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* dv1394-private.h - DV input/output over IEEE 1394 on OHCI chips
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* Copyright (C)2001 Daniel Maas <dmaas@dcine.com>
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* receive by Dan Dennedy <dan@dennedy.org>
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*
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* based on:
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* video1394.h - driver for OHCI 1394 boards
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* Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
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* Peter Schlaile <udbz@rz.uni-karlsruhe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _DV_1394_PRIVATE_H
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#define _DV_1394_PRIVATE_H
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#include "ieee1394.h"
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#include "ohci1394.h"
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#include "dma.h"
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/* data structures private to the dv1394 driver */
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/* none of this is exposed to user-space */
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/*
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the 8-byte CIP (Common Isochronous Packet) header that precedes
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each packet of DV data.
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See the IEC 61883 standard.
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*/
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struct CIP_header { unsigned char b[8]; };
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static inline void fill_cip_header(struct CIP_header *cip,
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unsigned char source_node_id,
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unsigned long counter,
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enum pal_or_ntsc format,
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unsigned long timestamp)
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{
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cip->b[0] = source_node_id;
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cip->b[1] = 0x78; /* packet size in quadlets (480/4) - even for empty packets! */
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cip->b[2] = 0x00;
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cip->b[3] = counter;
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cip->b[4] = 0x80; /* const */
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switch(format) {
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case DV1394_PAL:
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cip->b[5] = 0x80;
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break;
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case DV1394_NTSC:
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cip->b[5] = 0x00;
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break;
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}
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cip->b[6] = timestamp >> 8;
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cip->b[7] = timestamp & 0xFF;
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}
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/*
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DMA commands used to program the OHCI's DMA engine
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See the Texas Instruments OHCI 1394 chipset documentation.
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*/
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struct output_more_immediate { u32 q[8]; };
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struct output_more { u32 q[4]; };
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struct output_last { u32 q[4]; };
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struct input_more { u32 q[4]; };
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struct input_last { u32 q[4]; };
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/* outputs */
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static inline void fill_output_more_immediate(struct output_more_immediate *omi,
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unsigned char tag,
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unsigned char channel,
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unsigned char sync_tag,
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unsigned int payload_size)
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{
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omi->q[0] = cpu_to_le32(0x02000000 | 8); /* OUTPUT_MORE_IMMEDIATE; 8 is the size of the IT header */
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omi->q[1] = 0;
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omi->q[2] = 0;
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omi->q[3] = 0;
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/* IT packet header */
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omi->q[4] = cpu_to_le32( (0x0 << 16) /* IEEE1394_SPEED_100 */
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| (tag << 14)
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| (channel << 8)
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| (TCODE_ISO_DATA << 4)
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| (sync_tag) );
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/* reserved field; mimic behavior of my Sony DSR-40 */
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omi->q[5] = cpu_to_le32((payload_size << 16) | (0x7F << 8) | 0xA0);
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omi->q[6] = 0;
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omi->q[7] = 0;
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}
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static inline void fill_output_more(struct output_more *om,
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unsigned int data_size,
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unsigned long data_phys_addr)
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{
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om->q[0] = cpu_to_le32(data_size);
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om->q[1] = cpu_to_le32(data_phys_addr);
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om->q[2] = 0;
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om->q[3] = 0;
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}
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static inline void fill_output_last(struct output_last *ol,
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int want_timestamp,
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int want_interrupt,
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unsigned int data_size,
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unsigned long data_phys_addr)
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{
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u32 temp = 0;
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temp |= 1 << 28; /* OUTPUT_LAST */
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if (want_timestamp) /* controller will update timestamp at DMA time */
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temp |= 1 << 27;
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if (want_interrupt)
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temp |= 3 << 20;
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temp |= 3 << 18; /* must take branch */
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temp |= data_size;
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ol->q[0] = cpu_to_le32(temp);
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ol->q[1] = cpu_to_le32(data_phys_addr);
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ol->q[2] = 0;
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ol->q[3] = 0;
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}
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/* inputs */
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static inline void fill_input_more(struct input_more *im,
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int want_interrupt,
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unsigned int data_size,
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unsigned long data_phys_addr)
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{
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u32 temp = 2 << 28; /* INPUT_MORE */
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temp |= 8 << 24; /* s = 1, update xferStatus and resCount */
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if (want_interrupt)
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temp |= 0 << 20; /* interrupts, i=0 in packet-per-buffer mode */
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temp |= 0x0 << 16; /* disable branch to address for packet-per-buffer mode */
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/* disable wait on sync field, not used in DV :-( */
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temp |= data_size;
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im->q[0] = cpu_to_le32(temp);
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im->q[1] = cpu_to_le32(data_phys_addr);
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im->q[2] = 0; /* branchAddress and Z not use in packet-per-buffer mode */
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im->q[3] = 0; /* xferStatus & resCount, resCount must be initialize to data_size */
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}
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static inline void fill_input_last(struct input_last *il,
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int want_interrupt,
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unsigned int data_size,
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unsigned long data_phys_addr)
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{
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u32 temp = 3 << 28; /* INPUT_LAST */
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temp |= 8 << 24; /* s = 1, update xferStatus and resCount */
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if (want_interrupt)
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temp |= 3 << 20; /* enable interrupts */
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temp |= 0xC << 16; /* enable branch to address */
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/* disable wait on sync field, not used in DV :-( */
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temp |= data_size;
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il->q[0] = cpu_to_le32(temp);
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il->q[1] = cpu_to_le32(data_phys_addr);
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il->q[2] = cpu_to_le32(1); /* branchAddress (filled in later) and Z = 1 descriptor in next block */
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il->q[3] = cpu_to_le32(data_size); /* xferStatus & resCount, resCount must be initialize to data_size */
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}
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/*
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A "DMA descriptor block" consists of several contiguous DMA commands.
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struct DMA_descriptor_block encapsulates all of the commands necessary
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to send one packet of DV data.
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There are three different types of these blocks:
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1) command to send an empty packet (CIP header only, no DV data):
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OUTPUT_MORE-Immediate <-- contains the iso header in-line
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OUTPUT_LAST <-- points to the CIP header
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2) command to send a full packet when the DV data payload does NOT
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cross a page boundary:
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OUTPUT_MORE-Immediate <-- contains the iso header in-line
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OUTPUT_MORE <-- points to the CIP header
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OUTPUT_LAST <-- points to entire DV data payload
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3) command to send a full packet when the DV payload DOES cross
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a page boundary:
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OUTPUT_MORE-Immediate <-- contains the iso header in-line
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OUTPUT_MORE <-- points to the CIP header
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OUTPUT_MORE <-- points to first part of DV data payload
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OUTPUT_LAST <-- points to second part of DV data payload
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This struct describes all three block types using unions.
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!!! It is vital that an even number of these descriptor blocks fit on one
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page of memory, since a block cannot cross a page boundary !!!
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*/
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struct DMA_descriptor_block {
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union {
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struct {
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/* iso header, common to all output block types */
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struct output_more_immediate omi;
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union {
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/* empty packet */
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struct {
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struct output_last ol; /* CIP header */
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} empty;
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/* full packet */
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struct {
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struct output_more om; /* CIP header */
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union {
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/* payload does not cross page boundary */
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struct {
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struct output_last ol; /* data payload */
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} nocross;
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/* payload crosses page boundary */
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struct {
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struct output_more om; /* data payload */
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struct output_last ol; /* data payload */
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} cross;
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} u;
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} full;
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} u;
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} out;
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struct {
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struct input_last il;
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} in;
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} u;
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/* ensure that PAGE_SIZE % sizeof(struct DMA_descriptor_block) == 0
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by padding out to 128 bytes */
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u32 __pad__[12];
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};
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/* struct frame contains all data associated with one frame in the
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ringbuffer these are allocated when the DMA context is initialized
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do_dv1394_init(). They are re-used after the card finishes
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transmitting the frame. */
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struct video_card; /* forward declaration */
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struct frame {
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/* points to the struct video_card that owns this frame */
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struct video_card *video;
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/* index of this frame in video_card->frames[] */
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unsigned int frame_num;
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/* FRAME_CLEAR - DMA program not set up, waiting for data
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FRAME_READY - DMA program written, ready to transmit
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Changes to these should be locked against the interrupt
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*/
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enum {
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FRAME_CLEAR = 0,
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FRAME_READY
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} state;
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/* whether this frame has been DMA'ed already; used only from
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the IRQ handler to determine whether the frame can be reset */
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int done;
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/* kernel virtual pointer to the start of this frame's data in
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the user ringbuffer. Use only for CPU access; to get the DMA
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bus address you must go through the video->user_dma mapping */
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unsigned long data;
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/* Max # of packets per frame */
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#define MAX_PACKETS 500
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/* a PAGE_SIZE memory pool for allocating CIP headers
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!header_pool must be aligned to PAGE_SIZE! */
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struct CIP_header *header_pool;
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dma_addr_t header_pool_dma;
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/* a physically contiguous memory pool for allocating DMA
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descriptor blocks; usually around 64KB in size
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!descriptor_pool must be aligned to PAGE_SIZE! */
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struct DMA_descriptor_block *descriptor_pool;
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dma_addr_t descriptor_pool_dma;
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unsigned long descriptor_pool_size;
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/* # of packets allocated for this frame */
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unsigned int n_packets;
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/* below are several pointers (kernel virtual addresses, not
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DMA bus addresses) to parts of the DMA program. These are
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set each time the DMA program is written in
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frame_prepare(). They are used later on, e.g. from the
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interrupt handler, to check the status of the frame */
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/* points to status/timestamp field of first DMA packet */
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/* (we'll check it later to monitor timestamp accuracy) */
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u32 *frame_begin_timestamp;
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/* the timestamp we assigned to the first packet in the frame */
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u32 assigned_timestamp;
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/* pointer to the first packet's CIP header (where the timestamp goes) */
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struct CIP_header *cip_syt1;
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/* pointer to the second packet's CIP header
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(only set if the first packet was empty) */
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struct CIP_header *cip_syt2;
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/* in order to figure out what caused an interrupt,
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store pointers to the status fields of the two packets
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that can cause interrupts. We'll check these from the
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interrupt handler.
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*/
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u32 *mid_frame_timestamp;
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u32 *frame_end_timestamp;
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/* branch address field of final packet. This is effectively
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the "tail" in the chain of DMA descriptor blocks.
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We will fill it with the address of the first DMA descriptor
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block in the subsequent frame, once it is ready.
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*/
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u32 *frame_end_branch;
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/* the number of descriptors in the first descriptor block
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of the frame. Needed to start DMA */
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int first_n_descriptors;
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};
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struct packet {
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u16 timestamp;
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u16 invalid;
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u16 iso_header;
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u16 data_length;
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u32 cip_h1;
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u32 cip_h2;
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unsigned char data[480];
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unsigned char padding[16]; /* force struct size =512 for page alignment */
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};
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/* allocate/free a frame */
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static struct frame* frame_new(unsigned int frame_num, struct video_card *video);
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static void frame_delete(struct frame *f);
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/* reset f so that it can be used again */
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static void frame_reset(struct frame *f);
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/* struct video_card contains all data associated with one instance
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of the dv1394 driver
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*/
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enum modes {
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MODE_RECEIVE,
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MODE_TRANSMIT
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};
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struct video_card {
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/* ohci card to which this instance corresponds */
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struct ti_ohci *ohci;
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/* OHCI card id; the link between the VFS inode and a specific video_card
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(essentially the device minor number) */
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int id;
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/* entry in dv1394_cards */
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struct list_head list;
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/* OHCI card IT DMA context number, -1 if not in use */
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int ohci_it_ctx;
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struct ohci1394_iso_tasklet it_tasklet;
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/* register offsets for current IT DMA context, 0 if not in use */
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u32 ohci_IsoXmitContextControlSet;
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u32 ohci_IsoXmitContextControlClear;
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u32 ohci_IsoXmitCommandPtr;
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/* OHCI card IR DMA context number, -1 if not in use */
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struct ohci1394_iso_tasklet ir_tasklet;
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int ohci_ir_ctx;
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/* register offsets for current IR DMA context, 0 if not in use */
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u32 ohci_IsoRcvContextControlSet;
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u32 ohci_IsoRcvContextControlClear;
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u32 ohci_IsoRcvCommandPtr;
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u32 ohci_IsoRcvContextMatch;
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/* CONCURRENCY CONTROL */
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/* there are THREE levels of locking associated with video_card. */
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/*
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1) the 'open' flag - this prevents more than one process from
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opening the device. (the driver currently assumes only one opener).
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This is a regular int, but use test_and_set_bit() (on bit zero)
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for atomicity.
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*/
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unsigned long open;
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/*
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2) the spinlock - this provides mutual exclusion between the interrupt
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handler and process-context operations. Generally you must take the
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spinlock under the following conditions:
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1) DMA (and hence the interrupt handler) may be running
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AND
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2) you need to operate on the video_card, especially active_frame
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It is OK to play with video_card without taking the spinlock if
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you are certain that DMA is not running. Even if DMA is running,
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it is OK to *read* active_frame with the lock, then drop it
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immediately. This is safe because the interrupt handler will never
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advance active_frame onto a frame that is not READY (and the spinlock
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must be held while marking a frame READY).
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spinlock is also used to protect ohci_it_ctx and ohci_ir_ctx,
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which can be accessed from both process and interrupt context
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*/
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spinlock_t spinlock;
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/* flag to prevent spurious interrupts (which OHCI seems to
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generate a lot :) from accessing the struct */
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int dma_running;
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/*
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3) the sleeping semaphore 'sem' - this is used from process context only,
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to serialize various operations on the video_card. Even though only one
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open() is allowed, we still need to prevent multiple threads of execution
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from entering calls like read, write, ioctl, etc.
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I honestly can't think of a good reason to use dv1394 from several threads
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at once, but we need to serialize anyway to prevent oopses =).
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NOTE: if you need both spinlock and sem, take sem first to avoid deadlock!
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*/
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struct semaphore sem;
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/* people waiting for buffer space, please form a line here... */
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wait_queue_head_t waitq;
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/* support asynchronous I/O signals (SIGIO) */
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struct fasync_struct *fasync;
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/* the large, non-contiguous (rvmalloc()) ringbuffer for DV
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data, exposed to user-space via mmap() */
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unsigned long dv_buf_size;
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struct dma_region dv_buf;
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/* next byte in the ringbuffer that a write() call will fill */
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size_t write_off;
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struct frame *frames[DV1394_MAX_FRAMES];
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/* n_frames also serves as an indicator that this struct video_card is
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initialized and ready to run DMA buffers */
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int n_frames;
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/* this is the frame that is currently "owned" by the OHCI DMA controller
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(set to -1 iff DMA is not running)
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! must lock against the interrupt handler when accessing it !
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RULES:
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Only the interrupt handler may change active_frame if DMA
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is running; if not, process may change it
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If the next frame is READY, the interrupt handler will advance
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active_frame when the current frame is finished.
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If the next frame is CLEAR, the interrupt handler will re-transmit
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the current frame, and the dropped_frames counter will be incremented.
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The interrupt handler will NEVER advance active_frame to a
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frame that is not READY.
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*/
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int active_frame;
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int first_run;
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/* the same locking rules apply to these three fields also: */
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/* altered ONLY from process context. Must check first_clear_frame->state;
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if it's READY, that means the ringbuffer is full with READY frames;
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if it's CLEAR, that means one or more ringbuffer frames are CLEAR */
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unsigned int first_clear_frame;
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/* altered both by process and interrupt */
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unsigned int n_clear_frames;
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/* only altered by the interrupt */
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unsigned int dropped_frames;
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/* the CIP accumulator and continuity counter are properties
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of the DMA stream as a whole (not a single frame), so they
|
|
are stored here in the video_card */
|
|
|
|
unsigned long cip_accum;
|
|
unsigned long cip_n, cip_d;
|
|
unsigned int syt_offset;
|
|
unsigned int continuity_counter;
|
|
|
|
enum pal_or_ntsc pal_or_ntsc;
|
|
|
|
/* redundant, but simplifies the code somewhat */
|
|
unsigned int frame_size; /* in bytes */
|
|
|
|
/* the isochronous channel to use, -1 if video card is inactive */
|
|
int channel;
|
|
|
|
|
|
/* physically contiguous packet ringbuffer for receive */
|
|
struct dma_region packet_buf;
|
|
unsigned long packet_buf_size;
|
|
|
|
unsigned int current_packet;
|
|
int first_frame; /* received first start frame marker? */
|
|
enum modes mode;
|
|
};
|
|
|
|
/*
|
|
if the video_card is not initialized, then the ONLY fields that are valid are:
|
|
ohci
|
|
open
|
|
n_frames
|
|
*/
|
|
|
|
static inline int video_card_initialized(struct video_card *v)
|
|
{
|
|
return v->n_frames > 0;
|
|
}
|
|
|
|
static int do_dv1394_init(struct video_card *video, struct dv1394_init *init);
|
|
static int do_dv1394_init_default(struct video_card *video);
|
|
static void do_dv1394_shutdown(struct video_card *video, int free_user_buf);
|
|
|
|
|
|
/* NTSC empty packet rate accurate to within 0.01%,
|
|
calibrated against a Sony DSR-40 DVCAM deck */
|
|
|
|
#define CIP_N_NTSC 68000000
|
|
#define CIP_D_NTSC 1068000000
|
|
|
|
#define CIP_N_PAL 1
|
|
#define CIP_D_PAL 16
|
|
|
|
#endif /* _DV_1394_PRIVATE_H */
|
|
|