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6ee738610f
This adds a drm/kms staging non-API stable driver for GPUs from NVIDIA. This driver is a KMS-based driver and requires a compatible nouveau userspace libdrm and nouveau X.org driver. This driver requires firmware files not available in this kernel tree, interested parties can find them via the nouveau project git archive. This driver is reverse engineered, and is in no way supported by nVidia. Support for nearly the complete range of nvidia hw from nv04->g80 (nv50) is available, and the kms driver should support driving nearly all output types (displayport is under development still) along with supporting suspend/resume. This work is all from the upstream nouveau project found at nouveau.freedesktop.org. The original authors list from nouveau git tree is: Anssi Hannula <anssi.hannula@iki.fi> Ben Skeggs <bskeggs@redhat.com> Francisco Jerez <currojerez@riseup.net> Maarten Maathuis <madman2003@gmail.com> Marcin Kościelnicki <koriakin@0x04.net> Matthew Garrett <mjg@redhat.com> Matt Parnell <mparnell@gmail.com> Patrice Mandin <patmandin@gmail.com> Pekka Paalanen <pq@iki.fi> Xavier Chantry <shiningxc@gmail.com> along with project founder Stephane Marchesin <marchesin@icps.u-strasbg.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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int
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nv04_timer_init(struct drm_device *dev)
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{
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nv_wr32(dev, NV04_PTIMER_INTR_EN_0, 0x00000000);
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nv_wr32(dev, NV04_PTIMER_INTR_0, 0xFFFFFFFF);
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/* Just use the pre-existing values when possible for now; these regs
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* are not written in nv (driver writer missed a /4 on the address), and
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* writing 8 and 3 to the correct regs breaks the timings on the LVDS
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* hardware sequencing microcode.
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* A correct solution (involving calculations with the GPU PLL) can
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* be done when kernel modesetting lands
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*/
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if (!nv_rd32(dev, NV04_PTIMER_NUMERATOR) ||
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!nv_rd32(dev, NV04_PTIMER_DENOMINATOR)) {
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nv_wr32(dev, NV04_PTIMER_NUMERATOR, 0x00000008);
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nv_wr32(dev, NV04_PTIMER_DENOMINATOR, 0x00000003);
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}
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return 0;
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}
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uint64_t
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nv04_timer_read(struct drm_device *dev)
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{
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uint32_t low;
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/* From kmmio dumps on nv28 this looks like how the blob does this.
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* It reads the high dword twice, before and after.
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* The only explanation seems to be that the 64-bit timer counter
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* advances between high and low dword reads and may corrupt the
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* result. Not confirmed.
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*/
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uint32_t high2 = nv_rd32(dev, NV04_PTIMER_TIME_1);
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uint32_t high1;
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do {
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high1 = high2;
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low = nv_rd32(dev, NV04_PTIMER_TIME_0);
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high2 = nv_rd32(dev, NV04_PTIMER_TIME_1);
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} while (high1 != high2);
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return (((uint64_t)high2) << 32) | (uint64_t)low;
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}
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void
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nv04_timer_takedown(struct drm_device *dev)
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{
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}
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