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The z14 machine introduces new mode of the next-instruction-access-intent NIAI instruction. With NIAI-8 it is possible to pin a cache-line on a CPU for a small amount of time, NIAI-7 releases the cache-line again. Finally NIAI-4 can be used to prevent the CPU to speculatively access memory beyond the compare-and-swap instruction to get the lock. Use these instruction in the spinlock code. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
273 lines
5.6 KiB
C
273 lines
5.6 KiB
C
/*
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* Out of line spinlock code.
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*
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* Copyright IBM Corp. 2004, 2006
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
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*/
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#include <linux/types.h>
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#include <linux/export.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/io.h>
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int spin_retry = -1;
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static int __init spin_retry_init(void)
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{
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if (spin_retry < 0)
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spin_retry = 1000;
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return 0;
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}
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early_initcall(spin_retry_init);
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/**
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* spin_retry= parameter
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*/
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static int __init spin_retry_setup(char *str)
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{
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spin_retry = simple_strtoul(str, &str, 0);
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return 1;
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}
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__setup("spin_retry=", spin_retry_setup);
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static inline int arch_load_niai4(int *lock)
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{
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int owner;
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asm volatile(
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#ifdef CONFIG_HAVE_MARCH_ZEC12_FEATURES
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" .long 0xb2fa0040\n" /* NIAI 4 */
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#endif
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" l %0,%1\n"
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: "=d" (owner) : "Q" (*lock) : "memory");
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return owner;
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}
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static inline int arch_cmpxchg_niai8(int *lock, int old, int new)
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{
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int expected = old;
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asm volatile(
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#ifdef CONFIG_HAVE_MARCH_ZEC12_FEATURES
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" .long 0xb2fa0080\n" /* NIAI 8 */
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#endif
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" cs %0,%3,%1\n"
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: "=d" (old), "=Q" (*lock)
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: "0" (old), "d" (new), "Q" (*lock)
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: "cc", "memory");
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return expected == old;
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}
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void arch_spin_lock_wait(arch_spinlock_t *lp)
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{
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int cpu = SPINLOCK_LOCKVAL;
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int owner, count;
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/* Pass the virtual CPU to the lock holder if it is not running */
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owner = arch_load_niai4(&lp->lock);
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if (owner && arch_vcpu_is_preempted(~owner))
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smp_yield_cpu(~owner);
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count = spin_retry;
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while (1) {
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owner = arch_load_niai4(&lp->lock);
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/* Try to get the lock if it is free. */
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if (!owner) {
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if (arch_cmpxchg_niai8(&lp->lock, 0, cpu))
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return;
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continue;
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}
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if (count-- >= 0)
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continue;
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count = spin_retry;
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/*
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* For multiple layers of hypervisors, e.g. z/VM + LPAR
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* yield the CPU unconditionally. For LPAR rely on the
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* sense running status.
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*/
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if (!MACHINE_IS_LPAR || arch_vcpu_is_preempted(~owner))
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smp_yield_cpu(~owner);
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}
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}
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EXPORT_SYMBOL(arch_spin_lock_wait);
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void arch_spin_lock_wait_flags(arch_spinlock_t *lp, unsigned long flags)
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{
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int cpu = SPINLOCK_LOCKVAL;
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int owner, count;
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local_irq_restore(flags);
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/* Pass the virtual CPU to the lock holder if it is not running */
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owner = arch_load_niai4(&lp->lock);
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if (owner && arch_vcpu_is_preempted(~owner))
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smp_yield_cpu(~owner);
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count = spin_retry;
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while (1) {
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owner = arch_load_niai4(&lp->lock);
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/* Try to get the lock if it is free. */
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if (!owner) {
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local_irq_disable();
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if (arch_cmpxchg_niai8(&lp->lock, 0, cpu))
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return;
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local_irq_restore(flags);
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continue;
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}
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if (count-- >= 0)
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continue;
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count = spin_retry;
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/*
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* For multiple layers of hypervisors, e.g. z/VM + LPAR
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* yield the CPU unconditionally. For LPAR rely on the
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* sense running status.
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*/
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if (!MACHINE_IS_LPAR || arch_vcpu_is_preempted(~owner))
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smp_yield_cpu(~owner);
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}
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}
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EXPORT_SYMBOL(arch_spin_lock_wait_flags);
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int arch_spin_trylock_retry(arch_spinlock_t *lp)
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{
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int cpu = SPINLOCK_LOCKVAL;
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int owner, count;
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for (count = spin_retry; count > 0; count--) {
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owner = READ_ONCE(lp->lock);
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/* Try to get the lock if it is free. */
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if (!owner) {
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if (__atomic_cmpxchg_bool(&lp->lock, 0, cpu))
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return 1;
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}
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}
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return 0;
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}
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EXPORT_SYMBOL(arch_spin_trylock_retry);
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void _raw_read_lock_wait(arch_rwlock_t *rw)
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{
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int count = spin_retry;
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int owner, old;
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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__RAW_LOCK(&rw->lock, -1, __RAW_OP_ADD);
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#endif
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owner = 0;
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while (1) {
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if (count-- <= 0) {
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if (owner && arch_vcpu_is_preempted(~owner))
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smp_yield_cpu(~owner);
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count = spin_retry;
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}
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old = ACCESS_ONCE(rw->lock);
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owner = ACCESS_ONCE(rw->owner);
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if (old < 0)
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continue;
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if (__atomic_cmpxchg_bool(&rw->lock, old, old + 1))
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return;
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}
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}
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EXPORT_SYMBOL(_raw_read_lock_wait);
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int _raw_read_trylock_retry(arch_rwlock_t *rw)
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{
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int count = spin_retry;
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int old;
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while (count-- > 0) {
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old = ACCESS_ONCE(rw->lock);
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if (old < 0)
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continue;
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if (__atomic_cmpxchg_bool(&rw->lock, old, old + 1))
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return 1;
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}
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return 0;
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}
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EXPORT_SYMBOL(_raw_read_trylock_retry);
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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void _raw_write_lock_wait(arch_rwlock_t *rw, int prev)
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{
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int count = spin_retry;
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int owner, old;
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owner = 0;
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while (1) {
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if (count-- <= 0) {
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if (owner && arch_vcpu_is_preempted(~owner))
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smp_yield_cpu(~owner);
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count = spin_retry;
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}
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old = ACCESS_ONCE(rw->lock);
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owner = ACCESS_ONCE(rw->owner);
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smp_mb();
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if (old >= 0) {
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prev = __RAW_LOCK(&rw->lock, 0x80000000, __RAW_OP_OR);
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old = prev;
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}
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if ((old & 0x7fffffff) == 0 && prev >= 0)
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break;
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}
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}
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EXPORT_SYMBOL(_raw_write_lock_wait);
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#else /* CONFIG_HAVE_MARCH_Z196_FEATURES */
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void _raw_write_lock_wait(arch_rwlock_t *rw)
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{
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int count = spin_retry;
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int owner, old, prev;
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prev = 0x80000000;
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owner = 0;
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while (1) {
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if (count-- <= 0) {
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if (owner && arch_vcpu_is_preempted(~owner))
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smp_yield_cpu(~owner);
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count = spin_retry;
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}
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old = ACCESS_ONCE(rw->lock);
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owner = ACCESS_ONCE(rw->owner);
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if (old >= 0 &&
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__atomic_cmpxchg_bool(&rw->lock, old, old | 0x80000000))
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prev = old;
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else
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smp_mb();
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if ((old & 0x7fffffff) == 0 && prev >= 0)
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break;
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}
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}
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EXPORT_SYMBOL(_raw_write_lock_wait);
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#endif /* CONFIG_HAVE_MARCH_Z196_FEATURES */
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int _raw_write_trylock_retry(arch_rwlock_t *rw)
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{
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int count = spin_retry;
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int old;
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while (count-- > 0) {
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old = ACCESS_ONCE(rw->lock);
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if (old)
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continue;
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if (__atomic_cmpxchg_bool(&rw->lock, 0, 0x80000000))
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return 1;
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}
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return 0;
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}
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EXPORT_SYMBOL(_raw_write_trylock_retry);
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void arch_lock_relax(int cpu)
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{
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if (!cpu)
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return;
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if (MACHINE_IS_LPAR && !arch_vcpu_is_preempted(~cpu))
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return;
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smp_yield_cpu(~cpu);
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}
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EXPORT_SYMBOL(arch_lock_relax);
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