Kishon Vijay Abraham I db7a346405 dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock provider ... Add #clock-cells binding to model Sierra as clock provider and include clock IDs for PLL_CMNLC and PLL_CMNLC1. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210319124128.13308-12-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2021-03-31 16:43:21 +05:30
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phy-am654-serdes.h	dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC	2019-04-17 14:13:18 +05:30
phy-cadence.h	dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock provider	2021-03-31 16:43:21 +05:30
phy-lantiq-vrx200-pcie.h	dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYs	2019-08-23 09:40:46 +05:30
phy-ocelot-serdes.h	dt-bindings: phy: Update SERDES_MAX to be SERDES_MAX + 1	2018-10-22 19:27:14 -07:00
phy-pistachio-usb.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422	2019-06-05 17:37:15 +02:00
phy-qcom-qusb2.h	dt-bindings: phy-qcom-usb2: Add support to override tuning values	2018-05-20 21:51:31 +05:30
phy-ti.h	dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper	2021-03-17 12:02:40 +05:30
phy.h	dt-bindings: phy: Add PHY_TYPE_QSGMII definition	2020-09-18 10:47:19 +05:30