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79150ac9f3
Cleanup blank lines, remove wrong links to http://www.gnu.org/copyleft/gpl.html (the driver is licensed under the terms of GPLv2, but the link points to a copy of the GPLv3), and fix the filename reference in ddbridge-i2c.h. [mchehab@kernel.org: removed whitespace changes at the licensing text, as we didn't get any acks from the authors with regards to changing the text] Cc: Ralph Metzler <rjkm@metzlerbros.de> Cc: Manfred Voelkel <mvoelkel@DigitalDevices.de> Signed-off-by: Daniel Scheller <d.scheller@gmx.net> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
150 lines
5.0 KiB
C
150 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ddbridge-regs.h: Digital Devices PCIe bridge driver
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*
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* Copyright (C) 2010-2017 Digital Devices GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 only, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DDBRIDGE_REGS_H__
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#define __DDBRIDGE_REGS_H__
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/* ------------------------------------------------------------------------- */
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/* SPI Controller */
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#define SPI_CONTROL 0x10
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#define SPI_DATA 0x14
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/* ------------------------------------------------------------------------- */
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/* GPIO */
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#define GPIO_OUTPUT 0x20
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#define GPIO_INPUT 0x24
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#define GPIO_DIRECTION 0x28
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/* ------------------------------------------------------------------------- */
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#define BOARD_CONTROL 0x30
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/* ------------------------------------------------------------------------- */
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/* Interrupt controller
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* How many MSI's are available depends on HW (Min 2 max 8)
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* How many are usable also depends on Host platform
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*/
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#define INTERRUPT_BASE (0x40)
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#define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00)
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#define MSI1_ENABLE (INTERRUPT_BASE + 0x04)
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#define MSI2_ENABLE (INTERRUPT_BASE + 0x08)
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#define MSI3_ENABLE (INTERRUPT_BASE + 0x0C)
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#define MSI4_ENABLE (INTERRUPT_BASE + 0x10)
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#define MSI5_ENABLE (INTERRUPT_BASE + 0x14)
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#define MSI6_ENABLE (INTERRUPT_BASE + 0x18)
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#define MSI7_ENABLE (INTERRUPT_BASE + 0x1C)
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#define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20)
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#define INTERRUPT_ACK (INTERRUPT_BASE + 0x20)
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/* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */
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#define TEMPMON_BASE (0x1c0)
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#define TEMPMON_CONTROL (TEMPMON_BASE + 0x00)
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#define TEMPMON_CONTROL_AUTOSCAN (0x00000002)
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#define TEMPMON_CONTROL_INTENABLE (0x00000004)
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#define TEMPMON_CONTROL_OVERTEMP (0x00008000)
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/* SHORT Temperature in Celsius x 256 */
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#define TEMPMON_SENSOR0 (TEMPMON_BASE + 0x04)
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#define TEMPMON_SENSOR1 (TEMPMON_BASE + 0x08)
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#define TEMPMON_FANCONTROL (TEMPMON_BASE + 0x10)
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/* ------------------------------------------------------------------------- */
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/* I2C Master Controller */
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#define I2C_COMMAND (0x00)
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#define I2C_TIMING (0x04)
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#define I2C_TASKLENGTH (0x08) /* High read, low write */
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#define I2C_TASKADDRESS (0x0C) /* High read, low write */
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#define I2C_MONITOR (0x1C)
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#define I2C_SPEED_400 (0x04030404)
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#define I2C_SPEED_100 (0x13121313)
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/* ------------------------------------------------------------------------- */
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/* DMA Controller */
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#define DMA_BASE_WRITE (0x100)
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#define DMA_BASE_READ (0x140)
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#define TS_CONTROL(_io) ((_io)->regs + 0x00)
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#define TS_CONTROL2(_io) ((_io)->regs + 0x04)
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/* ------------------------------------------------------------------------- */
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/* DMA Buffer */
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#define DMA_BUFFER_CONTROL(_dma) ((_dma)->regs + 0x00)
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#define DMA_BUFFER_ACK(_dma) ((_dma)->regs + 0x04)
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#define DMA_BUFFER_CURRENT(_dma) ((_dma)->regs + 0x08)
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#define DMA_BUFFER_SIZE(_dma) ((_dma)->regs + 0x0c)
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/* ------------------------------------------------------------------------- */
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/* CI Interface (only CI-Bridge) */
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#define CI_BASE (0x400)
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#define CI_CONTROL(i) (CI_BASE + (i) * 32 + 0x00)
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#define CI_DO_ATTRIBUTE_RW(i) (CI_BASE + (i) * 32 + 0x04)
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#define CI_DO_IO_RW(i) (CI_BASE + (i) * 32 + 0x08)
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#define CI_READDATA(i) (CI_BASE + (i) * 32 + 0x0c)
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#define CI_DO_READ_ATTRIBUTES(i) (CI_BASE + (i) * 32 + 0x10)
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#define CI_RESET_CAM (0x00000001)
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#define CI_POWER_ON (0x00000002)
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#define CI_ENABLE (0x00000004)
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#define CI_BYPASS_DISABLE (0x00000010)
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#define CI_CAM_READY (0x00010000)
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#define CI_CAM_DETECT (0x00020000)
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#define CI_READY (0x80000000)
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#define CI_READ_CMD (0x40000000)
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#define CI_WRITE_CMD (0x80000000)
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#define CI_BUFFER_BASE (0x3000)
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#define CI_BUFFER_SIZE (0x0800)
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#define CI_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE)
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/* ------------------------------------------------------------------------- */
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/* LNB commands (mxl5xx / Max S8) */
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#define LNB_BASE (0x400)
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#define LNB_CONTROL(i) (LNB_BASE + (i) * 0x20 + 0x00)
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#define LNB_CMD (7ULL << 0)
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#define LNB_CMD_NOP 0
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#define LNB_CMD_INIT 1
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#define LNB_CMD_LOW 3
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#define LNB_CMD_HIGH 4
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#define LNB_CMD_OFF 5
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#define LNB_CMD_DISEQC 6
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#define LNB_BUSY BIT_ULL(4)
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#define LNB_TONE BIT_ULL(15)
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#define LNB_BUF_LEVEL(i) (LNB_BASE + (i) * 0x20 + 0x10)
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#define LNB_BUF_WRITE(i) (LNB_BASE + (i) * 0x20 + 0x14)
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#endif /* __DDBRIDGE_REGS_H__ */
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