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7d3392e546
Ignore drivers/staging/ since it is very likely that new drivers introduce it again. Signed-off-by: Markus Heidelberg <markus.heidelberg@web.de> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
101 lines
2.0 KiB
C
101 lines
2.0 KiB
C
/*
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* linux/arch/h8300/kernel/timer/tpu.c
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*
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* Yoshinori Sato <ysato@users.sourceforge.jp>
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*
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* TPU Timer Handler
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*
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/timex.h>
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#include <asm/segment.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/regs267x.h>
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/* TPU */
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#if CONFIG_H8300_TPU_CH == 0
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#define TPUBASE 0xffffd0
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#define TPUIRQ 40
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#elif CONFIG_H8300_TPU_CH == 1
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#define TPUBASE 0xffffe0
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#define TPUIRQ 48
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#elif CONFIG_H8300_TPU_CH == 2
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#define TPUBASE 0xfffff0
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#define TPUIRQ 52
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#elif CONFIG_H8300_TPU_CH == 3
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#define TPUBASE 0xfffe80
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#define TPUIRQ 56
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#elif CONFIG_H8300_TPU_CH == 4
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#define TPUBASE 0xfffe90
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#define TPUIRQ 64
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#else
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#error Unknown timer channel.
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#endif
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#define _TCR 0
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#define _TMDR 1
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#define _TIOR 2
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#define _TIER 4
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#define _TSR 5
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#define _TCNT 6
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#define _GRA 8
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#define _GRB 10
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#define CCLR0 0x20
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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h8300_timer_tick();
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ctrl_bclr(0, TPUBASE + _TSR);
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return IRQ_HANDLED;
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}
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static struct irqaction tpu_irq = {
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.name = "tpu",
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER,
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};
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static const int __initdata divide_rate[] = {
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#if CONFIG_H8300_TPU_CH == 0
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1,4,16,64,0,0,0,0,
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#elif (CONFIG_H8300_TPU_CH == 1) || (CONFIG_H8300_TPU_CH == 5)
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1,4,16,64,0,0,256,0,
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#elif (CONFIG_H8300_TPU_CH == 2) || (CONFIG_H8300_TPU_CH == 4)
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1,4,16,64,0,0,0,1024,
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#elif CONFIG_H8300_TPU_CH == 3
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1,4,16,64,0,1024,256,4096,
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#endif
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};
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void __init h8300_timer_setup(void)
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{
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unsigned int cnt;
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unsigned int div;
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calc_param(cnt, div, divide_rate, 0x10000);
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setup_irq(TPUIRQ, &tpu_irq);
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/* TPU module enabled */
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ctrl_bclr(3, MSTPCRH);
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ctrl_outb(0, TSTR);
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ctrl_outb(CCLR0 | div, TPUBASE + _TCR);
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ctrl_outb(0, TPUBASE + _TMDR);
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ctrl_outw(0, TPUBASE + _TIOR);
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ctrl_outb(0x01, TPUBASE + _TIER);
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ctrl_outw(cnt, TPUBASE + _GRA);
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ctrl_bset(CONFIG_H8300_TPU_CH, TSTR);
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}
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