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A Flexgen structure is composed by: - a clock cross bar (represented by a mux element) - a pre and final dividers (represented by a divider and gate elements) Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
101 lines
2.0 KiB
Plaintext
101 lines
2.0 KiB
Plaintext
Binding for a Clockgen hardware block found on
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certain STMicroelectronics consumer electronics SoC devices.
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A Clockgen node can contain pll, diviser or multiplexer nodes.
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We will find only the base address of the Clockgen, this base
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address is common of all subnode.
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clockgen_node {
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reg = <>;
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pll_node {
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...
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};
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prediv_node {
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...
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};
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divmux_node {
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...
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};
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quadfs_node {
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...
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};
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mux_node {
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...
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};
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vcc_node {
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...
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};
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flexgen_node {
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...
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};
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...
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};
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This binding uses the common clock binding[1].
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Each subnode should use the binding discribe in [2]..[7]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
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[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
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[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
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[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
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[6] Documentation/devicetree/bindings/clock/st,vcc.txt
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[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
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[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
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Required properties:
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- reg : A Base address and length of the register set.
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Example:
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clockgen-a@fee62000 {
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reg = <0xfee62000 0xb48>;
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,clkgena-plls-c65";
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clocks = <&clk-sysin>;
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clock-output-names = "clk-s-a0-pll0-hs",
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"clk-s-a0-pll0-ls",
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"clk-s-a0-pll1";
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};
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clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c65",
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"st,clkgena-prediv";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-osc-prediv";
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};
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clk_s_a0_hs: clk-s-a0-hs {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c65-hs",
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"st,clkgena-divmux";
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clocks = <&clk-s_a0_osc_prediv>,
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<&clk-s_a0_pll 0>, /* pll0 hs */
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<&clk-s_a0_pll 2>; /* pll1 */
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clock-output-names = "clk-s-fdma-0",
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"clk-s-fdma-1",
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""; /* clk-s-jit-sense */
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/* fourth output unused */
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};
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};
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