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bd0b9ac405
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
913 lines
24 KiB
C
913 lines
24 KiB
C
/*
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* leon_pci_grpci2.c: GRPCI2 Host PCI driver
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*
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* Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
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*
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*/
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#include <linux/of_device.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <asm/io.h>
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#include <asm/leon.h>
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#include <asm/vaddrs.h>
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#include <asm/sections.h>
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#include <asm/leon_pci.h>
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#include "irq.h"
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struct grpci2_barcfg {
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unsigned long pciadr; /* PCI Space Address */
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unsigned long ahbadr; /* PCI Base address mapped to this AHB addr */
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};
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/* Device Node Configuration options:
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* - barcfgs : Custom Configuration of Host's 6 target BARs
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* - irq_mask : Limit which PCI interrupts are enabled
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* - do_reset : Force PCI Reset on startup
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*
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* barcfgs
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* =======
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*
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* Optional custom Target BAR configuration (see struct grpci2_barcfg). All
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* addresses are physical. Array always contains 6 elements (len=2*4*6 bytes)
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*
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* -1 means not configured (let host driver do default setup).
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*
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* [i*2+0] = PCI Address of BAR[i] on target interface
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* [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address
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*
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*
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* irq_mask
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* ========
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*
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* Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
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* all are enabled. Use this when PCI interrupt pins are floating on PCB.
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* int, len=4.
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* bit0 = PCI INTA#
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* bit1 = PCI INTB#
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* bit2 = PCI INTC#
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* bit3 = PCI INTD#
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*
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*
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* reset
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* =====
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*
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* Force PCI reset on startup. int, len=4
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*/
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/* Enable Debugging Configuration Space Access */
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#undef GRPCI2_DEBUG_CFGACCESS
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/*
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* GRPCI2 APB Register MAP
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*/
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struct grpci2_regs {
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unsigned int ctrl; /* 0x00 Control */
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unsigned int sts_cap; /* 0x04 Status / Capabilities */
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int res1; /* 0x08 */
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unsigned int io_map; /* 0x0C I/O Map address */
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unsigned int dma_ctrl; /* 0x10 DMA */
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unsigned int dma_bdbase; /* 0x14 DMA */
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int res2[2]; /* 0x18 */
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unsigned int bars[6]; /* 0x20 read-only PCI BARs */
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int res3[2]; /* 0x38 */
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unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
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/* PCI Trace Buffer Registers (OPTIONAL) */
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unsigned int t_ctrl; /* 0x80 */
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unsigned int t_cnt; /* 0x84 */
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unsigned int t_adpat; /* 0x88 */
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unsigned int t_admask; /* 0x8C */
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unsigned int t_sigpat; /* 0x90 */
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unsigned int t_sigmask; /* 0x94 */
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unsigned int t_adstate; /* 0x98 */
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unsigned int t_sigstate; /* 0x9C */
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};
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#define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
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#define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
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#define CTRL_BUS_BIT 16
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#define CTRL_RESET (1<<31)
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#define CTRL_SI (1<<27)
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#define CTRL_PE (1<<26)
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#define CTRL_EI (1<<25)
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#define CTRL_ER (1<<24)
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#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
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#define CTRL_HOSTINT 0xf
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#define STS_HOST_BIT 31
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#define STS_MST_BIT 30
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#define STS_TAR_BIT 29
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#define STS_DMA_BIT 28
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#define STS_DI_BIT 27
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#define STS_HI_BIT 26
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#define STS_IRQMODE_BIT 24
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#define STS_TRACE_BIT 23
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#define STS_CFGERRVALID_BIT 20
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#define STS_CFGERR_BIT 19
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#define STS_INTTYPE_BIT 12
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#define STS_INTSTS_BIT 8
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#define STS_FDEPTH_BIT 2
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#define STS_FNUM_BIT 0
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#define STS_HOST (1<<STS_HOST_BIT)
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#define STS_MST (1<<STS_MST_BIT)
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#define STS_TAR (1<<STS_TAR_BIT)
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#define STS_DMA (1<<STS_DMA_BIT)
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#define STS_DI (1<<STS_DI_BIT)
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#define STS_HI (1<<STS_HI_BIT)
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#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
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#define STS_TRACE (1<<STS_TRACE_BIT)
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#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
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#define STS_CFGERR (1<<STS_CFGERR_BIT)
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#define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
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#define STS_INTSTS (0xf<<STS_INTSTS_BIT)
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#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
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#define STS_FNUM (0x3<<STS_FNUM_BIT)
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#define STS_ISYSERR (1<<17)
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#define STS_IDMA (1<<16)
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#define STS_IDMAERR (1<<15)
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#define STS_IMSTABRT (1<<14)
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#define STS_ITGTABRT (1<<13)
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#define STS_IPARERR (1<<12)
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#define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR)
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struct grpci2_bd_chan {
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unsigned int ctrl; /* 0x00 DMA Control */
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unsigned int nchan; /* 0x04 Next DMA Channel Address */
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unsigned int nbd; /* 0x08 Next Data Descriptor in chan */
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unsigned int res; /* 0x0C Reserved */
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};
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#define BD_CHAN_EN 0x80000000
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#define BD_CHAN_TYPE 0x00300000
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#define BD_CHAN_BDCNT 0x0000ffff
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#define BD_CHAN_EN_BIT 31
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#define BD_CHAN_TYPE_BIT 20
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#define BD_CHAN_BDCNT_BIT 0
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struct grpci2_bd_data {
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unsigned int ctrl; /* 0x00 DMA Data Control */
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unsigned int pci_adr; /* 0x04 PCI Start Address */
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unsigned int ahb_adr; /* 0x08 AHB Start address */
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unsigned int next; /* 0x0C Next Data Descriptor in chan */
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};
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#define BD_DATA_EN 0x80000000
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#define BD_DATA_IE 0x40000000
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#define BD_DATA_DR 0x20000000
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#define BD_DATA_TYPE 0x00300000
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#define BD_DATA_ER 0x00080000
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#define BD_DATA_LEN 0x0000ffff
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#define BD_DATA_EN_BIT 31
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#define BD_DATA_IE_BIT 30
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#define BD_DATA_DR_BIT 29
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#define BD_DATA_TYPE_BIT 20
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#define BD_DATA_ER_BIT 19
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#define BD_DATA_LEN_BIT 0
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/* GRPCI2 Capability */
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struct grpci2_cap_first {
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unsigned int ctrl;
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unsigned int pci2ahb_map[6];
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unsigned int ext2ahb_map;
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unsigned int io_map;
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unsigned int pcibar_size[6];
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};
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#define CAP9_CTRL_OFS 0
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#define CAP9_BAR_OFS 0x4
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#define CAP9_IOMAP_OFS 0x20
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#define CAP9_BARSIZE_OFS 0x24
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#define TGT 256
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struct grpci2_priv {
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struct leon_pci_info info; /* must be on top of this structure */
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struct grpci2_regs __iomem *regs;
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char irq;
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char irq_mode; /* IRQ Mode from CAPSTS REG */
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char bt_enabled;
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char do_reset;
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char irq_mask;
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u32 pciid; /* PCI ID of Host */
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unsigned char irq_map[4];
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/* Virtual IRQ numbers */
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unsigned int virq_err;
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unsigned int virq_dma;
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/* AHB PCI Windows */
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unsigned long pci_area; /* MEMORY */
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unsigned long pci_area_end;
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unsigned long pci_io; /* I/O */
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unsigned long pci_conf; /* CONFIGURATION */
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unsigned long pci_conf_end;
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unsigned long pci_io_va;
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struct grpci2_barcfg tgtbars[6];
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};
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static DEFINE_SPINLOCK(grpci2_dev_lock);
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static struct grpci2_priv *grpci2priv;
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static int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct grpci2_priv *priv = dev->bus->sysdata;
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int irq_group;
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/* Use default IRQ decoding on PCI BUS0 according slot numbering */
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irq_group = slot & 0x3;
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pin = ((pin - 1) + irq_group) & 0x3;
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return priv->irq_map[pin];
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}
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static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
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unsigned int devfn, int where, u32 *val)
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{
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unsigned int *pci_conf;
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unsigned long flags;
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u32 tmp;
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if (where & 0x3)
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return -EINVAL;
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if (bus == 0) {
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devfn += (0x8 * 6); /* start at AD16=Device0 */
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} else if (bus == TGT) {
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bus = 0;
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devfn = 0; /* special case: bridge controller itself */
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}
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/* Select bus */
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spin_lock_irqsave(&grpci2_dev_lock, flags);
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REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
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(bus << 16));
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spin_unlock_irqrestore(&grpci2_dev_lock, flags);
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/* clear old status */
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REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
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pci_conf = (unsigned int *) (priv->pci_conf |
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(devfn << 8) | (where & 0xfc));
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tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
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/* Wait until GRPCI2 signals that CFG access is done, it should be
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* done instantaneously unless a DMA operation is ongoing...
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*/
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while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
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;
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if (REGLOAD(priv->regs->sts_cap) & STS_CFGERR) {
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*val = 0xffffffff;
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} else {
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/* Bus always little endian (unaffected by byte-swapping) */
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*val = swab32(tmp);
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}
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return 0;
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}
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static int grpci2_cfg_r16(struct grpci2_priv *priv, unsigned int bus,
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unsigned int devfn, int where, u32 *val)
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{
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u32 v;
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int ret;
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if (where & 0x1)
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return -EINVAL;
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ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
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*val = 0xffff & (v >> (8 * (where & 0x3)));
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return ret;
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}
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static int grpci2_cfg_r8(struct grpci2_priv *priv, unsigned int bus,
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unsigned int devfn, int where, u32 *val)
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{
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u32 v;
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int ret;
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ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
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*val = 0xff & (v >> (8 * (where & 3)));
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return ret;
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}
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static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus,
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unsigned int devfn, int where, u32 val)
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{
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unsigned int *pci_conf;
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unsigned long flags;
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if (where & 0x3)
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return -EINVAL;
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if (bus == 0) {
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devfn += (0x8 * 6); /* start at AD16=Device0 */
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} else if (bus == TGT) {
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bus = 0;
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devfn = 0; /* special case: bridge controller itself */
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}
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/* Select bus */
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spin_lock_irqsave(&grpci2_dev_lock, flags);
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REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) |
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(bus << 16));
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spin_unlock_irqrestore(&grpci2_dev_lock, flags);
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/* clear old status */
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REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID));
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pci_conf = (unsigned int *) (priv->pci_conf |
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(devfn << 8) | (where & 0xfc));
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LEON3_BYPASS_STORE_PA(pci_conf, swab32(val));
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/* Wait until GRPCI2 signals that CFG access is done, it should be
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* done instantaneously unless a DMA operation is ongoing...
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*/
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while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0)
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;
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return 0;
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}
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static int grpci2_cfg_w16(struct grpci2_priv *priv, unsigned int bus,
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unsigned int devfn, int where, u32 val)
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{
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int ret;
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u32 v;
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if (where & 0x1)
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return -EINVAL;
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ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v);
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if (ret)
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return ret;
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v = (v & ~(0xffff << (8 * (where & 0x3)))) |
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((0xffff & val) << (8 * (where & 0x3)));
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return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
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}
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static int grpci2_cfg_w8(struct grpci2_priv *priv, unsigned int bus,
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unsigned int devfn, int where, u32 val)
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{
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int ret;
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u32 v;
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ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
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if (ret != 0)
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return ret;
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v = (v & ~(0xff << (8 * (where & 0x3)))) |
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((0xff & val) << (8 * (where & 0x3)));
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return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
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}
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/* Read from Configuration Space. When entering here the PCI layer has taken
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* the pci_lock spinlock and IRQ is off.
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*/
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static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct grpci2_priv *priv = grpci2priv;
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unsigned int busno = bus->number;
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int ret;
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if (PCI_SLOT(devfn) > 15 || busno > 255) {
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*val = ~0;
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return 0;
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}
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switch (size) {
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case 1:
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ret = grpci2_cfg_r8(priv, busno, devfn, where, val);
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break;
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case 2:
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ret = grpci2_cfg_r16(priv, busno, devfn, where, val);
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break;
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case 4:
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ret = grpci2_cfg_r32(priv, busno, devfn, where, val);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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#ifdef GRPCI2_DEBUG_CFGACCESS
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printk(KERN_INFO "grpci2_read_config: [%02x:%02x:%x] ofs=%d val=%x "
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"size=%d\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where,
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*val, size);
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#endif
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return ret;
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}
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/* Write to Configuration Space. When entering here the PCI layer has taken
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* the pci_lock spinlock and IRQ is off.
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*/
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static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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struct grpci2_priv *priv = grpci2priv;
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unsigned int busno = bus->number;
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if (PCI_SLOT(devfn) > 15 || busno > 255)
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return 0;
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#ifdef GRPCI2_DEBUG_CFGACCESS
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printk(KERN_INFO "grpci2_write_config: [%02x:%02x:%x] ofs=%d size=%d "
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"val=%x\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn),
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where, size, val);
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#endif
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switch (size) {
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default:
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return -EINVAL;
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case 1:
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return grpci2_cfg_w8(priv, busno, devfn, where, val);
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case 2:
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return grpci2_cfg_w16(priv, busno, devfn, where, val);
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case 4:
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return grpci2_cfg_w32(priv, busno, devfn, where, val);
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}
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}
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static struct pci_ops grpci2_ops = {
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.read = grpci2_read_config,
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.write = grpci2_write_config,
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};
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/* GENIRQ IRQ chip implementation for GRPCI2 irqmode=0..2. In configuration
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* 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
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* this is not needed and the standard IRQ controller can be used.
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*/
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static void grpci2_mask_irq(struct irq_data *data)
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{
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unsigned long flags;
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unsigned int irqidx;
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struct grpci2_priv *priv = grpci2priv;
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irqidx = (unsigned int)data->chip_data - 1;
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if (irqidx > 3) /* only mask PCI interrupts here */
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return;
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spin_lock_irqsave(&grpci2_dev_lock, flags);
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REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx));
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spin_unlock_irqrestore(&grpci2_dev_lock, flags);
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}
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static void grpci2_unmask_irq(struct irq_data *data)
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{
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unsigned long flags;
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unsigned int irqidx;
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struct grpci2_priv *priv = grpci2priv;
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irqidx = (unsigned int)data->chip_data - 1;
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if (irqidx > 3) /* only unmask PCI interrupts here */
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return;
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spin_lock_irqsave(&grpci2_dev_lock, flags);
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REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx));
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spin_unlock_irqrestore(&grpci2_dev_lock, flags);
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}
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|
|
static unsigned int grpci2_startup_irq(struct irq_data *data)
|
|
{
|
|
grpci2_unmask_irq(data);
|
|
return 0;
|
|
}
|
|
|
|
static void grpci2_shutdown_irq(struct irq_data *data)
|
|
{
|
|
grpci2_mask_irq(data);
|
|
}
|
|
|
|
static struct irq_chip grpci2_irq = {
|
|
.name = "grpci2",
|
|
.irq_startup = grpci2_startup_irq,
|
|
.irq_shutdown = grpci2_shutdown_irq,
|
|
.irq_mask = grpci2_mask_irq,
|
|
.irq_unmask = grpci2_unmask_irq,
|
|
};
|
|
|
|
/* Handle one or multiple IRQs from the PCI core */
|
|
static void grpci2_pci_flow_irq(struct irq_desc *desc)
|
|
{
|
|
struct grpci2_priv *priv = grpci2priv;
|
|
int i, ack = 0;
|
|
unsigned int ctrl, sts_cap, pci_ints;
|
|
|
|
ctrl = REGLOAD(priv->regs->ctrl);
|
|
sts_cap = REGLOAD(priv->regs->sts_cap);
|
|
|
|
/* Error Interrupt? */
|
|
if (sts_cap & STS_ERR_IRQ) {
|
|
generic_handle_irq(priv->virq_err);
|
|
ack = 1;
|
|
}
|
|
|
|
/* PCI Interrupt? */
|
|
pci_ints = ((~sts_cap) >> STS_INTSTS_BIT) & ctrl & CTRL_HOSTINT;
|
|
if (pci_ints) {
|
|
/* Call respective PCI Interrupt handler */
|
|
for (i = 0; i < 4; i++) {
|
|
if (pci_ints & (1 << i))
|
|
generic_handle_irq(priv->irq_map[i]);
|
|
}
|
|
ack = 1;
|
|
}
|
|
|
|
/*
|
|
* Decode DMA Interrupt only when shared with Err and PCI INTX#, when
|
|
* the DMA is a unique IRQ the DMA interrupts doesn't end up here, they
|
|
* goes directly to DMA ISR.
|
|
*/
|
|
if ((priv->irq_mode == 0) && (sts_cap & (STS_IDMA | STS_IDMAERR))) {
|
|
generic_handle_irq(priv->virq_dma);
|
|
ack = 1;
|
|
}
|
|
|
|
/*
|
|
* Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
|
|
* Controller, this must be done after IRQ sources have been handled to
|
|
* avoid double IRQ generation
|
|
*/
|
|
if (ack)
|
|
desc->irq_data.chip->irq_eoi(&desc->irq_data);
|
|
}
|
|
|
|
/* Create a virtual IRQ */
|
|
static unsigned int grpci2_build_device_irq(unsigned int irq)
|
|
{
|
|
unsigned int virq = 0, pil;
|
|
|
|
pil = 1 << 8;
|
|
virq = irq_alloc(irq, pil);
|
|
if (virq == 0)
|
|
goto out;
|
|
|
|
irq_set_chip_and_handler_name(virq, &grpci2_irq, handle_simple_irq,
|
|
"pcilvl");
|
|
irq_set_chip_data(virq, (void *)irq);
|
|
|
|
out:
|
|
return virq;
|
|
}
|
|
|
|
static void grpci2_hw_init(struct grpci2_priv *priv)
|
|
{
|
|
u32 ahbadr, pciadr, bar_sz, capptr, io_map, data;
|
|
struct grpci2_regs __iomem *regs = priv->regs;
|
|
int i;
|
|
struct grpci2_barcfg *barcfg = priv->tgtbars;
|
|
|
|
/* Reset any earlier setup */
|
|
if (priv->do_reset) {
|
|
printk(KERN_INFO "GRPCI2: Resetting PCI bus\n");
|
|
REGSTORE(regs->ctrl, CTRL_RESET);
|
|
ssleep(1); /* Wait for boards to settle */
|
|
}
|
|
REGSTORE(regs->ctrl, 0);
|
|
REGSTORE(regs->sts_cap, ~0); /* Clear Status */
|
|
REGSTORE(regs->dma_ctrl, 0);
|
|
REGSTORE(regs->dma_bdbase, 0);
|
|
|
|
/* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
|
|
REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff);
|
|
|
|
/* set 1:1 mapping between AHB -> PCI memory space, for all Masters
|
|
* Each AHB master has it's own mapping registers. Max 16 AHB masters.
|
|
*/
|
|
for (i = 0; i < 16; i++)
|
|
REGSTORE(regs->ahbmst_map[i], priv->pci_area);
|
|
|
|
/* Get the GRPCI2 Host PCI ID */
|
|
grpci2_cfg_r32(priv, TGT, 0, PCI_VENDOR_ID, &priv->pciid);
|
|
|
|
/* Get address to first (always defined) capability structure */
|
|
grpci2_cfg_r8(priv, TGT, 0, PCI_CAPABILITY_LIST, &capptr);
|
|
|
|
/* Enable/Disable Byte twisting */
|
|
grpci2_cfg_r32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, &io_map);
|
|
io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
|
|
grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, io_map);
|
|
|
|
/* Setup the Host's PCI Target BARs for other peripherals to access,
|
|
* and do DMA to the host's memory. The target BARs can be sized and
|
|
* enabled individually.
|
|
*
|
|
* User may set custom target BARs, but default is:
|
|
* The first BARs is used to map kernel low (DMA is part of normal
|
|
* region on sparc which is SRMMU_MAXMEM big) main memory 1:1 to the
|
|
* PCI bus, the other BARs are disabled. We assume that the first BAR
|
|
* is always available.
|
|
*/
|
|
for (i = 0; i < 6; i++) {
|
|
if (barcfg[i].pciadr != ~0 && barcfg[i].ahbadr != ~0) {
|
|
/* Target BARs must have the proper alignment */
|
|
ahbadr = barcfg[i].ahbadr;
|
|
pciadr = barcfg[i].pciadr;
|
|
bar_sz = ((pciadr - 1) & ~pciadr) + 1;
|
|
} else {
|
|
if (i == 0) {
|
|
/* Map main memory */
|
|
bar_sz = 0xf0000008; /* 256MB prefetchable */
|
|
ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN(
|
|
(unsigned long) &_end));
|
|
pciadr = ahbadr;
|
|
} else {
|
|
bar_sz = 0;
|
|
ahbadr = 0;
|
|
pciadr = 0;
|
|
}
|
|
}
|
|
grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BARSIZE_OFS+i*4,
|
|
bar_sz);
|
|
grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
|
|
grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
|
|
printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n",
|
|
i, pciadr, ahbadr);
|
|
}
|
|
|
|
/* set as bus master and enable pci memory responses */
|
|
grpci2_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
|
|
data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
grpci2_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
|
|
|
|
/* Enable Error respone (CPU-TRAP) on illegal memory access. */
|
|
REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);
|
|
}
|
|
|
|
static irqreturn_t grpci2_jump_interrupt(int irq, void *arg)
|
|
{
|
|
printk(KERN_ERR "GRPCI2: Jump IRQ happened\n");
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
/* Handle GRPCI2 Error Interrupt */
|
|
static irqreturn_t grpci2_err_interrupt(int irq, void *arg)
|
|
{
|
|
struct grpci2_priv *priv = arg;
|
|
struct grpci2_regs __iomem *regs = priv->regs;
|
|
unsigned int status;
|
|
|
|
status = REGLOAD(regs->sts_cap);
|
|
if ((status & STS_ERR_IRQ) == 0)
|
|
return IRQ_NONE;
|
|
|
|
if (status & STS_IPARERR)
|
|
printk(KERN_ERR "GRPCI2: Parity Error\n");
|
|
|
|
if (status & STS_ITGTABRT)
|
|
printk(KERN_ERR "GRPCI2: Target Abort\n");
|
|
|
|
if (status & STS_IMSTABRT)
|
|
printk(KERN_ERR "GRPCI2: Master Abort\n");
|
|
|
|
if (status & STS_ISYSERR)
|
|
printk(KERN_ERR "GRPCI2: System Error\n");
|
|
|
|
/* Clear handled INT TYPE IRQs */
|
|
REGSTORE(regs->sts_cap, status & STS_ERR_IRQ);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int grpci2_of_probe(struct platform_device *ofdev)
|
|
{
|
|
struct grpci2_regs __iomem *regs;
|
|
struct grpci2_priv *priv;
|
|
int err, i, len;
|
|
const int *tmp;
|
|
unsigned int capability;
|
|
|
|
if (grpci2priv) {
|
|
printk(KERN_ERR "GRPCI2: only one GRPCI2 core supported\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (ofdev->num_resources < 3) {
|
|
printk(KERN_ERR "GRPCI2: not enough APB/AHB resources\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/* Find Device Address */
|
|
regs = of_ioremap(&ofdev->resource[0], 0,
|
|
resource_size(&ofdev->resource[0]),
|
|
"grlib-grpci2 regs");
|
|
if (regs == NULL) {
|
|
printk(KERN_ERR "GRPCI2: ioremap failed\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/*
|
|
* Check that we're in Host Slot and that we can act as a Host Bridge
|
|
* and not only as target.
|
|
*/
|
|
capability = REGLOAD(regs->sts_cap);
|
|
if ((capability & STS_HOST) || !(capability & STS_MST)) {
|
|
printk(KERN_INFO "GRPCI2: not in host system slot\n");
|
|
err = -EIO;
|
|
goto err1;
|
|
}
|
|
|
|
priv = grpci2priv = kzalloc(sizeof(struct grpci2_priv), GFP_KERNEL);
|
|
if (grpci2priv == NULL) {
|
|
err = -ENOMEM;
|
|
goto err1;
|
|
}
|
|
priv->regs = regs;
|
|
priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */
|
|
priv->irq_mode = (capability & STS_IRQMODE) >> STS_IRQMODE_BIT;
|
|
|
|
printk(KERN_INFO "GRPCI2: host found at %p, irq%d\n", regs, priv->irq);
|
|
|
|
/* Byte twisting should be made configurable from kernel command line */
|
|
priv->bt_enabled = 1;
|
|
|
|
/* Let user do custom Target BAR assignment */
|
|
tmp = of_get_property(ofdev->dev.of_node, "barcfg", &len);
|
|
if (tmp && (len == 2*4*6))
|
|
memcpy(priv->tgtbars, tmp, 2*4*6);
|
|
else
|
|
memset(priv->tgtbars, -1, 2*4*6);
|
|
|
|
/* Limit IRQ unmasking in irq_mode 2 and 3 */
|
|
tmp = of_get_property(ofdev->dev.of_node, "irq_mask", &len);
|
|
if (tmp && (len == 4))
|
|
priv->do_reset = *tmp;
|
|
else
|
|
priv->irq_mask = 0xf;
|
|
|
|
/* Optional PCI reset. Force PCI reset on startup */
|
|
tmp = of_get_property(ofdev->dev.of_node, "reset", &len);
|
|
if (tmp && (len == 4))
|
|
priv->do_reset = *tmp;
|
|
else
|
|
priv->do_reset = 0;
|
|
|
|
/* Find PCI Memory, I/O and Configuration Space Windows */
|
|
priv->pci_area = ofdev->resource[1].start;
|
|
priv->pci_area_end = ofdev->resource[1].end+1;
|
|
priv->pci_io = ofdev->resource[2].start;
|
|
priv->pci_conf = ofdev->resource[2].start + 0x10000;
|
|
priv->pci_conf_end = priv->pci_conf + 0x10000;
|
|
priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
|
|
if (!priv->pci_io_va) {
|
|
err = -EIO;
|
|
goto err2;
|
|
}
|
|
|
|
printk(KERN_INFO
|
|
"GRPCI2: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
|
|
" I/O SPACE [0x%08lx - 0x%08lx]\n"
|
|
" CONFIG SPACE [0x%08lx - 0x%08lx]\n",
|
|
priv->pci_area, priv->pci_area_end-1,
|
|
priv->pci_io, priv->pci_conf-1,
|
|
priv->pci_conf, priv->pci_conf_end-1);
|
|
|
|
/*
|
|
* I/O Space resources in I/O Window mapped into Virtual Adr Space
|
|
* We never use low 4KB because some devices seem have problems using
|
|
* address 0.
|
|
*/
|
|
memset(&priv->info.io_space, 0, sizeof(struct resource));
|
|
priv->info.io_space.name = "GRPCI2 PCI I/O Space";
|
|
priv->info.io_space.start = priv->pci_io_va + 0x1000;
|
|
priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
|
|
priv->info.io_space.flags = IORESOURCE_IO;
|
|
|
|
/*
|
|
* GRPCI2 has no prefetchable memory, map everything as
|
|
* non-prefetchable memory
|
|
*/
|
|
memset(&priv->info.mem_space, 0, sizeof(struct resource));
|
|
priv->info.mem_space.name = "GRPCI2 PCI MEM Space";
|
|
priv->info.mem_space.start = priv->pci_area;
|
|
priv->info.mem_space.end = priv->pci_area_end - 1;
|
|
priv->info.mem_space.flags = IORESOURCE_MEM;
|
|
|
|
if (request_resource(&iomem_resource, &priv->info.mem_space) < 0)
|
|
goto err3;
|
|
if (request_resource(&ioport_resource, &priv->info.io_space) < 0)
|
|
goto err4;
|
|
|
|
/* setup maximum supported PCI buses */
|
|
priv->info.busn.name = "GRPCI2 busn";
|
|
priv->info.busn.start = 0;
|
|
priv->info.busn.end = 255;
|
|
|
|
grpci2_hw_init(priv);
|
|
|
|
/*
|
|
* Get PCI Interrupt to System IRQ mapping and setup IRQ handling
|
|
* Error IRQ always on PCI INTA.
|
|
*/
|
|
if (priv->irq_mode < 2) {
|
|
/* All PCI interrupts are shared using the same system IRQ */
|
|
leon_update_virq_handling(priv->irq, grpci2_pci_flow_irq,
|
|
"pcilvl", 0);
|
|
|
|
priv->irq_map[0] = grpci2_build_device_irq(1);
|
|
priv->irq_map[1] = grpci2_build_device_irq(2);
|
|
priv->irq_map[2] = grpci2_build_device_irq(3);
|
|
priv->irq_map[3] = grpci2_build_device_irq(4);
|
|
|
|
priv->virq_err = grpci2_build_device_irq(5);
|
|
if (priv->irq_mode & 1)
|
|
priv->virq_dma = ofdev->archdata.irqs[1];
|
|
else
|
|
priv->virq_dma = grpci2_build_device_irq(6);
|
|
|
|
/* Enable IRQs on LEON IRQ controller */
|
|
err = request_irq(priv->irq, grpci2_jump_interrupt, 0,
|
|
"GRPCI2_JUMP", priv);
|
|
if (err)
|
|
printk(KERN_ERR "GRPCI2: ERR IRQ request failed\n");
|
|
} else {
|
|
/* All PCI interrupts have an unique IRQ interrupt */
|
|
for (i = 0; i < 4; i++) {
|
|
/* Make LEON IRQ layer handle level IRQ by acking */
|
|
leon_update_virq_handling(ofdev->archdata.irqs[i],
|
|
handle_fasteoi_irq, "pcilvl",
|
|
1);
|
|
priv->irq_map[i] = ofdev->archdata.irqs[i];
|
|
}
|
|
priv->virq_err = priv->irq_map[0];
|
|
if (priv->irq_mode & 1)
|
|
priv->virq_dma = ofdev->archdata.irqs[4];
|
|
else
|
|
priv->virq_dma = priv->irq_map[0];
|
|
|
|
/* Unmask all PCI interrupts, request_irq will not do that */
|
|
REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf));
|
|
}
|
|
|
|
/* Setup IRQ handler for non-configuration space access errors */
|
|
err = request_irq(priv->virq_err, grpci2_err_interrupt, IRQF_SHARED,
|
|
"GRPCI2_ERR", priv);
|
|
if (err) {
|
|
printk(KERN_DEBUG "GRPCI2: ERR VIRQ request failed: %d\n", err);
|
|
goto err5;
|
|
}
|
|
|
|
/*
|
|
* Enable Error Interrupts. PCI interrupts are unmasked once request_irq
|
|
* is called by the PCI Device drivers
|
|
*/
|
|
REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI);
|
|
|
|
/* Init common layer and scan buses */
|
|
priv->info.ops = &grpci2_ops;
|
|
priv->info.map_irq = grpci2_map_irq;
|
|
leon_pci_init(ofdev, &priv->info);
|
|
|
|
return 0;
|
|
|
|
err5:
|
|
release_resource(&priv->info.io_space);
|
|
err4:
|
|
release_resource(&priv->info.mem_space);
|
|
err3:
|
|
err = -ENOMEM;
|
|
iounmap((void __iomem *)priv->pci_io_va);
|
|
err2:
|
|
kfree(priv);
|
|
err1:
|
|
of_iounmap(&ofdev->resource[0], regs,
|
|
resource_size(&ofdev->resource[0]));
|
|
return err;
|
|
}
|
|
|
|
static struct of_device_id grpci2_of_match[] = {
|
|
{
|
|
.name = "GAISLER_GRPCI2",
|
|
},
|
|
{
|
|
.name = "01_07c",
|
|
},
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver grpci2_of_driver = {
|
|
.driver = {
|
|
.name = "grpci2",
|
|
.of_match_table = grpci2_of_match,
|
|
},
|
|
.probe = grpci2_of_probe,
|
|
};
|
|
|
|
static int __init grpci2_init(void)
|
|
{
|
|
return platform_driver_register(&grpci2_of_driver);
|
|
}
|
|
|
|
subsys_initcall(grpci2_init);
|