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76c6217c31
Add reset, clk dt bindings headers, and update compatible support for AST2700 clk, silicon-id in yaml. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20241023090153.1395220-2-ryan_chen@aspeedtech.com Signed-off-by: Lee Jones <lee@kernel.org>
164 lines
4.7 KiB
C
164 lines
4.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Device Tree binding constants for AST2700 clock controller.
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*
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* Copyright (c) 2024 Aspeed Technology Inc.
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*/
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#ifndef __DT_BINDINGS_CLOCK_AST2700_H
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#define __DT_BINDINGS_CLOCK_AST2700_H
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/* SOC0 clk */
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#define SCU0_CLKIN 0
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#define SCU0_CLK_24M 1
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#define SCU0_CLK_192M 2
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#define SCU0_CLK_UART 3
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#define SCU0_CLK_UART_DIV13 3
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#define SCU0_CLK_PSP 4
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#define SCU0_CLK_HPLL 5
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#define SCU0_CLK_HPLL_DIV2 6
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#define SCU0_CLK_HPLL_DIV4 7
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#define SCU0_CLK_HPLL_DIV_AHB 8
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#define SCU0_CLK_DPLL 9
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#define SCU0_CLK_MPLL 10
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#define SCU0_CLK_MPLL_DIV2 11
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#define SCU0_CLK_MPLL_DIV4 12
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#define SCU0_CLK_MPLL_DIV8 13
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#define SCU0_CLK_MPLL_DIV_AHB 14
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#define SCU0_CLK_D0 15
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#define SCU0_CLK_D1 16
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#define SCU0_CLK_CRT0 17
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#define SCU0_CLK_CRT1 18
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#define SCU0_CLK_MPHY 19
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#define SCU0_CLK_AXI0 20
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#define SCU0_CLK_AXI1 21
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#define SCU0_CLK_AHB 22
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#define SCU0_CLK_APB 23
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#define SCU0_CLK_UART4 24
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#define SCU0_CLK_EMMCMUX 25
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#define SCU0_CLK_EMMC 26
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#define SCU0_CLK_U2PHY_CLK12M 27
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#define SCU0_CLK_U2PHY_REFCLK 28
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/* SOC0 clk-gate */
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#define SCU0_CLK_GATE_MCLK 29
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#define SCU0_CLK_GATE_ECLK 30
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#define SCU0_CLK_GATE_2DCLK 31
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#define SCU0_CLK_GATE_VCLK 32
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#define SCU0_CLK_GATE_BCLK 33
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#define SCU0_CLK_GATE_VGA0CLK 34
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#define SCU0_CLK_GATE_REFCLK 35
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#define SCU0_CLK_GATE_PORTBUSB2CLK 36
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#define SCU0_CLK_GATE_UHCICLK 37
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#define SCU0_CLK_GATE_VGA1CLK 38
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#define SCU0_CLK_GATE_DDRPHYCLK 39
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#define SCU0_CLK_GATE_E2M0CLK 40
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#define SCU0_CLK_GATE_HACCLK 41
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#define SCU0_CLK_GATE_PORTAUSB2CLK 42
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#define SCU0_CLK_GATE_UART4CLK 43
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#define SCU0_CLK_GATE_SLICLK 44
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#define SCU0_CLK_GATE_DACCLK 45
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#define SCU0_CLK_GATE_DP 46
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#define SCU0_CLK_GATE_E2M1CLK 47
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#define SCU0_CLK_GATE_CRT0CLK 48
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#define SCU0_CLK_GATE_CRT1CLK 49
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#define SCU0_CLK_GATE_ECDSACLK 50
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#define SCU0_CLK_GATE_RSACLK 51
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#define SCU0_CLK_GATE_RVAS0CLK 52
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#define SCU0_CLK_GATE_UFSCLK 53
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#define SCU0_CLK_GATE_EMMCCLK 54
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#define SCU0_CLK_GATE_RVAS1CLK 55
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/* SOC1 clk */
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#define SCU1_CLKIN 0
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#define SCU1_CLK_HPLL 1
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#define SCU1_CLK_APLL 2
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#define SCU1_CLK_APLL_DIV2 3
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#define SCU1_CLK_APLL_DIV4 4
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#define SCU1_CLK_DPLL 5
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#define SCU1_CLK_UXCLK 6
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#define SCU1_CLK_HUXCLK 7
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#define SCU1_CLK_UARTX 8
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#define SCU1_CLK_HUARTX 9
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#define SCU1_CLK_AHB 10
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#define SCU1_CLK_APB 11
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#define SCU1_CLK_UART0 12
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#define SCU1_CLK_UART1 13
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#define SCU1_CLK_UART2 14
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#define SCU1_CLK_UART3 15
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#define SCU1_CLK_UART5 16
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#define SCU1_CLK_UART6 17
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#define SCU1_CLK_UART7 18
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#define SCU1_CLK_UART8 19
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#define SCU1_CLK_UART9 20
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#define SCU1_CLK_UART10 21
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#define SCU1_CLK_UART11 22
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#define SCU1_CLK_UART12 23
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#define SCU1_CLK_UART13 24
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#define SCU1_CLK_UART14 25
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#define SCU1_CLK_APLL_DIVN 26
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#define SCU1_CLK_SDMUX 27
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#define SCU1_CLK_SDCLK 28
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#define SCU1_CLK_RMII 29
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#define SCU1_CLK_RGMII 30
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#define SCU1_CLK_MACHCLK 31
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#define SCU1_CLK_MAC0RCLK 32
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#define SCU1_CLK_MAC1RCLK 33
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#define SCU1_CLK_CAN 34
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/* SOC1 clk gate */
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#define SCU1_CLK_GATE_LCLK0 35
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#define SCU1_CLK_GATE_LCLK1 36
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#define SCU1_CLK_GATE_ESPI0CLK 37
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#define SCU1_CLK_GATE_ESPI1CLK 38
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#define SCU1_CLK_GATE_SDCLK 39
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#define SCU1_CLK_GATE_IPEREFCLK 40
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#define SCU1_CLK_GATE_REFCLK 41
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#define SCU1_CLK_GATE_LPCHCLK 42
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#define SCU1_CLK_GATE_MAC0CLK 43
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#define SCU1_CLK_GATE_MAC1CLK 44
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#define SCU1_CLK_GATE_MAC2CLK 45
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#define SCU1_CLK_GATE_UART0CLK 46
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#define SCU1_CLK_GATE_UART1CLK 47
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#define SCU1_CLK_GATE_UART2CLK 48
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#define SCU1_CLK_GATE_UART3CLK 49
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#define SCU1_CLK_GATE_I2CCLK 50
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#define SCU1_CLK_GATE_I3C0CLK 51
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#define SCU1_CLK_GATE_I3C1CLK 52
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#define SCU1_CLK_GATE_I3C2CLK 53
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#define SCU1_CLK_GATE_I3C3CLK 54
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#define SCU1_CLK_GATE_I3C4CLK 55
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#define SCU1_CLK_GATE_I3C5CLK 56
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#define SCU1_CLK_GATE_I3C6CLK 57
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#define SCU1_CLK_GATE_I3C7CLK 58
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#define SCU1_CLK_GATE_I3C8CLK 59
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#define SCU1_CLK_GATE_I3C9CLK 60
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#define SCU1_CLK_GATE_I3C10CLK 61
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#define SCU1_CLK_GATE_I3C11CLK 62
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#define SCU1_CLK_GATE_I3C12CLK 63
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#define SCU1_CLK_GATE_I3C13CLK 64
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#define SCU1_CLK_GATE_I3C14CLK 65
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#define SCU1_CLK_GATE_I3C15CLK 66
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#define SCU1_CLK_GATE_UART5CLK 67
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#define SCU1_CLK_GATE_UART6CLK 68
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#define SCU1_CLK_GATE_UART7CLK 69
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#define SCU1_CLK_GATE_UART8CLK 70
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#define SCU1_CLK_GATE_UART9CLK 71
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#define SCU1_CLK_GATE_UART10CLK 72
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#define SCU1_CLK_GATE_UART11CLK 73
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#define SCU1_CLK_GATE_UART12CLK 74
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#define SCU1_CLK_GATE_FSICLK 75
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#define SCU1_CLK_GATE_LTPIPHYCLK 76
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#define SCU1_CLK_GATE_LTPICLK 77
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#define SCU1_CLK_GATE_VGALCLK 78
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#define SCU1_CLK_GATE_UHCICLK 79
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#define SCU1_CLK_GATE_CANCLK 80
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#define SCU1_CLK_GATE_PCICLK 81
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#define SCU1_CLK_GATE_SLICLK 82
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#define SCU1_CLK_GATE_E2MCLK 83
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#define SCU1_CLK_GATE_PORTCUSB2CLK 84
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#define SCU1_CLK_GATE_PORTDUSB2CLK 85
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#define SCU1_CLK_GATE_LTPI1TXCLK 86
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#endif
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