Huacai Chen f339bd3b51 Docs/LoongArch: Add advanced extended IRQ model description ... Introduce the advanced extended interrupt controllers (AVECINTC). This feature will allow each core to have 256 independent interrupt vectors and MSI interrupts can be independently routed to any vector on any CPU. The whole topology of irqchips in LoongArch machines looks like this if AVECINTC is supported: +-----+ +-----------------------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +-----------------------+ +-------+ ^ ^ ^ | | | +---------+ +----------+ +---------+ +-------+ | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | +---------+ +----------+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | Devices | | PCH-LPC | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+ Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>		2024-09-24 15:32:20 +08:00
..
arm	arm: docs: Move Arm documentation to Documentation/arch/	2023-06-12 06:33:40 -06:00
arm64	docs: arm64: Move arm64 documentation under Documentation/arch/	2023-06-21 08:51:51 -06:00
loongarch	Docs/LoongArch: Add advanced extended IRQ model description	2024-09-24 15:32:20 +08:00
mips	docs: kernel_feat.py: fix potential command injection	2024-01-11 09:21:01 -07:00
openrisc
parisc	docs: move parisc documentation under Documentation/arch/	2023-04-10 16:45:52 -06:00
riscv	Translated the RISC-V architecture boot documentation.	2024-01-03 14:29:28 -07:00
index.rst	The number of commits for documentation is not huge this time around, but	2023-11-01 17:11:41 -10:00