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Support official HID GOOG0016 for ChromeOS ACPI (see [1]). [1]: https://crrev.com/c/2266713 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Muhammad Usama Anjum <usama.anjum@collabora.com> Reviewed-by: Guenter Roeck <groeck@chromium.org> Link: https://lore.kernel.org/r/20230731024214.908235-1-tzungbi@kernel.org Signed-off-by: Tzung-Bi Shih <tzungbi@kernel.org>
363 lines
8.7 KiB
ReStructuredText
363 lines
8.7 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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=====================
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Chrome OS ACPI Device
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=====================
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Hardware functionality specific to Chrome OS is exposed through a Chrome OS ACPI device.
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The plug and play ID of a Chrome OS ACPI device is GGL0001 and the hardware ID is
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GOOG0016. The following ACPI objects are supported:
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.. flat-table:: Supported ACPI Objects
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:widths: 1 2
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:header-rows: 1
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* - Object
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- Description
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* - CHSW
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- Chrome OS switch positions
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* - HWID
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- Chrome OS hardware ID
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* - FWID
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- Chrome OS firmware version
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* - FRID
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- Chrome OS read-only firmware version
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* - BINF
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- Chrome OS boot information
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* - GPIO
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- Chrome OS GPIO assignments
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* - VBNV
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- Chrome OS NVRAM locations
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* - VDTA
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- Chrome OS verified boot data
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* - FMAP
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- Chrome OS flashmap base address
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* - MLST
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- Chrome OS method list
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CHSW (Chrome OS switch positions)
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=================================
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This control method returns the switch positions for Chrome OS specific hardware switches.
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Arguments:
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----------
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None
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Result code:
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------------
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An integer containing the switch positions as bitfields:
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.. flat-table::
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:widths: 1 2
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* - 0x00000002
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- Recovery button was pressed when x86 firmware booted.
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* - 0x00000004
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- Recovery button was pressed when EC firmware booted. (required if EC EEPROM is
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rewritable; otherwise optional)
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* - 0x00000020
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- Developer switch was enabled when x86 firmware booted.
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* - 0x00000200
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- Firmware write protection was disabled when x86 firmware booted. (required if
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firmware write protection is controlled through x86 BIOS; otherwise optional)
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All other bits are reserved and should be set to 0.
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HWID (Chrome OS hardware ID)
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============================
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This control method returns the hardware ID for the Chromebook.
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Arguments:
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----------
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None
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Result code:
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------------
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A null-terminated ASCII string containing the hardware ID from the Model-Specific Data area of
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EEPROM.
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Note that the hardware ID can be up to 256 characters long, including the terminating null.
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FWID (Chrome OS firmware version)
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=================================
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This control method returns the firmware version for the rewritable portion of the main
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processor firmware.
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Arguments:
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----------
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None
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Result code:
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------------
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A null-terminated ASCII string containing the complete firmware version for the rewritable
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portion of the main processor firmware.
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FRID (Chrome OS read-only firmware version)
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===========================================
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This control method returns the firmware version for the read-only portion of the main
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processor firmware.
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Arguments:
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----------
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None
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Result code:
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------------
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A null-terminated ASCII string containing the complete firmware version for the read-only
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(bootstrap + recovery ) portion of the main processor firmware.
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BINF (Chrome OS boot information)
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=================================
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This control method returns information about the current boot.
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Arguments:
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----------
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None
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Result code:
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------------
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.. code-block::
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Package {
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Reserved1
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Reserved2
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Active EC Firmware
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Active Main Firmware Type
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Reserved5
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}
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.. flat-table::
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:widths: 1 1 2
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:header-rows: 1
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* - Field
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- Format
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- Description
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* - Reserved1
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- DWORD
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- Set to 256 (0x100). This indicates this field is no longer used.
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* - Reserved2
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- DWORD
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- Set to 256 (0x100). This indicates this field is no longer used.
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* - Active EC firmware
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- DWORD
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- The EC firmware which was used during boot.
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- 0 - Read-only (recovery) firmware
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- 1 - Rewritable firmware.
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Set to 0 if EC firmware is always read-only.
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* - Active Main Firmware Type
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- DWORD
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- The main firmware type which was used during boot.
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- 0 - Recovery
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- 1 - Normal
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- 2 - Developer
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- 3 - netboot (factory installation only)
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Other values are reserved.
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* - Reserved5
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- DWORD
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- Set to 256 (0x100). This indicates this field is no longer used.
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GPIO (Chrome OS GPIO assignments)
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=================================
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This control method returns information about Chrome OS specific GPIO assignments for
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Chrome OS hardware, so the kernel can directly control that hardware.
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Arguments:
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----------
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None
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Result code:
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------------
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.. code-block::
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Package {
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Package {
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// First GPIO assignment
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Signal Type //DWORD
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Attributes //DWORD
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Controller Offset //DWORD
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Controller Name //ASCIIZ
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},
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...
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Package {
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// Last GPIO assignment
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Signal Type //DWORD
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Attributes //DWORD
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Controller Offset //DWORD
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Controller Name //ASCIIZ
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}
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}
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Where ASCIIZ means a null-terminated ASCII string.
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.. flat-table::
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:widths: 1 1 2
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:header-rows: 1
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* - Field
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- Format
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- Description
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* - Signal Type
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- DWORD
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- Type of GPIO signal
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- 0x00000001 - Recovery button
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- 0x00000002 - Developer mode switch
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- 0x00000003 - Firmware write protection switch
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- 0x00000100 - Debug header GPIO 0
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- ...
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- 0x000001FF - Debug header GPIO 255
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Other values are reserved.
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* - Attributes
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- DWORD
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- Signal attributes as bitfields:
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- 0x00000001 - Signal is active-high (for button, a GPIO value
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of 1 means the button is pressed; for switches, a GPIO value
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of 1 means the switch is enabled). If this bit is 0, the signal
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is active low. Set to 0 for debug header GPIOs.
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* - Controller Offset
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- DWORD
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- GPIO number on the specified controller.
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* - Controller Name
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- ASCIIZ
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- Name of the controller for the GPIO.
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Currently supported names:
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"NM10" - Intel NM10 chip
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VBNV (Chrome OS NVRAM locations)
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================================
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This control method returns information about the NVRAM (CMOS) locations used to
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communicate with the BIOS.
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Arguments:
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----------
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None
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Result code:
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------------
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.. code-block::
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Package {
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NV Storage Block Offset //DWORD
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NV Storage Block Size //DWORD
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}
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.. flat-table::
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:widths: 1 1 2
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:header-rows: 1
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* - Field
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- Format
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- Description
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* - NV Storage Block Offset
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- DWORD
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- Offset in CMOS bank 0 of the verified boot non-volatile storage block, counting from
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the first writable CMOS byte (that is, offset=0 is the byte following the 14 bytes of
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clock data).
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* - NV Storage Block Size
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- DWORD
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- Size in bytes of the verified boot non-volatile storage block.
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FMAP (Chrome OS flashmap address)
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=================================
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This control method returns the physical memory address of the start of the main processor
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firmware flashmap.
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Arguments:
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----------
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None
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NoneResult code:
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----------------
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A DWORD containing the physical memory address of the start of the main processor firmware
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flashmap.
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VDTA (Chrome OS verified boot data)
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===================================
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This control method returns the verified boot data block shared between the firmware
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verification step and the kernel verification step.
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Arguments:
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----------
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None
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Result code:
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------------
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A buffer containing the verified boot data block.
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MECK (Management Engine Checksum)
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=================================
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This control method returns the SHA-1 or SHA-256 hash that is read out of the Management
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Engine extended registers during boot. The hash is exported via ACPI so the OS can verify that
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the ME firmware has not changed. If Management Engine is not present, or if the firmware was
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unable to read the extended registers, this buffer can be zero.
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Arguments:
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----------
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None
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Result code:
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------------
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A buffer containing the ME hash.
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MLST (Chrome OS method list)
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============================
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This control method returns a list of the other control methods supported by the Chrome OS
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hardware device.
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Arguments:
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----------
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None
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Result code:
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------------
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A package containing a list of null-terminated ASCII strings, one for each control method
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supported by the Chrome OS hardware device, not including the MLST method itself.
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For this version of the specification, the result is:
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.. code-block::
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Package {
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"CHSW",
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"FWID",
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"HWID",
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"FRID",
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"BINF",
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"GPIO",
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"VBNV",
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"FMAP",
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"VDTA",
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"MECK"
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}
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