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55dfb8bed6
Add support for using DPDES in the library for using guest state
buffers. DPDES support is needed for enabling usage of doorbells in a L2
KVM on PAPR guest.
Fixes: 6ccbbc33f0 ("KVM: PPC: Add helper library for Guest State Buffers")
Cc: stable@vger.kernel.org # v6.7+
Signed-off-by: Gautam Menghani <gautam@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20240605113913.83715-2-gautam@linux.ibm.com
637 lines
29 KiB
ReStructuredText
637 lines
29 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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====================================
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Nested KVM on POWER
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====================================
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Introduction
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============
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This document explains how a guest operating system can act as a
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hypervisor and run nested guests through the use of hypercalls, if the
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hypervisor has implemented them. The terms L0, L1, and L2 are used to
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refer to different software entities. L0 is the hypervisor mode entity
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that would normally be called the "host" or "hypervisor". L1 is a
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guest virtual machine that is directly run under L0 and is initiated
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and controlled by L0. L2 is a guest virtual machine that is initiated
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and controlled by L1 acting as a hypervisor.
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Existing API
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============
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Linux/KVM has had support for Nesting as an L0 or L1 since 2018
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The L0 code was added::
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commit 8e3f5fc1045dc49fd175b978c5457f5f51e7a2ce
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Author: Paul Mackerras <paulus@ozlabs.org>
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Date: Mon Oct 8 16:31:03 2018 +1100
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KVM: PPC: Book3S HV: Framework and hcall stubs for nested virtualization
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The L1 code was added::
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commit 360cae313702cdd0b90f82c261a8302fecef030a
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Author: Paul Mackerras <paulus@ozlabs.org>
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Date: Mon Oct 8 16:31:04 2018 +1100
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KVM: PPC: Book3S HV: Nested guest entry via hypercall
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This API works primarily using a single hcall h_enter_nested(). This
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call made by the L1 to tell the L0 to start an L2 vCPU with the given
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state. The L0 then starts this L2 and runs until an L2 exit condition
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is reached. Once the L2 exits, the state of the L2 is given back to
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the L1 by the L0. The full L2 vCPU state is always transferred from
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and to L1 when the L2 is run. The L0 doesn't keep any state on the L2
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vCPU (except in the short sequence in the L0 on L1 -> L2 entry and L2
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-> L1 exit).
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The only state kept by the L0 is the partition table. The L1 registers
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it's partition table using the h_set_partition_table() hcall. All
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other state held by the L0 about the L2s is cached state (such as
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shadow page tables).
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The L1 may run any L2 or vCPU without first informing the L0. It
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simply starts the vCPU using h_enter_nested(). The creation of L2s and
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vCPUs is done implicitly whenever h_enter_nested() is called.
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In this document, we call this existing API the v1 API.
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New PAPR API
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===============
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The new PAPR API changes from the v1 API such that the creating L2 and
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associated vCPUs is explicit. In this document, we call this the v2
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API.
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h_enter_nested() is replaced with H_GUEST_VCPU_RUN(). Before this can
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be called the L1 must explicitly create the L2 using h_guest_create()
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and any associated vCPUs() created with h_guest_create_vCPU(). Getting
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and setting vCPU state can also be performed using h_guest_{g|s}et
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hcall.
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The basic execution flow is for an L1 to create an L2, run it, and
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delete it is:
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- L1 and L0 negotiate capabilities with H_GUEST_{G,S}ET_CAPABILITIES()
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(normally at L1 boot time).
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- L1 requests the L0 create an L2 with H_GUEST_CREATE() and receives a token
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- L1 requests the L0 create an L2 vCPU with H_GUEST_CREATE_VCPU()
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- L1 and L0 communicate the vCPU state using the H_GUEST_{G,S}ET() hcall
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- L1 requests the L0 runs the vCPU running H_GUEST_VCPU_RUN() hcall
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- L1 deletes L2 with H_GUEST_DELETE()
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More details of the individual hcalls follows:
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HCALL Details
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=============
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This documentation is provided to give an overall understating of the
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API. It doesn't aim to provide all the details required to implement
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an L1 or L0. Latest version of PAPR can be referred to for more details.
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All these HCALLs are made by the L1 to the L0.
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H_GUEST_GET_CAPABILITIES()
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--------------------------
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This is called to get the capabilities of the L0 nested
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hypervisor. This includes capabilities such the CPU versions (eg
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POWER9, POWER10) that are supported as L2s::
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H_GUEST_GET_CAPABILITIES(uint64 flags)
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Parameters:
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Input:
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flags: Reserved
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Output:
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R3: Return code
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R4: Hypervisor Supported Capabilities bitmap 1
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H_GUEST_SET_CAPABILITIES()
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--------------------------
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This is called to inform the L0 of the capabilities of the L1
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hypervisor. The set of flags passed here are the same as
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H_GUEST_GET_CAPABILITIES()
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Typically, GET will be called first and then SET will be called with a
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subset of the flags returned from GET. This process allows the L0 and
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L1 to negotiate an agreed set of capabilities::
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H_GUEST_SET_CAPABILITIES(uint64 flags,
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uint64 capabilitiesBitmap1)
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Parameters:
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Input:
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flags: Reserved
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capabilitiesBitmap1: Only capabilities advertised through
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H_GUEST_GET_CAPABILITIES
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Output:
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R3: Return code
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R4: If R3 = H_P2: The number of invalid bitmaps
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R5: If R3 = H_P2: The index of first invalid bitmap
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H_GUEST_CREATE()
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----------------
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This is called to create an L2. A unique ID of the L2 created
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(similar to an LPID) is returned, which can be used on subsequent HCALLs to
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identify the L2::
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H_GUEST_CREATE(uint64 flags,
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uint64 continueToken);
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Parameters:
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Input:
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flags: Reserved
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continueToken: Initial call set to -1. Subsequent calls,
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after H_Busy or H_LongBusyOrder has been
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returned, value that was returned in R4.
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Output:
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R3: Return code. Notable:
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H_Not_Enough_Resources: Unable to create Guest VCPU due to not
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enough Hypervisor memory. See H_GUEST_CREATE_GET_STATE(flags =
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takeOwnershipOfVcpuState)
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R4: If R3 = H_Busy or_H_LongBusyOrder -> continueToken
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H_GUEST_CREATE_VCPU()
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---------------------
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This is called to create a vCPU associated with an L2. The L2 id
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(returned from H_GUEST_CREATE()) should be passed it. Also passed in
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is a unique (for this L2) vCPUid. This vCPUid is allocated by the
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L1::
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H_GUEST_CREATE_VCPU(uint64 flags,
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uint64 guestId,
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uint64 vcpuId);
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Parameters:
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Input:
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flags: Reserved
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guestId: ID obtained from H_GUEST_CREATE
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vcpuId: ID of the vCPU to be created. This must be within the
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range of 0 to 2047
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Output:
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R3: Return code. Notable:
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H_Not_Enough_Resources: Unable to create Guest VCPU due to not
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enough Hypervisor memory. See H_GUEST_CREATE_GET_STATE(flags =
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takeOwnershipOfVcpuState)
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H_GUEST_GET_STATE()
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-------------------
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This is called to get state associated with an L2 (Guest-wide or vCPU specific).
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This info is passed via the Guest State Buffer (GSB), a standard format as
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explained later in this doc, necessary details below:
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This can get either L2 wide or vcpu specific information. Examples of
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L2 wide is the timebase offset or process scoped page table
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info. Examples of vCPU specific are GPRs or VSRs. A bit in the flags
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parameter specifies if this call is L2 wide or vCPU specific and the
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IDs in the GSB must match this.
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The L1 provides a pointer to the GSB as a parameter to this call. Also
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provided is the L2 and vCPU IDs associated with the state to set.
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The L1 writes only the IDs and sizes in the GSB. L0 writes the
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associated values for each ID in the GSB::
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H_GUEST_GET_STATE(uint64 flags,
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uint64 guestId,
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uint64 vcpuId,
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uint64 dataBuffer,
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uint64 dataBufferSizeInBytes);
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Parameters:
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Input:
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flags:
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Bit 0: getGuestWideState: Request state of the Guest instead
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of an individual VCPU.
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Bit 1: takeOwnershipOfVcpuState Indicate the L1 is taking
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over ownership of the VCPU state and that the L0 can free
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the storage holding the state. The VCPU state will need to
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be returned to the Hypervisor via H_GUEST_SET_STATE prior
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to H_GUEST_RUN_VCPU being called for this VCPU. The data
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returned in the dataBuffer is in a Hypervisor internal
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format.
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Bits 2-63: Reserved
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guestId: ID obtained from H_GUEST_CREATE
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vcpuId: ID of the vCPU pass to H_GUEST_CREATE_VCPU
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dataBuffer: A L1 real address of the GSB.
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If takeOwnershipOfVcpuState, size must be at least the size
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returned by ID=0x0001
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dataBufferSizeInBytes: Size of dataBuffer
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Output:
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R3: Return code
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R4: If R3 = H_Invalid_Element_Id: The array index of the bad
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element ID.
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If R3 = H_Invalid_Element_Size: The array index of the bad
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element size.
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If R3 = H_Invalid_Element_Value: The array index of the bad
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element value.
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H_GUEST_SET_STATE()
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-------------------
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This is called to set L2 wide or vCPU specific L2 state. This info is
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passed via the Guest State Buffer (GSB), necessary details below:
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This can set either L2 wide or vcpu specific information. Examples of
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L2 wide is the timebase offset or process scoped page table
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info. Examples of vCPU specific are GPRs or VSRs. A bit in the flags
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parameter specifies if this call is L2 wide or vCPU specific and the
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IDs in the GSB must match this.
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The L1 provides a pointer to the GSB as a parameter to this call. Also
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provided is the L2 and vCPU IDs associated with the state to set.
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The L1 writes all values in the GSB and the L0 only reads the GSB for
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this call::
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H_GUEST_SET_STATE(uint64 flags,
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uint64 guestId,
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uint64 vcpuId,
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uint64 dataBuffer,
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uint64 dataBufferSizeInBytes);
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Parameters:
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Input:
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flags:
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Bit 0: getGuestWideState: Request state of the Guest instead
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of an individual VCPU.
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Bit 1: returnOwnershipOfVcpuState Return Guest VCPU state. See
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GET_STATE takeOwnershipOfVcpuState
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Bits 2-63: Reserved
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guestId: ID obtained from H_GUEST_CREATE
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vcpuId: ID of the vCPU pass to H_GUEST_CREATE_VCPU
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dataBuffer: A L1 real address of the GSB.
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If takeOwnershipOfVcpuState, size must be at least the size
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returned by ID=0x0001
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dataBufferSizeInBytes: Size of dataBuffer
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Output:
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R3: Return code
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R4: If R3 = H_Invalid_Element_Id: The array index of the bad
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element ID.
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If R3 = H_Invalid_Element_Size: The array index of the bad
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element size.
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If R3 = H_Invalid_Element_Value: The array index of the bad
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element value.
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H_GUEST_RUN_VCPU()
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------------------
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This is called to run an L2 vCPU. The L2 and vCPU IDs are passed in as
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parameters. The vCPU runs with the state set previously using
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H_GUEST_SET_STATE(). When the L2 exits, the L1 will resume from this
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hcall.
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This hcall also has associated input and output GSBs. Unlike
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H_GUEST_{S,G}ET_STATE(), these GSB pointers are not passed in as
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parameters to the hcall (This was done in the interest of
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performance). The locations of these GSBs must be preregistered using
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the H_GUEST_SET_STATE() call with ID 0x0c00 and 0x0c01 (see table
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below).
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The input GSB may contain only VCPU specific elements to be set. This
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GSB may also contain zero elements (ie 0 in the first 4 bytes of the
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GSB) if nothing needs to be set.
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On exit from the hcall, the output buffer is filled with elements
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determined by the L0. The reason for the exit is contained in GPR4 (ie
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NIP is put in GPR4). The elements returned depend on the exit
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type. For example, if the exit reason is the L2 doing a hcall (GPR4 =
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0xc00), then GPR3-12 are provided in the output GSB as this is the
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state likely needed to service the hcall. If additional state is
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needed, H_GUEST_GET_STATE() may be called by the L1.
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To synthesize interrupts in the L2, when calling H_GUEST_RUN_VCPU()
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the L1 may set a flag (as a hcall parameter) and the L0 will
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synthesize the interrupt in the L2. Alternatively, the L1 may
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synthesize the interrupt itself using H_GUEST_SET_STATE() or the
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H_GUEST_RUN_VCPU() input GSB to set the state appropriately::
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H_GUEST_RUN_VCPU(uint64 flags,
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uint64 guestId,
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uint64 vcpuId,
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uint64 dataBuffer,
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uint64 dataBufferSizeInBytes);
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Parameters:
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Input:
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flags:
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Bit 0: generateExternalInterrupt: Generate an external interrupt
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Bit 1: generatePrivilegedDoorbell: Generate a Privileged Doorbell
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Bit 2: sendToSystemReset”: Generate a System Reset Interrupt
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Bits 3-63: Reserved
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guestId: ID obtained from H_GUEST_CREATE
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vcpuId: ID of the vCPU pass to H_GUEST_CREATE_VCPU
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Output:
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R3: Return code
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R4: If R3 = H_Success: The reason L1 VCPU exited (ie. NIA)
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0x000: The VCPU stopped running for an unspecified reason. An
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example of this is the Hypervisor stopping a VCPU running
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due to an outstanding interrupt for the Host Partition.
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0x980: HDEC
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0xC00: HCALL
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0xE00: HDSI
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0xE20: HISI
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0xE40: HEA
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0xF80: HV Fac Unavail
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If R3 = H_Invalid_Element_Id, H_Invalid_Element_Size, or
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H_Invalid_Element_Value: R4 is offset of the invalid element
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in the input buffer.
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H_GUEST_DELETE()
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----------------
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This is called to delete an L2. All associated vCPUs are also
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deleted. No specific vCPU delete call is provided.
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A flag may be provided to delete all guests. This is used to reset the
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L0 in the case of kdump/kexec::
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H_GUEST_DELETE(uint64 flags,
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uint64 guestId)
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Parameters:
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Input:
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flags:
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Bit 0: deleteAllGuests: deletes all guests
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Bits 1-63: Reserved
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guestId: ID obtained from H_GUEST_CREATE
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Output:
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R3: Return code
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Guest State Buffer
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==================
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The Guest State Buffer (GSB) is the main method of communicating state
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about the L2 between the L1 and L0 via H_GUEST_{G,S}ET() and
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H_GUEST_VCPU_RUN() calls.
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State may be associated with a whole L2 (eg timebase offset) or a
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specific L2 vCPU (eg. GPR state). Only L2 VCPU state maybe be set by
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H_GUEST_VCPU_RUN().
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All data in the GSB is big endian (as is standard in PAPR)
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The Guest state buffer has a header which gives the number of
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elements, followed by the GSB elements themselves.
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GSB header:
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+----------+----------+-------------------------------------------+
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| Offset | Size | Purpose |
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| Bytes | Bytes | |
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+==========+==========+===========================================+
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| 0 | 4 | Number of elements |
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+----------+----------+-------------------------------------------+
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| 4 | | Guest state buffer elements |
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+----------+----------+-------------------------------------------+
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GSB element:
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+----------+----------+-------------------------------------------+
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| Offset | Size | Purpose |
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| Bytes | Bytes | |
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+==========+==========+===========================================+
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| 0 | 2 | ID |
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+----------+----------+-------------------------------------------+
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| 2 | 2 | Size of Value |
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+----------+----------+-------------------------------------------+
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| 4 | As above | Value |
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+----------+----------+-------------------------------------------+
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The ID in the GSB element specifies what is to be set. This includes
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archtected state like GPRs, VSRs, SPRs, plus also some meta data about
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the partition like the timebase offset and partition scoped page
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table information.
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+--------+-------+----+--------+----------------------------------+
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| ID | Size | RW | Thread | Details |
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| | Bytes | | Guest | |
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| | | | Scope | |
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+========+=======+====+========+==================================+
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| 0x0000 | | RW | TG | NOP element |
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+--------+-------+----+--------+----------------------------------+
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| 0x0001 | 0x08 | R | G | Size of L0 vCPU state. See: |
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| | | | | H_GUEST_GET_STATE: |
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| | | | | flags = takeOwnershipOfVcpuState |
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+--------+-------+----+--------+----------------------------------+
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| 0x0002 | 0x08 | R | G | Size Run vCPU out buffer |
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+--------+-------+----+--------+----------------------------------+
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| 0x0003 | 0x04 | RW | G | Logical PVR |
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+--------+-------+----+--------+----------------------------------+
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| 0x0004 | 0x08 | RW | G | TB Offset (L1 relative) |
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+--------+-------+----+--------+----------------------------------+
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| 0x0005 | 0x18 | RW | G |Partition scoped page tbl info: |
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| | | | | |
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| | | | |- 0x00 Addr part scope table |
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| | | | |- 0x08 Num addr bits |
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| | | | |- 0x10 Size root dir |
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+--------+-------+----+--------+----------------------------------+
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| 0x0006 | 0x10 | RW | G |Process Table Information: |
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| | | | | |
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| | | | |- 0x0 Addr proc scope table |
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| | | | |- 0x8 Table size. |
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+--------+-------+----+--------+----------------------------------+
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| 0x0007-| | | | Reserved |
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| 0x0BFF | | | | |
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+--------+-------+----+--------+----------------------------------+
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| 0x0C00 | 0x10 | RW | T |Run vCPU Input Buffer: |
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| | | | | |
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| | | | |- 0x0 Addr of buffer |
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| | | | |- 0x8 Buffer Size. |
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+--------+-------+----+--------+----------------------------------+
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| 0x0C01 | 0x10 | RW | T |Run vCPU Output Buffer: |
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| | | | | |
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| | | | |- 0x0 Addr of buffer |
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| | | | |- 0x8 Buffer Size. |
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+--------+-------+----+--------+----------------------------------+
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| 0x0C02 | 0x08 | RW | T | vCPU VPA Address |
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+--------+-------+----+--------+----------------------------------+
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| 0x0C03-| | | | Reserved |
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| 0x0FFF | | | | |
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+--------+-------+----+--------+----------------------------------+
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| 0x1000-| 0x08 | RW | T | GPR 0-31 |
|
|
| 0x101F | | | | |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1020 | 0x08 | T | T | HDEC expiry TB |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1021 | 0x08 | RW | T | NIA |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1022 | 0x08 | RW | T | MSR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1023 | 0x08 | RW | T | LR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1024 | 0x08 | RW | T | XER |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1025 | 0x08 | RW | T | CTR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1026 | 0x08 | RW | T | CFAR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1027 | 0x08 | RW | T | SRR0 |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1028 | 0x08 | RW | T | SRR1 |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1029 | 0x08 | RW | T | DAR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x102A | 0x08 | RW | T | DEC expiry TB |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x102B | 0x08 | RW | T | VTB |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x102C | 0x08 | RW | T | LPCR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x102D | 0x08 | RW | T | HFSCR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x102E | 0x08 | RW | T | FSCR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x102F | 0x08 | RW | T | FPSCR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1030 | 0x08 | RW | T | DAWR0 |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1031 | 0x08 | RW | T | DAWR1 |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1032 | 0x08 | RW | T | CIABR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1033 | 0x08 | RW | T | PURR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1034 | 0x08 | RW | T | SPURR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1035 | 0x08 | RW | T | IC |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1036-| 0x08 | RW | T | SPRG 0-3 |
|
|
| 0x1039 | | | | |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x103A | 0x08 | W | T | PPR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x103B | 0x08 | RW | T | MMCR 0-3 |
|
|
| 0x103E | | | | |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x103F | 0x08 | RW | T | MMCRA |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1040 | 0x08 | RW | T | SIER |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1041 | 0x08 | RW | T | SIER 2 |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1042 | 0x08 | RW | T | SIER 3 |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1043 | 0x08 | RW | T | BESCR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1044 | 0x08 | RW | T | EBBHR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1045 | 0x08 | RW | T | EBBRR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1046 | 0x08 | RW | T | AMR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1047 | 0x08 | RW | T | IAMR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1048 | 0x08 | RW | T | AMOR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1049 | 0x08 | RW | T | UAMOR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x104A | 0x08 | RW | T | SDAR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x104B | 0x08 | RW | T | SIAR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x104C | 0x08 | RW | T | DSCR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x104D | 0x08 | RW | T | TAR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x104E | 0x08 | RW | T | DEXCR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x104F | 0x08 | RW | T | HDEXCR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1050 | 0x08 | RW | T | HASHKEYR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1051 | 0x08 | RW | T | HASHPKEYR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1052 | 0x08 | RW | T | CTRL |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1053 | 0x08 | RW | T | DPDES |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x1054-| | | | Reserved |
|
|
| 0x1FFF | | | | |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x2000 | 0x04 | RW | T | CR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x2001 | 0x04 | RW | T | PIDR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x2002 | 0x04 | RW | T | DSISR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x2003 | 0x04 | RW | T | VSCR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x2004 | 0x04 | RW | T | VRSAVE |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x2005 | 0x04 | RW | T | DAWRX0 |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x2006 | 0x04 | RW | T | DAWRX1 |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x2007-| 0x04 | RW | T | PMC 1-6 |
|
|
| 0x200c | | | | |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x200D | 0x04 | RW | T | WORT |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x200E | 0x04 | RW | T | PSPB |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x200F-| | | | Reserved |
|
|
| 0x2FFF | | | | |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x3000-| 0x10 | RW | T | VSR 0-63 |
|
|
| 0x303F | | | | |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0x3040-| | | | Reserved |
|
|
| 0xEFFF | | | | |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0xF000 | 0x08 | R | T | HDAR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0xF001 | 0x04 | R | T | HDSISR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0xF002 | 0x04 | R | T | HEIR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
| 0xF003 | 0x08 | R | T | ASDR |
|
|
+--------+-------+----+--------+----------------------------------+
|
|
|
|
|
|
Miscellaneous info
|
|
==================
|
|
|
|
State not in ptregs/hvregs
|
|
--------------------------
|
|
|
|
In the v1 API, some state is not in the ptregs/hvstate. This includes
|
|
the vector register and some SPRs. For the L1 to set this state for
|
|
the L2, the L1 loads up these hardware registers before the
|
|
h_enter_nested() call and the L0 ensures they end up as the L2 state
|
|
(by not touching them).
|
|
|
|
The v2 API removes this and explicitly sets this state via the GSB.
|
|
|
|
L1 Implementation details: Caching state
|
|
----------------------------------------
|
|
|
|
In the v1 API, all state is sent from the L1 to the L0 and vice versa
|
|
on every h_enter_nested() hcall. If the L0 is not currently running
|
|
any L2s, the L0 has no state information about them. The only
|
|
exception to this is the location of the partition table, registered
|
|
via h_set_partition_table().
|
|
|
|
The v2 API changes this so that the L0 retains the L2 state even when
|
|
it's vCPUs are no longer running. This means that the L1 only needs to
|
|
communicate with the L0 about L2 state when it needs to modify the L2
|
|
state, or when it's value is out of date. This provides an opportunity
|
|
for performance optimisation.
|
|
|
|
When a vCPU exits from a H_GUEST_RUN_VCPU() call, the L1 internally
|
|
marks all L2 state as invalid. This means that if the L1 wants to know
|
|
the L2 state (say via a kvm_get_one_reg() call), it needs call
|
|
H_GUEST_GET_STATE() to get that state. Once it's read, it's marked as
|
|
valid in L1 until the L2 is run again.
|
|
|
|
Also, when an L1 modifies L2 vcpu state, it doesn't need to write it
|
|
to the L0 until that L2 vcpu runs again. Hence when the L1 updates
|
|
state (say via a kvm_set_one_reg() call), it writes to an internal L1
|
|
copy and only flushes this copy to the L0 when the L2 runs again via
|
|
the H_GUEST_VCPU_RUN() input buffer.
|
|
|
|
This lazy updating of state by the L1 avoids unnecessary
|
|
H_GUEST_{G|S}ET_STATE() calls.
|