Huacai Chen f339bd3b51 Docs/LoongArch: Add advanced extended IRQ model description ... Introduce the advanced extended interrupt controllers (AVECINTC). This feature will allow each core to have 256 independent interrupt vectors and MSI interrupts can be independently routed to any vector on any CPU. The whole topology of irqchips in LoongArch machines looks like this if AVECINTC is supported: +-----+ +-----------------------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +-----------------------+ +-------+ ^ ^ ^ | | | +---------+ +----------+ +---------+ +-------+ | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | +---------+ +----------+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | Devices | | PCH-LPC | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+ Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>		2024-09-24 15:32:20 +08:00
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booting.rst
features.rst	docs: kernel_feat.py: fix potential command injection	2024-01-11 09:21:01 -07:00
index.rst
introduction.rst	Docs/LoongArch: Update links in LoongArch introduction.rst	2023-11-21 15:03:25 +08:00
irq-chip-model.rst	Docs/LoongArch: Add advanced extended IRQ model description	2024-09-24 15:32:20 +08:00