Commit Graph

11 Commits

Author SHA1 Message Date
Gabriel FERNANDEZ
08488e20cc ARM: STi: DT: STiH416: 416 DT Entry for clockgen A0/1/10/11/12
Patch adds DT entries for clockgen A0/1/10/11/12

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2014-05-21 14:27:09 +02:00
Gabriel FERNANDEZ
ed3593f986 ARM: STi: DT: STiH41x: Rename CLK_SYSIN into clk_sysin
all-caps node name is not very usual.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2014-05-21 14:27:08 +02:00
Gabriel FERNANDEZ
948d8ffb47 ARM: STi: DT: add keyscan for stih416
Add keyscan support for stih416.
It is disabled by default given that it is not enabled on all boards.
Also there are PIOs conflict with already claimed lines.

Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2014-05-21 14:27:07 +02:00
Lee Jones
77f8d9b7e6 ARM: STi: stih416: Add support for the FSM Serial Flash Controller
Here we add the necessary device nodes required for successful device
probing and Pinctrl setup for the FSM when booting on an STiH416 (Orly2).

Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by Angus Clark <angus.clark@st.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27 02:01:05 +01:00
Srinivas Kandagatla
e063735f91 ARM: STi: STIH416: Add IR support.
This patch adds IRB support to STiH416 platforms.

Tested on B2000 and B2020 development board

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
2014-03-11 10:04:38 +00:00
Srinivas Kandagatla
d25ea58453 ARM: STi: STiH416: Add ethernet support.
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.

Tested on both B2020 and B2000.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
2014-03-11 10:04:13 +00:00
Srinivas Kandagatla
bef40df89f ARM: STi: STiH416: Add soft reset controller support.
This patch adds soft reset controller support for STiH415 and adds new
softreset lines required for other device tree nodes in the header file.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
2014-03-11 10:03:47 +00:00
Srinivas Kandagatla
da3e02a236 ARM: STi: STiH416: Add reset controller support.
This patch adds a reset controller node to the SOC device tree and also
adds new header files with reset lines required for other device tree
nodes.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
2014-03-11 10:03:27 +00:00
Maxime COQUELIN
f53e99a9b4 ARM: STi: Supply I2C configuration to STiH416 SoC
This patch supplies I2C configuration to STiH416 SoC.

Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
2013-12-04 08:59:55 +00:00
Srinivas Kandagatla
334ab91d58 ARM: dts: STi: Fix pinconf setup for STiH416 serial2
This patch fixes a bug in pinctrl setup of serial2 device, Some of the
pins in the pinctrl node of serial2 do not belong to that
pin-controller. This patch divides them in the pins into there
respective pin controller nodes.

Without this patch serial on StiH416-B2000 Board will not work as it
fails with:

"st-pinctrl pin-controller-rear.3: failed to get pin(99) name
st-pinctrl pin-controller-rear.3: maps: function serial2 group serial2-0
num 4
pinconfig core: failed to register map default (3): no group/pin given"

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-07-22 19:34:55 -07:00
Srinivas Kandagatla
15969b4577 ARM: sti: Add STiH416 SOC support
The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
CC: Stephen Gallimore <stephen.gallimore@st.com>
CC: Stuart Menefy <stuart.menefy@st.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Linus Walleij <linus.walleij@linaro.org>

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-25 13:26:58 -07:00