Commit Graph

5784 Commits

Author SHA1 Message Date
Paul Cercueil
7ca4c922aa clk: ingenic: Fix doc of ingenic_cgu_div_info
The 'div' field does not represent a number of bits used to divide
(understand: right-shift) the divider, but a number itself used to
divide the divider.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Maarten ter Huurne <maarten@treewalker.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22 10:13:44 -08:00
Paul Cercueil
bc5d922c93 clk: ingenic: Fix round_rate misbehaving with non-integer dividers
Take a parent rate of 180 MHz, and a requested rate of 4.285715 MHz.
This results in a theorical divider of 41.999993 which is then rounded
up to 42. The .round_rate function would then return (180 MHz / 42) as
the clock, rounded down, so 4.285714 MHz.

Calling clk_set_rate on 4.285714 MHz would round the rate again, and
give a theorical divider of 42,0000028, now rounded up to 43, and the
rate returned would be (180 MHz / 43) which is 4.186046 MHz, aka. not
what we requested.

Fix this by rounding up the divisions.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Maarten ter Huurne <maarten@treewalker.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22 10:13:43 -08:00
YueHaibing
8122966318 clk: mediatek: fix platform_no_drv_owner.cocci warnings
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22 10:01:31 -08:00
YueHaibing
e7e6198c60 clk: tegra: dfll: Fix debugfs_simple_attr.cocci warnings
Use DEFINE_DEBUGFS_ATTRIBUTE rather than DEFINE_SIMPLE_ATTRIBUTE
for debugfs files.

Semantic patch information:
Rationale: DEFINE_SIMPLE_ATTRIBUTE + debugfs_create_file()
imposes some significant overhead as compared to
DEFINE_DEBUGFS_ATTRIBUTE + debugfs_create_file_unsafe().

Generated by: scripts/coccinelle/api/debugfs/debugfs_simple_attr.cocci

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22 10:01:21 -08:00
Dan Carpenter
8f99f5eab0 clk: qoriq: Improve an error message
We intended to print "ret" but there is a copy and paste bug from the
previous error message.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22 10:00:45 -08:00
Michał Mirosław
bb631af3d5 clk: at91: optimize clk_round_rate() for AUDIO_PLL
Stop the search for parent rate when exact match is found.

This makes for 3 clk_round_rate() calls instead of 64 of them on
SAMA5D2-based board when searching for 12.288MHz clock.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22 09:54:17 -08:00
Andy Shevchenko
a9443a6328 clk: x86: Move clk-lpss.h to platform_data/x86
clk-lpss.h is solely x86 related header. Move it to correct folder.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22 00:14:31 -08:00
Katsuhiro Suzuki
d13501a2be clk: fractional-divider: check parent rate only if flag is set
Custom approximation of fractional-divider may not need parent clock
rate checking. For example Rockchip SoCs work fine using grand parent
clock rate even if target rate is greater than parent.

This patch checks parent clock rate only if CLK_SET_RATE_PARENT flag
is set.

For detailed example, clock tree of Rockchip I2S audio hardware.
  - Clock rate of CPLL is 1.2GHz, GPLL is 491.52MHz.
  - i2s1_div is integer divider can divide N (N is 1~128).
    Input clock is CPLL or GPLL. Initial divider value is N = 1.
    Ex) PLL = CPLL, N = 10, i2s1_div output rate is
      CPLL / 10 = 1.2GHz / 10 = 120MHz
  - i2s1_frac is fractional divider can divide input to x/y, x and
    y are 16bit integer.

CPLL --> | selector | ---> i2s1_div -+--> | selector | --> I2S1 MCLK
GPLL --> |          | ,--------------'    |          |
                      `--> i2s1_frac ---> |          |

Clock mux system try to choose suitable one from i2s1_div and
i2s1_frac for master clock (MCLK) of I2S1.

Bad scenario as follows:
  - Try to set MCLK to 8.192MHz (32kHz audio replay)
    Candidate setting is
    - i2s1_div: GPLL / 60 = 8.192MHz
    i2s1_div candidate is exactly same as target clock rate, so mux
    choose this clock source. i2s1_div output rate is changed
    491.52MHz -> 8.192MHz

  - After that try to set to 11.2896MHz (44.1kHz audio replay)
    Candidate settings are
    - i2s1_div : CPLL / 107 = 11.214945MHz
    - i2s1_frac: i2s1_div   = 8.192MHz
      This is because clk_fd_round_rate() thinks target rate
      (11.2896MHz) is higher than parent rate (i2s1_div = 8.192MHz)
      and returns parent clock rate.

Above is current upstreamed behavior. Clock mux system choose
i2s1_div, but this clock rate is not acceptable for I2S driver, so
users cannot replay audio.

Expected behavior is:
  - Try to set master clock to 11.2896MHz (44.1kHz audio replay)
    Candidate settings are
    - i2s1_div : CPLL / 107          = 11.214945MHz
    - i2s1_frac: i2s1_div * 147/6400 = 11.2896MHz
                 Change i2s1_div to GPLL / 1 = 491.52MHz at same
                 time.

If apply this commit, clk_fd_round_rate() calls custom approximate
function of Rockchip even if target rate is higher than parent.
Custom function changes both grand parent (i2s1_div) and parent
(i2s_frac) settings at same time. Clock mux system can choose
i2s1_frac and audio works fine.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
[sboyd@kernel.org: Make function into a macro instead]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22 00:11:47 -08:00
Jeffrey Hugo
760be6586f clk: qcom: Make common clk_hw registrations
Several clock controller drivers define a list of clk_hw devices, and then
register those devices in probe() before using common code to process the
rest of initialization.  Extend the common code to accept a list of clk_hw
devices to process, thus eliminating many duplicate implementations.

Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Tested-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22 00:06:57 -08:00
Manivannan Sadhasivam
ed6b4795ec clk: actions: Add clock driver for S500 SoC
Add common clock driver for Actions Semi S500 SoC.

Signed-off-by: Edgar Bernardi Righi <edgar.righi@lsitec.org.br>
[Mani: cleaned up the driver]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22 00:01:08 -08:00
Manivannan Sadhasivam
9831289f6f clk: actions: Add configurable PLL delay
S500 SoC requires configurable delay for different PLLs. Hence, add
a separate macro for declaring a PLL with configurable delay and also
modify the existing OWL_PLL_NO_PARENT macro to use default delay so
that no need to modify the existing S700/S900 drivers.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 23:58:12 -08:00
Stephen Boyd
341fdf2602 clk: imx: imx8mm: Mark init function __init
It calls another __init marked function and thus causes a section
mismatch if we don't mark it this way.

Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 15:29:10 -08:00
Taniya Das
9d575719ca clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock
The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
only for blsp1_uart3 clock, so add it for uart3 only.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:18:13 -08:00
Taniya Das
96dc791d0b clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs
The RCG CFG/M/N/D register base could be at a different offset than
the CMD register, so introduce a cfg_offset to identify the offset
with respect to the CMD RCGR register.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:18:12 -08:00
Vinod Koul
fe6b580ec6 clk: qcom: remove empty lines in clk-rcg.h
Remove the redundant empty lines crept in.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:18:11 -08:00
Gabriel Fernandez
97621d22df clk: stm32mp1: fix bit width of hse_rtc divider
Fix the bit width of the hse rtc divider because it's off by one.

Fixes: 2c87c9d331 ("clk: stm32mp1: add RTC clock")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:22 -08:00
Gabriel Fernandez
f9b76fd24d clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag
The divisor of ethptp_k and ck_hse_rtc clocks is: 'value register
plus one'.
Then CLK_DIVIDER_ALLOW_ZERO flag has no effect and is useless here.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:21 -08:00
Gabriel Fernandez
d3f2e33c87 clk: stm32mp1: fix HSI divider flag
The divider of HSI (clk-hsi-div) is power of two divider.

Fixes: 9bee94e7b7 ("clk: stm32mp1: Introduce STM32MP1 clock driver")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:21 -08:00
Gabriel Fernandez
140fc4e406 clk: stm32mp1: fix mcu divider table
index 8: ck_mcu is divided by 256 (not 512)

Fixes: e51d297e9a ("clk: stm32mp1: add Sub System clocks")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:20 -08:00
Gabriel Fernandez
c488b24f86 clk: stm32mp1: set ck_csi as critical clock
ck_csi is used for IO compensation so it should be
considered as "always-on" and kept on.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:19 -08:00
Gabriel Fernandez
72cfd1ad10 clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks
STM32MP1 clock IP offers lots of Kernel clocks that are shared
by multiple IP's at the same time.
Then boot loader applies a clock tree that allows to use all IP's
at same time and with the maximum of performance.
Not change parents on a change rate on kernel clocks ensures
the integrity of the system.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:18 -08:00
Gabriel Fernandez
749c9e553e clk: stm32mp1: parent clocks update
Fixes parent clock for axi, fdcan, sai and adc12 clocks.

Fixes: e51d297e9a ("clk: stm32mp1: add Sub System clocks")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:06 -08:00
Tony Lindgren
5ae51d67ae clk: clk-twl6040: Fix imprecise external abort for pdmclk
I noticed that modprobe clk-twl6040 can fail after a cold boot with:
abe_cm:clk:0010:0: failed to enable
...
Unhandled fault: imprecise external abort (0x1406) at 0xbe896b20

WARNING: CPU: 1 PID: 29 at drivers/clk/clk.c:828 clk_core_disable_lock+0x18/0x24
...
(clk_core_disable_lock) from [<c0123534>] (_disable_clocks+0x18/0x90)
(_disable_clocks) from [<c0124040>] (_idle+0x17c/0x244)
(_idle) from [<c0125ad4>] (omap_hwmod_idle+0x24/0x44)
(omap_hwmod_idle) from [<c053a038>] (sysc_runtime_suspend+0x48/0x108)
(sysc_runtime_suspend) from [<c06084c4>] (__rpm_callback+0x144/0x1d8)
(__rpm_callback) from [<c0608578>] (rpm_callback+0x20/0x80)
(rpm_callback) from [<c0607034>] (rpm_suspend+0x120/0x694)
(rpm_suspend) from [<c0607a78>] (__pm_runtime_idle+0x60/0x84)
(__pm_runtime_idle) from [<c053aaf0>] (sysc_probe+0x874/0xf2c)
(sysc_probe) from [<c05fecd4>] (platform_drv_probe+0x48/0x98)

After searching around for a similar issue, I came across an earlier fix
that never got merged upstream in the Android tree for glass-omap-xrr02.
There is patch "MFD: twl6040-codec: Implement PDMCLK cold temp errata"
by Misael Lopez Cruz <misael.lopez@ti.com>.

Based on my observations, this fix is also needed when cold booting
devices, and not just for deeper idle modes. Since we now have a clock
driver for pdmclk, let's fix the issue in twl6040_pdmclk_prepare().

Cc: Misael Lopez Cruz <misael.lopez@ti.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:11:23 -08:00
Thomas Petazzoni
c0189feead clk: clk-gpio: add support for sleeping GPIOs in gpio-gate-clk
The current implementation of gpio-gate-clk enables/disables the clock
using the GPIO in the ->enable() and ->disable() clock callbacks. This
requires the GPIO to be configurable in atomic contexts. While it is
the case for most memory-mapped GPIO controllers, it is not the case
for GPIO expanders on I2C or SPI.

This commit extends the gpio-gate-clk to check whether the GPIO calls
require sleeping or not. If sleeping is not required, the current
implementation based on ->enable()/->disable() is kept. However, if
sleeping is needed, we instead implement the logic in the ->prepare()
and ->unprepare() hooks. Thanks to this, a gate clock connected to a
GPIO on a GPIO expander can be controlled with the existing driver.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
[sboyd@kernel.org: Mark clk ops static]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:05:25 -08:00
David Dai
04053f4d23 clk: qcom: clk-rpmh: Add IPA clock support
The clk-rpmh driver only supports on and off RPMh clock resources. Let's
extend the driver by adding support for clocks that are managed by a
different type of RPMh resource known as Bus Clock Manager(BCM). The BCM
is a configurable shared resource aggregator that scales performance
based on a set of frequency points. The Qualcomm IP Accelerator (IPA)
clock is an example of a resource that is managed by the BCM and this a
requirement from the IPA driver in order to scale its core clock.

Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:57:55 -08:00
Lubomir Rintel
0ea8cbc15d clk: mmp2: separate LCDC peripheral clk form the display clock
These are in fact two clocks, they shouldn't be exposed as one. One is
required for accessing LCD controller registers (peripheral clock), while
other (AXI clock) can be optionally used as a pixel clock source for the
panel.

LCDC can alternatively use different clocks than the Display 1 AXI clock
for generating the pixel clock: the second AXI clock (fixed in this
commit too), the HDMI PLL, or the AXI bus clock.

They should really be controlled independently.

Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:52:02 -08:00
Kunihiko Hayashi
521282237b clk: uniphier: Fix update register for CPU-gear
Need to set the update bit in UNIPHIER_CLK_CPUGEAR_UPD to update
the CPU-gear value.

Fixes: d08f1f0d59 ("clk: uniphier: add CPU-gear change (cpufreq) support")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:50:23 -08:00
Gustavo A. R. Silva
0612fe604d clk: samsung: s3c2443: Mark expected switch fall-through
In preparation to enabling -Wimplicit-fallthrough, mark switch
cases where we are expecting to fall through.

This patch fixes the following warnings:

drivers/clk/samsung/clk-s3c2443.c: In function ‘s3c2443_common_clk_init’:
drivers/clk/samsung/clk-s3c2443.c:390:3: warning: this statement may fall through [-Wimplicit-fallthrough=]
   samsung_clk_register_alias(ctx, s3c2450_aliases,
   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     ARRAY_SIZE(s3c2450_aliases));
     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2443.c:393:2: note: here
  case S3C2416:
  ^~~~

Warning level 3 was used: -Wimplicit-fallthrough=3

Notice that, in this particular case,  the code comment is modified
in accordance with what GCC is expecting to find.

This patch is part of the ongoing efforts to enable
-Wimplicit-fallthrough.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:43:49 -08:00
Krzysztof Kozlowski
785c9f411e clk: samsung: exynos5: Fix kfree() of const memory on setting driver_override
Platform driver driver_override field should not be initialized from
const memory because the core later kfree() it.  If driver_override is
manually set later through sysfs, kfree() of old value leads to:

    $ echo "new_value" > /sys/bus/platform/drivers/.../driver_override

    kernel BUG at ../mm/slub.c:3960!
    Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
    ...
    (kfree) from [<c058e8c0>] (platform_set_driver_override+0x84/0xac)
    (platform_set_driver_override) from [<c058e908>] (driver_override_store+0x20/0x34)
    (driver_override_store) from [<c031f778>] (kernfs_fop_write+0x100/0x1dc)
    (kernfs_fop_write) from [<c0296de8>] (__vfs_write+0x2c/0x17c)
    (__vfs_write) from [<c02970c4>] (vfs_write+0xa4/0x188)
    (vfs_write) from [<c02972e8>] (ksys_write+0x4c/0xac)
    (ksys_write) from [<c0101000>] (ret_fast_syscall+0x0/0x28)

The clk-exynos5-subcmu driver uses override only for the purpose of
creating meaningful names for children devices (matching names of power
domains, e.g. DISP, MFC).  The driver_override was not developed for
this purpose so just switch to default names of devices to fix the
issue.

Fixes: b06a532bf1 ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:33:00 -08:00
Krzysztof Kozlowski
5f0b6216ea clk: samsung: exynos5: Fix possible NULL pointer exception on platform_device_alloc() failure
During initialization of subdevices if platform_device_alloc() failed,
returned NULL pointer will be later dereferenced.  Add proper error
paths to exynos5_clk_register_subcmu().  The return value of this
function is still ignored because at this stage of init there is nothing
we can do.

Fixes: b06a532bf1 ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:32:50 -08:00
Fabrizio Castro
e61b30bb34 clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLK
Enum LAST_DT_CORE_CLK needs updating as R8A774C0_CLK_CANFD
was recently added and it's the core clock with the highest
index.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Fixes: 2a6efbc6da ("clk: renesas: r8a774c0: Add missing CANFD clock")
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:09:52 -08:00
Abel Vesa
db27e40b27 clk: imx8mq: Add the missing ARM clock
Add the ARM clock as imx_clk_cpu type.
Will be used by cpufreq.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:56:52 -08:00
Abel Vesa
ad18bbf369 clk: imx: imx8mq: Fix the rate propagation for arm pll
The arm pll bypass needs to propagate the rate upwards
in order for the cpufreq to work.

Fixes: b80522040c ("clk: imx: Add clock driver for i.MX8MQ CCM")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:56:52 -08:00
Fabio Estevam
202ce5afe5 clk: imx8mq: Add support for the CLKO1 clock
Add the entry for the CLKO1 clock.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:56:52 -08:00
Fabio Estevam
0bfed63baf clk: imx8mq: Fix the CLKO2 source select list
The CLKO2 clock source select list is the following as per the i.MX8M
Reference Manual:

000 - 25M_REF_CLK
001 - SYSTEM_PLL2_DIV5
010 - SYSTEM_PLL1_DIV2
011 - SYSTEM_PLL2_DIV6
100 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL1_CLK
111 - 32K_REF_CLK

However, in imx8mq_clko2_sels[] only the first four entries are correct.

Fix it by adding the missing "sys3_pll2_out" entry in order to match
the description from the manual.

Fixes: b80522040c ("clk: imx: Add clock driver for i.MX8MQ CCM")
Reported-by: Rogerio Pimentel <rogerio.silva@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:17 -08:00
Carlo Caione
81bf81e7d3 clk: imx8mq: Add missing M4 clocks
The clocks list is missing the clocks for the M4 core.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Bai Ping
ba5625c3e2 clk: imx: Add clock driver support for imx8mm
Add clock driver support for i.MX8MM SOC.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Bai Ping
8646d4dcc7 clk: imx: Add PLLs driver for imx8mm soc
New PLLs are introduced on i.MX8M Mini SOC.
PLL1416X is Integer PLL, PLL1443X is a Frac PLL.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Michael Grzeschik
9b15cffbf2 clk: imx5: add imx5_SCC2_IPG_GATE
This adds the missing clock for the SCC2 peripheral unit.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Aisheng Dong
666aed2d13 clk: imx: scu: add set parent support
Add clk scu set parents support.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@kernel.org: Remove le32_to_cpu() on get_parent op]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Aisheng Dong
cd67d32727 clk: imx: scu: add fallback compatible string support
SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs.
Make the driver support "fsl,scu-clk" fallback compatible string
to allow other SoCs to reuse the common part.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Abel Vesa
402564aee0 clk: imx8mq: Make parent names arrays const pointers
The arrays containing the mux selectors need to be of const pointer
to const char.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Abel Vesa
470663e078 clk: imx: Make parents const pointer in mux wrappers
The parents needs to be pointer to const pointer to const char.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Abel Vesa
65a6b7c5f3 clk: imx: Make parent_names const pointer in composite-8m
The parent_names needs to be pointer to const pointer to const char.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Alexandre Belloni
65a91e2e59 clk: at91: fix masterck name
The master clock is actually named masterck earlier in the driver. Having
"mck" in the parent list means that it can never be selected.

Fixes: 1eabdc2f9d ("clk: at91: add at91sam9x5 PMCs driver")
Fixes: a2038077de ("clk: at91: add sama5d2 PMC driver")
Fixes: 084b696bb5 ("clk: at91: add sama5d4 pmc driver")
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: <stable@vger.kernel.org> # v4.20+
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-20 11:40:21 -08:00
Alexandre Belloni
1b328a2e09 clk: at91: fix at91sam9x5 peripheral clock number
nck() looks at the last id in an array and unfortunately,
at91sam9x35_periphck has a sentinel, hence the id is 0 and the calculated
number of peripheral clocks is 1 instead of a maximum of 31.

Fixes: 1eabdc2f9d ("clk: at91: add at91sam9x5 PMCs driver")
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: <stable@vger.kernel.org> # v4.20+
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-20 11:34:24 -08:00
Wei Yongjun
bb8727096c clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static
Fixes the following sparse warning:

drivers/clk/tegra/clk-tegra124-dfll-fcpu.c:244:18: warning:
 symbol 'tegra210_cpu_cvb_tables' was not declared. Should it be static?

Fixes: 2b2dbc2f94 ("clk: tegra: dfll: add CVB tables for Tegra210")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-18 11:16:22 +01:00
Arnd Bergmann
7e5c4c26c7 clk: tegra: Changes for v5.1-rc1
This contains a couple of prerequisite patches to enable CPU frequency
 scaling on Tegra210.
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Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

clk: tegra: Changes for v5.1-rc1

This contains a couple of prerequisite patches to enable CPU frequency
scaling on Tegra210.

* tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210
  clk: tegra: dfll: add CVB tables for Tegra210
  clk: tegra: dfll: round down voltages based on alignment
  clk: tegra: dfll: support PWM regulator control
  clk: tegra: dfll: CVB calculation alignment with the regulator
  clk: tegra: dfll: registration for multiple SoCs

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15 17:31:41 +01:00
Andreas Kemnade
fddf4e29a6 clk: ti: check clock type before doing autoidle ops
Code might use autoidle api with clocks not being omap2 clocks,
so check if clock type is really omap2.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-02-15 16:47:55 +02:00
Andreas Kemnade
d277ce2d3a clk: ti: add a usecount for autoidle
Multiple users might deny autoidle on a clock. So we should have some
counting here, also according to the comment in  _setup_iclk_autoidle().
Also setting autoidle regs is not atomic, so there is another reason
for locking.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-02-15 16:47:55 +02:00
Tero Kristo
ead478250b clk: ti: generalize the init sequence of clk_hw_omap clocks
Add a generic API for initializing clocks of clk_hw_omap type clocks,
and convert the whole TI clock driver suite to use this for registering
the clocks. Also, get rid of the now redundant API for adding the clocks
to the OMAP HW clocks list; instead this is used directly from the
register API.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-15 16:46:22 +02:00
Tero Kristo
8aa09cf322 clk: ti: remove usage of CLK_IS_BASIC
Remove the usage of CLK_IS_BASIC flag completely from TI clock driver.
In most cases, the use is completely redundant, but in some cases
we need to use the new API to check if the clock is an OMAP clock or not.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-15 16:46:22 +02:00
Tero Kristo
7fd79ee78a clk: ti: add new API for checking if a provided clock is an OMAP clock
omap2_clk_is_hw_omap can now be used to verify if the provided clk_hw
is an omap HW clock or not. This is done to replace the usage of CLK_IS_BASIC
flag within the TI clock drivers.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-15 16:46:21 +02:00
Tero Kristo
77b773aea5 clk: ti: move clk_hw_omap list handling under generic part of the driver
Currently the clk_hw_omap list is handled under the autoidle code, but
it should be accessible generically. Add a few APIs towards this, and
update the autoidle code to use the generic implementations.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-15 16:46:21 +02:00
Stephen Boyd
05c3ae7aa1 Allwinner clock fixes for 5.0
Two fixes for clock indices, one for the A31 and one for the V3s.
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Merge tag 'sunxi-clk-fixes-for-5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

Pull Allwinner clock fixes from Maxime Ripard:

Two fixes for clock indices, one for the A31 and one for the V3s.

* tag 'sunxi-clk-fixes-for-5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi: A31: Fix wrong AHB gate number
  clk: sunxi-ng: v3s: Fix TCON reset de-assert bit
2019-02-13 09:01:21 -08:00
Martin Blumenstingl
c5f09e6bd8 clk: meson: meson8b: fix the naming of the APB clocks
Fix a typo in the APB clock names by renaming them from "abp" to "apb".
No functional changes.

Fixes: a7d19b05ce ("clk: meson: meson8b: add the CPU clock post divider clocks")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190210222603.6404-2-martin.blumenstingl@googlemail.com
2019-02-13 09:51:09 +01:00
Neil Armstrong
042f01bb7f clk: meson: Add G12A AO Clock + Reset Controller
Add the Amlogic G12A AO Clock and Reset controller driver handling
generation of Always-On clocks :
- AO Clocks and Reset for Always-On modules
- 32K Generation for USB and CEC
- SAR ADC controller clock

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190212162859.20743-3-narmstrong@baylibre.com
2019-02-13 09:49:32 +01:00
Matti Vaittinen
d3236214e7 clk: clk-st: avoid clkdev lookup leak at remove
Use devm based clkdev lookup registration to avoid leaking lookup
structures.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06 10:35:04 -08:00
Matti Vaittinen
8144e1e8ca clk: clk-max77686: Clean clkdev lookup leak and use devm
clk-max77686 never clean clkdev lookup at remove. This can cause
oops if clk-max77686 is removed and inserted again. Fix leak by
using new devm clkdev lookup registration. Simplify also error
path by using new devm_of_clk_add_hw_provider.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06 10:35:03 -08:00
Matti Vaittinen
3eee6c7d11 clkdev: add managed clkdev lookup registration
Clkdev registration lacks of managed registration functions and it
seems few drivers do not drop clkdev lookups at exit. Add
devm_clk_hw_register_clkdev and devm_clk_release_clkdev to ease lookup
releasing at exit.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06 10:35:02 -08:00
Phil Edworthy
60b8f0ddf1 clk: Add (devm_)clk_get_optional() functions
This adds clk_get_optional() and devm_clk_get_optional() functions to get
optional clocks.

They behave the same as (devm_)clk_get() except where there is no clock
producer. In this case, instead of returning -ENOENT, the function
returns NULL. This makes error checking simpler and allows
clk_prepare_enable, etc to be called on the returned reference
without additional checks.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Russell King <linux@armlinux.org.uk>
[sboyd@kernel.org: Document in devres.txt]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06 10:33:10 -08:00
Phil Edworthy
5c56dfe63b clk: Add comment about __of_clk_get_by_name() error values
It's not immediately obvious from the code that failure to get a
clock provider can return either -ENOENT or -EINVAL. Therefore, add
a comment to highlight this.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Russell King <linux@armlinux.org.uk>
[sboyd@kernel.org: Fix comment to be proper C with ==]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06 10:32:42 -08:00
Peter De Schrijver
8bf9437a4e clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210
Tegra210 has a DFLL as well and can share the majority of the code with
the Tegra124 implementation. So build the same code for both platforms.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:29:37 +01:00
Joseph Lo
2b2dbc2f94 clk: tegra: dfll: add CVB tables for Tegra210
Add CVB tables with different chip characterization, so that we can
generate the customize OPP table that suitable for different chips with
different SKUs.

The parameter 'tune_high_min_millivolts' is first time introduced in
this patch, which didn't use in the DFLL driver for clock and voltage
tuning before. It will be used later when DFLL in high voltage range.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:29:23 +01:00
Joseph Lo
f7ebf8874c clk: tegra: dfll: round down voltages based on alignment
When generating the OPP table, the voltages are round down with the
alignment from the regulator. The alignment should be applied for
voltages look up as well.

Based on the work of Penny Chiu <pchiu@nvidia.com>.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:29:08 +01:00
Joseph Lo
36541f0499 clk: tegra: dfll: support PWM regulator control
The DFLL hardware supports two modes (I2C and PWM) for voltage control
when requesting a frequency. In this patch, we introduce PWM mode support.

To support that, we re-organize the LUT for unifying the table for both
cases of I2C and PWM mode. And generate that based on regulator info.
For the PWM-based regulator, we get this info from DT. And do the same as
the case of I2C LUT, which can help to map the PMIC voltage ID and voltages
that the regulator supported.

The other parts are the support code for initializing the DFLL hardware
to support PWM mode. Also, the register debugfs file is slightly
reworked to only show the i2c registers when I2C mode is in use.

Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:28:55 +01:00
Joseph Lo
b3cf8d0695 clk: tegra: dfll: CVB calculation alignment with the regulator
The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset parameters depend
on the regulator supplying vdd-cpu, not on the specific Tegra SKU.

When using a PWM controlled regulator, the voltage step and offset are
determined by the regulator type in use. This is specified in DT. When
using an I2C controlled regulator, we can retrieve them from CPU regulator
Then pass this information to the CVB table calculation function.

Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>"
and "Alex Frid <afrid@nvidia.com>".

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:28:41 +01:00
Peter De Schrijver
b0dcfb78dc clk: tegra: dfll: registration for multiple SoCs
In a future patch, support for the DFLL in Tegra210 will be introduced.
This requires support for more than 1 set of CVB and CPU max frequency
tables.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:28:25 +01:00
Paul Cercueil
b7e29924a1 clk: ingenic: jz4740: Fix gating of UDC clock
The UDC clock is gated when the bit is cleared, not when it is set.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Fixes: 2b555a4b9c ("clk: ingenic: Add missing flag for UDC clock")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-05 13:32:26 -08:00
Weiyi Lu
51ff86dd10 clk: mediatek: update clock driver of MT2712
According to 3rd ECO design change,
1. Add new fixed factor clock of audio.
2. Add the parent clocks for audio clock mux.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-05 13:28:04 -08:00
Biju Das
d1de227de8 clk: renesas: r8a774c0: Add TMU clock
This patch adds the TMU clocks to the R8A774C0 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-02-05 10:40:05 +01:00
Sergei Shtylyov
94e3935b57 clk: renesas: r8a77980: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the R-Car V3H (R8A77980) CPG/MSSR
driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-02-05 10:40:05 +01:00
Sergei Shtylyov
db4a0073cc clk: renesas: rcar-gen3: Add RPC clocks
The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all
the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field
is different between SoCs; it makes sense to support the most common case
of this encoding in the R-Car gen3 CPG driver...

After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from
it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except
V3M (R8A77970); the composite clock driver seems handy for this task, using
the spinlock added in the previous patch...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-02-05 10:40:05 +01:00
Jerome Brunet
6682bd4d44 clk: meson: factorise meson64 peripheral clock controller drivers
The function used to probe the peripheral clock controller of the arm64
amlogic SoCs is mostly the same. We now have 3 of those controllers so
it is time to factorize things a bit.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com
2019-02-04 09:52:11 +01:00
Jian Hu
085a4ea93d clk: meson: g12a: add peripheral clock controller
Add the peripheral clock controller found in the g12a SoC family

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com
2019-02-04 09:52:11 +01:00
Jerome Brunet
8eed1db1ad clk: meson: pll: update driver for the g12a
The g12a use fractional parameter of 17 useful bits. At the moment, this
parameter in encoded using u16 value. Use this opportunity to switch all
the pll to parameter to unsigned int. This should save us some annoying
trouble shooting when and m and n field eventually grow as well.

This patch also introduce pll multiplier range. On the g12a, the hifi and
gp0 plls are able to lock as long as the following condition is met:
55 <= m/n <= 255.

The param table describing this would be huge which is a waste of memory.
Using ranges, we can save memory. Ranges also help find the best pll
parameter significantly faster since we don't have to try all the possible
settings.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[jbrunet: fixed fix pll settings calculation with arm32]
Link: https://lkml.kernel.org/r/20190201145345.6795-2-jbrunet@baylibre.com
2019-02-04 09:51:37 +01:00
Jerome Brunet
889c2b7ec4 clk: meson: rework and clean drivers dependencies
Initially, the meson clock directory only hosted 2 controllers drivers,
for meson8 and gxbb. At the time, both used the same set of clock drivers
so managing the dependencies was not a big concern.

Since this ancient time, entropy did its job, controllers with different
requirement and specific clock drivers have been added. Unfortunately, we
did not do a great job at managing the dependencies between the
controllers and the different clock drivers. Some drivers, such as
clk-phase or vid-pll-div, are compiled even if they are useless on the
target (meson8). As we are adding new controllers, we need to be able to
pick a driver w/o pulling the whole thing.

The patch aims to clean things up by:
* providing a dedicated CONFIG_ for each clock drivers
* allowing clock drivers to be compiled as a modules, if possible
* stating explicitly which drivers are required by each controller.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201125841.26785-5-jbrunet@baylibre.com
2019-02-02 17:43:32 +01:00
Jerome Brunet
cb78ba7629 clk: meson: axg-audio does not require syscon
The axg audio clock controller uses regmap mmio, not syscon.

Fixes: 1cd5018175 ("clk: meson: axg: add the audio clock controller driver")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201125841.26785-4-jbrunet@baylibre.com
2019-02-02 17:43:08 +01:00
Jerome Brunet
6e47b53073 clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory
Use CONFIG_ARCH_MESON to let make enter the meson clock directory.
As part of a rework, CONFIG_COMMON_CLK_AMLOGIC is about to be removed.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201125841.26785-3-jbrunet@baylibre.com
2019-02-02 17:42:50 +01:00
Jerome Brunet
12aa377bf8 clk: export some clk_hw function symbols for module drivers
clk-provider.h provides clk_hw_is_prepared(), clk_hw_is_enabled() and
clk_hw_is_prepared() but these symbols are not exported for the
modules which prevents a clock driver using them to be compiled as
a module. Export them to fix the problem.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201125841.26785-2-jbrunet@baylibre.com
2019-02-02 17:42:02 +01:00
Stephen Boyd
73d4f945f6 clk: Document and simplify clk_core_get_rate_nolock()
This function uses a few gotos and doesn't explain why parents and
numbers of parents are being checked before returning different values
for the clk's rate. Document and simplify this function somewhat to make
this better.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-01 15:40:17 -08:00
Kamil Konieczny
81faa30df9 clk: samsung: exynos5433: Add selected IMEM clocks
This patch adds clocks required for the Exynos5433 SoC Slim Security
SubSystem (SlimSSS) IP block.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
[s.nawrocki@samsung.com: edited commit description]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-02-01 14:36:47 +01:00
Kamil Konieczny
b80a40c659 clk: samsung: exynos5433: Fix name typo in sssx
Fix typo in sssx name, there should be three letters 's'.

Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-02-01 14:36:47 +01:00
Kamil Konieczny
4e16c9ef2a clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocks
This fixes typos in CLK_ACLK_IMEM_200 and CLK_ACLK_IMEM_266 clock definition,
leading to incorrect parent clock assignment.

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
[s.nawrocki@samsung.com: edited commit description]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-02-01 14:36:47 +01:00
Andre Przywara
ee0b27a3a4
clk: sunxi: A31: Fix wrong AHB gate number
According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.

Fix the gate bit definitions in the clock driver.

Fixes: c6e6c96d8f ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-28 09:26:32 +01:00
Sergei Shtylyov
875e8f6b01 clk: renesas: rcar-gen3: Add spinlock
Protect the CPG register read-modify-write sequence with a spinlock.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-25 11:26:22 +01:00
Sergei Shtylyov
8cb8f16c62 clk: renesas: rcar-gen3: Factor out cpg_reg_modify()
There's quite often repeated sequence of a CPG register read-modify-write,
so it seems worth factoring it out into a function -- this saves 68 bytes
of the object code (AArch64 gcc 4.8.5) and simplifies protecting all such
sequences with a spinlock in the next patch...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-25 11:26:22 +01:00
Chen-Yu Tsai
108a459ef4
clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it
The PLL-MIPI clock is somewhat special as it has its own LDOs which
need to be turned on for this PLL to actually work and output a clock
signal.

Add the 2 LDO enable bits to the gate bits.

Fixes: 5690879d93 ("clk: sunxi-ng: Add A23 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-25 10:43:44 +01:00
Stephen Boyd
7150e182c8 clk: nxp: Drop 'flags' on fixed_rate clk macro
The flags argument here is always 0, and we want to get rid of the flags
member of the clk_fixed_rate struct. So remove this here and just pass 0
when it's used.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 14:21:29 -08:00
Stephen Boyd
777c1a40a3 clk: Document __clk_mux_determine_rate()
It had some documentation, but not kerneldoc style so it wasn't getting
picked up. Add some docs so scripts can pick this function out.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 14:21:14 -08:00
Stephen Boyd
9fe9b7ab4d clk: Document deprecated things
We don't want driver authors to use the struct clk based registration
and provider APIs. Instead, they should use the clk_hw based APIs. Add
some notes in the kerneldoc to this effect.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 14:21:13 -08:00
Matteo Croce
463a554baa clk: samsung: fix typo
Fix spelling mistake: "lenght" -> "length"

Signed-off-by: Matteo Croce <mcroce@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 14:17:53 -08:00
Taniya Das
9ff1a3b491 clk: qcom: gcc: Use active only source for CPUSS clocks
The clocks of the CPUSS such as "gcc_cpuss_ahb_clk_src" is a CRITICAL
clock and needs to vote on the active only source of XO, so as to keep
the vote as long as CPUSS is active. Similar rbcpr_clk_src is also has
the same requirement.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Fixes: 06391eddb6 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:41:48 -08:00
Gustavo A. R. Silva
921e88a4f9 clk: imx: imx7ulp: use struct_size() in kzalloc()
One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:

struct foo {
    int stuff;
    void *entry[];
};

instance = kzalloc(sizeof(struct foo) + sizeof(void *) * count, GFP_KERNEL);

Instead of leaving these open-coded and prone to type mistakes, we can
now use the new struct_size() helper:

instance = kzalloc(struct_size(instance, entry, count), GFP_KERNEL);

This issue was detected with the help of Coccinelle.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:37:46 -08:00
Stephen Boyd
a30a67be7b clk: socfpga: Don't have get_parent for single parent ops
This driver creates a gate clk with the possibility to have multiple
parents. That can cause problems if the common clk framework tries to
call the get_parent() op and gets back a number that's larger than the
number of parents the clk says it supports in
clk_init_data::num_parents. Let's duplicate the clk_ops structure each
time this function is called and drop the get/set parent ops when there
is only one parent. This allows the framework to consider a number
larger than clk_init_data::num_parents as an error condition of the
get_parent() clk op, clearing the way for proper code.

Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:36:25 -08:00
Dan Carpenter
303aef8b84 clk: ti: Fix error handling in ti_clk_parse_divider_data()
The ti_clk_parse_divider_data() function is only called from
_get_div_table_from_setup().  That function doesn't look at the return
value but instead looks at the "*table" pointer.  In this case, if the
kcalloc() fails then *table is NULL (which means success).  It should
instead be an error pointer.

The ti_clk_parse_divider_data() function has two callers.  One checks
for errors and the other doesn't.  I have fixed it so now both handle
errors.

Fixes: 4f6be5655d ("clk: ti: divider: add driver internal API for parsing divider data")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:23:32 -08:00
Abel Vesa
a64a9c088b clk: imx: Fix fractional clock set rate computation
Before multiplying by PLL_FRAC_DENOM, the temp64 needs to be
 temp64 = rate * 2 - divfi * parent_rate * 8, instead of:
 temp64 = (rate * 2 - divfi) * parent_rate

Fixes: 6209624b9a ("clk: imx: Add fractional PLL output clock")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:17:28 -08:00
Derek Basehore
ede7785847 clk: Remove global clk traversal on fetch parent index
It's not required to traverse the entire clk tree when the parents array
contains a NULL value. We already have the parent clk_core pointer, so
we can just compare the parent->name and parent_names[i] pointers.

This can be a substantial power improvement in cases where the parent
clk isn't known and that clk is never registered, because a mux having
an unregistered parent name may traverse the clk tree on every
clk_set_rate() call in clk_mux_determine_rate_flags(). This can happen
hundreds of times a second for CPU clks.

This patch is the combination of reverting commit 470b5e2f97 ("clk:
simplify clk_fetch_parent_index() function") and optimizing the
resulting code to never call __clk_lookup() because we already have the
clk_core pointer we're looking for. That optimization went unnoticed
even after commit da0f0b2c3a ("clk: Correct lookup logic in
clk_fetch_parent_index()") tried to optimize this path.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
[sboyd@kernel.org: More description in commit text]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:13:28 -08:00
Lubomir Rintel
0acb69e7b9 Revert "clk: mmp2: add SP clock"
It seems that the kernel has no business managing this clock: once the SP
clock is disabled, it's not sufficient to just enable in order to bring the
SP core back up. Just let the firmware keep it enabled and don't expose it
to drivers.

This reverts commit fc27c2394d.

Link: https://lore.kernel.org/lkml/154783267051.169631.3197836544646625747@swboyd.mtv.corp.google.com/
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 10:55:32 -08:00
Geert Uytterhoeven
d9286d9743 clk: renesas: r8a774c0: Correct parent clock of DU
According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
the parent clock of the DU module clocks on RZ/G2E is S1D1.

Fixes: 906e0a4a6d ("clk: renesas: cpg-mssr: Add r8a774c0 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-24 16:01:08 +01:00
Paul Kocialkowski
5c59801f70
clk: sunxi-ng: v3s: Fix TCON reset de-assert bit
According to the datasheet and the reference code from Allwinner, the
bit used to de-assert the TCON reset is bit 4, not bit 3.

Fix it in the V3s CCU driver.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-22 10:03:04 +01:00
Fabrizio Castro
9d034e151b clk: renesas: r8a774a1: Add missing CANFD clock
This patch adds the missing CANFD clock to the r8a774a1 specific
clock driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-21 14:01:57 +01:00
Fabrizio Castro
2a6efbc6da clk: renesas: r8a774c0: Add missing CANFD clock
This patch adds the missing CANFD clock to the r8a774c0 specific
clock driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-21 13:50:40 +01:00
Jerome Brunet
439a6bb5bf clk: meson: ao-clkc: claim clock controller input clocks from DT
Instead of relying on a fixed names for the differents input clocks
of the controller, get them through DT.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190116175435.4990-4-jbrunet@baylibre.com
2019-01-18 10:51:39 +01:00
Jerome Brunet
6e73dac707 clk: meson: axg: claim clock controller input clock from DT
Instead of relying on a fixed name for the xtal clock, claim the
controller input clock trough DT.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190116175435.4990-3-jbrunet@baylibre.com
2019-01-18 10:51:14 +01:00
Jerome Brunet
c0e6f5bf76 clk: meson: gxbb: claim clock controller input clock from DT
Instead of relying on a fixed name for the xtal clock, claim the
controller input clock trough DT.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190116175435.4990-2-jbrunet@baylibre.com
2019-01-18 10:49:26 +01:00
Dinh Nguyen
b488517b28 clk: socfpga: stratix10: fix naming convention for the fixed-clocks
The fixed clocks in the DTS file have a hyphen, but the clock driver has
the fixed clocks using underbar. Thus the clock driver cannot detect the
other fixed clocks correctly. Change the fixed clock names to a hyphen.

Fixes: 07afb8db73 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-15 12:58:38 -08:00
Dinh Nguyen
c0a636e4cc clk: socfpga: stratix10: fix rate calculation for pll clocks
The main PLL calculation has a mistake. We should be using the
multiplying the VCO frequency, not the parent clock frequency.

Fixes: 07afb8db73 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-11 15:41:02 -08:00
Marc Gonzalez
83b4c14796 clk: qcom: Select QCOM_GDSC with MSM_GCC_8998
If QCOM_GDSC is disabled, gdsc_register() returns -ENOSYS, which causes
gcc_msm8998_probe() to fail. Select QCOM_GDSC to solve the problem.

gcc-msm8998: probe of 100000.clock-controller failed with error -38

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Fixes: b5f5f525c5 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-11 10:39:15 -08:00
Alexander Shiyan
31cc9e0968 clk: clps711x: Remove board support
Since board support for the CLPS711X platform was removed,
remove the board support from the clk-clps711x driver.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 12:50:21 -08:00
Michał Mirosław
77977b8004 clk: at91: enable AUDIOPLL as source for PCKx on SAMA5D2
Datasheet for SAMA5D2x mentions 6 sources for PCKx, the last being AUDIOPLL.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 11:49:35 -08:00
Jeffrey Hugo
6131dc8121 clk: qcom: smd: Add support for MSM8998 rpm clocks
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.

Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 11:46:42 -08:00
Jan Kotas
50cc4caf53 clk: Add Fixed MMIO clock driver
This patch adds a driver for Fixed MMIO clock.
The driver reads a clock frequency value from a single 32-bit memory
mapped register and registers it as a fixed rate clock.

It can be enabled with COMMON_CLK_FIXED_MMIO Kconfig option.

Signed-off-by: Jan Kotas <jank@cadence.com>
[sboyd@kernel.org: Make of_fixed_mmio_clk_setup() static, use clk_hw
based APIs]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 11:41:19 -08:00
Jeffrey Hugo
5f2420ed21 clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998
The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by
the phy during init.  The clock needs to be enabled during the init
sequence, but may not be fully active until after the init sequence is
complete.  This causes a catch-22 if the clock status is checked during
enable.  As a result, skip the checks to avoid the troubling situation.

Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:57:29 -08:00
Jeffrey Hugo
0c8ff62504 clk: qcom: Add missing freq for usb30_master_clk on 8998
The usb30_master_clk supports a 60Mhz frequency, but that is missing from
the table of supported frequencies.  Add it.

Fixes: b5f5f525c5 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:57:26 -08:00
Jeffrey Hugo
26fe27d920 clk: qcom: Add CLK_SET_RATE_PARENT for 8998 branch clocks
A branch clock is basically a clock that can be gated for power savings,
but is also what devices/drivers consume.  Configuring a branch clock's
rate needs to be done at the source, so for all branch clocks which have
a defined parent, set CLK_SET_RATE_PARENT so that clk_set_rate() calls on
branch clocks can do what is expected.  This is important as most drivers
do not check the resulting clock rate after a successful clk_set_rate()
call, thus the driver may get out of sync with the actual hardware state
and weird issues might crop up.  This has been observed with issues
getting SDHCI to reliably support "fast" cards such as SDR104.

Fixes: 4807c71cc6 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:57:22 -08:00
Marek Vasut
2137a109a5 clk: vc5: Abort clock configuration without upstream clock
In case the upstream clock are not set, which can happen in case the
VC5 has no valid upstream clock, the $src variable is used uninited
by regmap_update_bits(). Check for this condition and return -EINVAL
in such case.

Note that in case the VC5 has no valid upstream clock, the VC5 can
not operate correctly. That is a hardware property of the VC5. The
internal oscilator present in some VC5 models is also considered
upstream clock.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-renesas-soc@vger.kernel.org
[sboyd@kernel.org: Added comment about probe preventing this from
happening in the first place]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:53:58 -08:00
Lubomir Rintel
c6e909972e clk: sysfs: fix invalid JSON in clk_dump
Add a missing comma so that the output is valid JSON format again.

Fixes: 9fba738a53 ("clk: add duty cycle support")
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:45:03 -08:00
Abel Vesa
3d51e4d9de clk: imx: Remove Kconfig duplicate include
Commit d360b130e2 ("clk: imx: Make the i.MX8MQ CCM clock driver
CLK_IMX8MQ dependant") introduced this duplicate and incorrectly ordered
kconfig include.

Fixes: d360b130e2 ("clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:43:41 -08:00
Gustavo A. R. Silva
4f340efcb2 clk: zynqmp: Fix memory allocation in zynqmp_clk_setup
Fix memory allocation and use struct_size() in kzalloc(). This also
fixes the allocation size to be correct, and smaller, because before we
were allocating a bunch of sizeof(struct clk_hw_onecell_data) structures
for each struct clk_hw we needed.

Fixes: 3fde0e16d0 ("drivers: clk: Add ZynqMP clock driver")
Cc: stable@vger.kernel.org
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
[sboyd@kernel.org: Expand commit text]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:37:01 -08:00
Dan Carpenter
d39eca547f clk: tegra: dfll: Fix a potential Oop in remove()
If tegra_dfll_unregister() fails then "soc" is an error pointer.  We
should just return instead of dereferencing it.

Fixes: 1752c9ee23 ("clk: tegra: dfll: Fix drvdata overwriting issue")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:35:37 -08:00
Wei Yongjun
48504619a6 clk: imx: fix potential NULL dereference in imx8qxp_lpcg_clk_probe()
platform_get_resource() may fail and return NULL, so we should
better check it's return value to avoid a NULL pointer dereference
a bit later in the code.

This is detected by Coccinelle semantic patch.

@@
expression pdev, res, n, t, e, e1, e2;
@@

res = platform_get_resource(pdev, t, n);
+ if (!res)
+   return -EINVAL;
... when != res == NULL
e = devm_ioremap(e1, res->start, e2);

Fixes: 1e3121bfe5 ("clk: imx: add imx8qxp lpcg driver")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:34:54 -08:00
Martin Blumenstingl
74e1f2521f clk: meson: meson8b: add the GPU clock tree
Add the GPU clock tree on Meson8, Meson8b and Meson8m2.

The GPU clock tree on Meson8b and Meson8m2 is almost identical to the
one one GXBB:
- there's a glitch-free mux at HHI_MALI_CLK_CNTL[31]
- there are two identical parents for this mux: mali_0 and mali_1, each
  with a gate, divider and mux
- the parents of mali_0_sel and mali_1_sel are identical to GXBB except
  there's no GP0_PLL on these 32-bit SoCs

Meson8 is different because it does not have the glitch-free mux.
Instead if only has the mali_0 clock tree. The parents of mali_0_sel are
identical to the ones on Meson8b and Meson8m2.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181208171247.22238-4-martin.blumenstingl@googlemail.com
2019-01-07 15:35:13 +01:00
Martin Blumenstingl
cce433e6bc clk: meson: meson8b: use a separate clock table for Meson8
The Meson8 SoC is slightly different compared to Meson8b and Meson8m2
because it does not have the glitch-free Mali GPU clock mux. For Meson8b
and Meson8m2 there are currently no known differences.

Add a separate clk_hw_onecell_data table for Meson8 so these differences
can be implemented. For now meson8_hw_onecell_data is a clone of our
existing meson8b_hw_onecell_data.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181208171247.22238-3-martin.blumenstingl@googlemail.com
2019-01-07 15:34:54 +01:00
Jerome Brunet
172e95346d clk: meson: axg-ao: add 32k generation subtree
Add the clock subtree generating the 32k clock in amlogic axg ao block.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181221160239.26265-6-jbrunet@baylibre.com
2019-01-07 15:21:43 +01:00
Jerome Brunet
b249623fd1 clk: meson: gxbb-ao: replace cec-32k with the dual divider
Replace the cec-32k clock of gxbb-ao with the simpler dual divider
driver. The dual divider implements only the dividing part. All the
other bits are now exposed using simple elements, such as gates and
muxes

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181221160239.26265-5-jbrunet@baylibre.com
2019-01-07 15:21:22 +01:00
Jerome Brunet
a8d552a638 clk: meson: add dual divider clock driver
Add the dual divider driver. This special divider make a weighted
average between 2 dividers to reach fractional divider values.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181221160239.26265-4-jbrunet@baylibre.com
2019-01-07 15:21:01 +01:00
Jerome Brunet
8d9981efbc clk: meson: clean-up clock registration
Order, ids and size  between the table of regmap clocks and the onecell
data table could be different.

Set regmap pointer in all the regmap clocks before starting the
registration using the onecell data, to make sure we don't
get into an incoherent situation.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181221160239.26265-3-jbrunet@baylibre.com
2019-01-07 15:20:41 +01:00
Finley Xiao
491b00ff69 clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
Add CLK_SET_RATE_PARENT for both rk3066 lcdc dclk.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-01-07 09:17:15 +01:00
Katsuhiro Suzuki
a0e447b0c5 clk: rockchip: fix frac settings of GPLL clock for rk3328
This patch fixes settings of GPLL frequency in fractional mode for
rk3328. In this mode, FOUTVCO is calcurated by following formula:
  FOUTVCO = FREF * FBDIV / REFDIV + ((FREF * FRAC / REFDIV) >> 24)

The problem is in FREF * FRAC >> 24 term. This result always lacks
one from target value is specified by rate member. For example first
itme of rk3328_pll_frac_rate originally has
  - rate  : 1016064000
  - refdiv: 3
  - fbdiv : 127
  - frac  : 134217
  - FREF * FBDIV / REFDIV        = 1016000000
  - (FREF * FRAC / REFDIV) >> 24 = 63999
Thus calculated rate is 1016063999. It seems wrong.

If frac has 134218 (it is increased 1 from original value), second
term is 64000. All other items have same situation. So this patch
adds 1 to frac member in all items of rk3328_pll_frac_rate.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Acked-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-01-07 09:17:15 +01:00
Linus Torvalds
645ff1e8e7 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
Pull input updates from Dmitry Torokhov:
 "A tiny pull request this merge window unfortunately, should get more
  material in for the next release:

   - new driver for Raspberry Pi's touchscreen (firmware interface)

   - miscellaneous input driver fixes"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input:
  Input: elan_i2c - add ACPI ID for touchpad in ASUS Aspire F5-573G
  Input: atmel_mxt_ts - don't try to free unallocated kernel memory
  Input: drv2667 - fix indentation issues
  Input: touchscreen - fix coding style issue
  Input: add official Raspberry Pi's touchscreen driver
  Input: nomadik-ske-keypad - fix a loop timeout test
  Input: rotary-encoder - don't log EPROBE_DEFER to kernel log
  Input: olpc_apsp - remove set but not used variable 'np'
  Input: olpc_apsp - enable the SP clock
  Input: olpc_apsp - check FIFO status on open(), not probe()
  Input: olpc_apsp - drop CONFIG_OLPC dependency
  clk: mmp2: add SP clock
  dt-bindings: marvell,mmp2: Add clock id for the SP clock
  Input: ad7879 - drop platform data support
2019-01-02 18:56:59 -08:00
Yangtao Li
8d726c5128 clk: dove: fix refcount leak in dove_clk_init()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Fixes: 8f7fc5450b ("clk: mvebu: dove: maintain clock init order")
Fixes: 63b8d92c79 ("clk: add Dove PLL divider support for GPU, VMeta and AXI clocks")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:45:43 -08:00
Yangtao Li
9b4eedf627 clk: mv98dx3236: fix refcount leak in mv98dx3236_clk_init()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Fixes: 3370726042 ("clk: mvebu: Expand mv98dx3236-core-clock support")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:45:41 -08:00
Yangtao Li
db20a90a4b clk: armada-xp: fix refcount leak in axp_clk_init()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Fixes: 0a11a6ae94 ("clk: mvebu: armada-xp: maintain clock init order")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:45:38 -08:00
Yangtao Li
e7beeab9c6 clk: kirkwood: fix refcount leak in kirkwood_clk_init()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Fixes: 58d516ae95 ("clk: mvebu: kirkwood: maintain clock init order")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:45:32 -08:00
Yangtao Li
a3c24050bd clk: armada-370: fix refcount leak in a370_clk_init()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Fixes: 07ad6836fa ("clk: mvebu: armada-370: maintain clock init order")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:42:41 -08:00
Yangtao Li
567177024e clk: vf610: fix refcount leak in vf610_clocks_init()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Fixes: 1f2c5fd5f0 ("ARM: imx: add VF610 clock support")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:40:59 -08:00
Yangtao Li
5f8c183a99 clk: imx7d: fix refcount leak in imx7d_clocks_init()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Fixes: 8f6d8094b2 ("ARM: imx: add imx7d clk tree support")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:40:44 -08:00
Yangtao Li
1731e14fb3 clk: imx6sx: fix refcount leak in imx6sx_clocks_init()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Fixes: d551356890 ("ARM: imx: add clock driver for imx6sx")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:40:25 -08:00
Yangtao Li
c9ec1d8fef clk: imx6q: fix refcount leak in imx6q_clocks_init()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Fixes: 2acd1b6f88 ("ARM: i.MX6: implement clocks using common clock framework")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:40:04 -08:00
Yangtao Li
cee82eb953 clk: samsung: exynos4: fix refcount leak in exynos4_get_xom()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Fixes: e062b57177 ("clk: exynos4: register clocks using common clock framework")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:38:30 -08:00
Yangtao Li
7f9705beeb clk: socfpga: fix refcount leak
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Fixes: 5343325ff3 ("clk: socfpga: add a clock driver for the Arria 10 platform")
Fixes: a30d27ed73 ("clk: socfpga: fix clock driver for 3.15")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:29:06 -08:00
Yangtao Li
2274d8001f clk: ti: fix refcount leak in ti_dt_clocks_register()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Fixes: 5b385a45e0 ("clk: ti: add support for clkctrl aliases")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:27:08 -08:00
Yangtao Li
70af6c5b52 clk: qoriq: fix refcount leak in clockgen_init()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Fixes: 0dfc86b317 ("clk: qoriq: Move chip-specific knowledge into driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:23:31 -08:00
Yangtao Li
5eb8ba9095 clk: highbank: fix refcount leak in hb_clk_init()
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Fixes: 26cae166cf ("ARM: highbank: remove custom .init_time hook")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 11:20:48 -08:00
Aisheng Dong
08972760d3 clk: imx8qxp: make the name of clock ID generic
SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs.
Let's make the name of clock ID generic to allow other SoCs to reuse
the common part.

This patch only changes the clock id name and file name, so no
functional change.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28 10:43:57 -08:00
Stephen Boyd
b677574bdf Merge branch 'clk-imx7ulp' into clk-next
* clk-imx7ulp:
  clk: imx: imx7ulp: add arm hsrun mode clocks support
  dt-bindings: clock: imx7ulp: add HSRUN mode related clocks
2018-12-14 14:03:38 -08:00
Anson Huang
7128d7f7ba clk: imx: imx7ulp: add arm hsrun mode clocks support
i.MX7ULP has a Cortex-A7 CPU which can run in RUN mode
or HSRUN mode, it is controlled in SMC1 module. The RUN
mode and HSRUN mode will use different clock source for
ARM, "divcore" for RUN mode and "hsrun_divcore" for HSRUN
mode, so the control bits in SMC1 module can be abstracted
as a HW clock mux, this patch adds HSRUN mode related
clocks in SCG1 module and adds "arm" clock in SMC1 module
to support RUN mode and HSRUN mode switch.

Latest clock tree in RUN mode as below:

 firc                                 0        0        0    48000000          0     0  50000
    firc_bus_clk                      0        0        0    48000000          0     0  50000
    hsrun_scs_sel                     0        0        0    48000000          0     0  50000
       hsrun_divcore                  0        0        0    48000000          0     0  50000

 sosc                                 3        3        3    24000000          0     0  50000
    spll_pre_sel                      1        1        1    24000000          0     0  50000
       spll_pre_div                   1        1        2    24000000          0     0  50000
          spll                        1        1        2   528000000          0     0  50000
             spll_pfd0                1        1        1   500210526          0     0  50000
                spll_pfd_sel          1        1        0   500210526          0     0  50000
                   spll_sel           1        1        0   500210526          0     0  50000
                      scs_sel         1        1        0   500210526          0     0  50000
                         divcore      1        1        0   500210526          0     0  50000
                            arm       1        1        0   500210526          0     0  50000

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 14:03:12 -08:00
Stephen Boyd
2de34ed964 Merge branch 'clk-of' into clk-next
* clk-of:
  clk: Use of_node_name_eq for node name comparisons
2018-12-14 14:02:55 -08:00
Rob Herring
87ab115185 clk: Use of_node_name_eq for node name comparisons
Convert string compares of DT node names to use of_node_name_eq helper
instead. This removes direct access to the node name pointer.

For instances using of_node_cmp, this has the side effect of now using
case sensitive comparisons. This should not matter for any FDT based
system which all of these are.

Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> (clk-mstp)
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> (ux500)
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 13:52:41 -08:00
Stephen Boyd
5964ac6013 Merge branch 'clk-vc5-suspend' into clk-next
- Proper suspend/resume on VersaClock5

* clk-vc5-suspend:
  clk: vc5: Add suspend/resume support
2018-12-14 13:44:19 -08:00
Marek Vasut
8cbdc1f09f clk: vc5: Add suspend/resume support
Add simple suspend/resume handlers to the driver to restore the chip
configuration after resume. It is possible that the chip was configured
with non-default values before suspend-resume cycle and that the chip
is powered down during this cycle, so the configuration could get lost.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-renesas-soc@vger.kernel.org
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 13:43:04 -08:00
Stephen Boyd
9dc3204247 Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: qcom: qcs404: Fix gpll0_out_main parent
  clk: zynqmp: Off by one in zynqmp_is_valid_clock()
  clk: mmp: Off by one in mmp_clk_add()
  clk: mvebu: Off by one bugs in cp110_of_clk_get()
  arm64: dts: qcom: sdm845-mtp: Mark protected gcc clocks
  clk: zynqmp: handle fixed factor param query error
  clk: qcom: gcc: Fix board clock node name
  clk: meson: axg: mark fdiv2 and fdiv3 as critical
  clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL
  clk: fixed-factor: fix of_node_get-put imbalance
2018-12-14 13:42:08 -08:00
Stephen Boyd
44a6951777 Merge branch 'clk-qcom-8998-resets' into clk-next
- Add resets and make Qualcomm MSM8998 GCC driver more functional

* clk-qcom-8998-resets:
  clk: qcom: Drop unused 8998 clock
  clk: qcom: Leave mmss noc on for 8998
  clk: qcom: Add missing msm8998 resets
  clk: qcom: gcc-msm8998: Add clkref clocks
  clk: qcom: gcc-msm8998: Disable halt check of UFS clocks
  clk: qcom: gcc-msm8998: Drop hmss_dvm and lpass_at
  clk: qcom: Enumerate remaining msm8998 resets
  clk: qcom: Add xo dummy clk on msm8998
  clk: qcom: Fix MSM8998 resets
2018-12-14 13:42:00 -08:00
Jeffrey Hugo
0f1c6ca83f clk: qcom: Drop unused 8998 clock
gcc_lpass_trig_clk is not used downstream, therefore there is no reason to
expect it to be needed for clients.  Let's remove it because messing with
the clock has been observed to cause Linux hangs when the qdss_clk is
initialized by rpmcc.

Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Fixes: 4807c71cc6 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 13:41:05 -08:00
Jeffrey Hugo
12eced09cd clk: qcom: Leave mmss noc on for 8998
Similar to other qcom targets, gcc_mmss_noc_cfg_ahb_clk should not be
disabled.  Any mmss access depends on this clock, and its been observed
that enabling mmssnoc_axi_rpm_clk with rpmcc results in an implicit
access to mmss and will crash the system if gcc_mmss_noc_cfg_ahb_clk is
disabled.

Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Fixes: 4807c71cc6 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 13:41:03 -08:00
Stephen Boyd
58c05c823b Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp' and 'clk-imx8mq' into clk-next
- NXP i.MX7ULP SoC clock support
 - Support for i.MX8QXP SoC clocks
 - Support for NXP i.MX8MQ clock controllers

* clk-imx7ulp:
  clk: imx: add imx7ulp clk driver
  clk: imx: implement new clk_hw based APIs
  clk: imx: make mux parent strings const
  dt-bindings: clock: add imx7ulp clock binding doc
  clk: imx: add imx7ulp composite clk support
  clk: imx: add pfdv2 support
  clk: imx: add pllv4 support
  clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
  clk: imx: add gatable clock divider support

* clk-imx6-fixes:
  clk: imx6q: handle ENET PLL bypass
  clk: imx6q: optionally get CCM inputs via standard clock handles
  clk: imx6q: reset exclusive gates on init

* clk-imx-fixes:
  clk: imx6q: add DCICx clocks gate
  clk: imx6sl: ensure MMDC CH0 handshake is bypassed
  clk: imx7d: remove UART1 clock setting

* clk-imx8qxp:
  clk: imx: add imx8qxp lpcg driver
  clk: imx: add lpcg clock support
  clk: imx: add imx8qxp clk driver
  clk: imx: add scu clock common part
  clk: imx: add configuration option for mmio clks
  dt-bindings: clock: add imx8qxp lpcg clock binding
  dt-bindings: clock: imx8qxp: add SCU clock IDs
  firmware: imx: add pm svc headfile
  dt-bindings: fsl: scu: update power domain binding
  firmware: imx: remove resource id enums
  dt-bindings: imx: add scu resource id headfile

* clk-imx8mq:
  clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant
  clk: imx: remove redundant initialization of ret to zero
  clk: imx: Add SCCG PLL type
  clk: imx: Add fractional PLL output clock
  clk: imx: Add clock driver for i.MX8MQ CCM
  clk: imx: Add imx composite clock
  dt-bindings: Add binding for i.MX8MQ CCM
2018-12-14 13:34:47 -08:00
Stephen Boyd
ffe05540d1 Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and 'clk-rockchip' into clk-next
* clk-renesas:
  clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
  clk: renesas: rcar-gen3: Add documentation for SD clocks
  clk: renesas: rcar-gen3: Set state when registering SD clocks
  clk: renesas: r8a77995: Simplify PLL3 multiplier/divider
  clk: renesas: r8a77995: Add missing CPEX clock
  clk: renesas: r8a77995: Remove non-existent SSP clocks
  clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks
  clk: renesas: r8a77995: Correct parent clock of DU
  clk: renesas: r8a77990: Correct parent clock of DU
  clk: renesas: r8a77970: Add CPEX clock
  clk: renesas: r8a77965: Add CPEX clock
  clk: renesas: r8a7796: Add CPEX clock
  clk: renesas: r8a7795: Add CPEX clock
  clk: renesas: r8a774a1: Add CPEX clock
  dt-bindings: clock: r8a7796: Remove CSIREF clock
  dt-bindings: clock: r8a7795: Remove CSIREF clock
  clk: renesas: Mark rza2_cpg_clk_register static
  clk: renesas: r7s9210: Add USB clocks
  clk: renesas: r8a77970: Add RPC clocks
  clk: renesas: r7s9210: Add SDHI clocks

* clk-allwinner:
  clk: sunxi-ng: a64: Allow parent change for VE clock
  clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks
  clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: h3: Allow parent change for ve clock
  clk: sunxi-ng: add support for suniv F1C100s SoC
  dt-bindings: clock: Add Allwinner suniv F1C100s CCU
  clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent
  clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output
  clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
  clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I
  clk: sunxi-ng: Add support for H6 DE3 clocks
  dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description
  clk: sunxi-ng: h6: Set video PLLs limits
  clk: sunxi-ng: Use u64 for calculation of NM rate
  clk: sunxi-ng: Adjust MP clock parent rate when allowed
  clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width
  clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock

* clk-tegra:
  clk: tegra: Return the exact clock rate from clk_round_rate
  clk: tegra30: Use Tegra CPU powergate helper function
  soc/tegra: pmc: Drop SMP dependency from CPU APIs
  clk: tegra: Fix maximum audio sync clock for Tegra124/210
  clk: tegra: get rid of duplicate defines
  clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
  clk: tegra20: Turn EMC clock gate into divider

* clk-meson: (25 commits)
  clk: meson: axg-audio: use the clk input helper function
  clk: meson: add clk-input helper function
  clk: meson: Mark some things static
  clk: meson: meson8b: add the read-only video clock trees
  clk: meson: meson8b: add the fractional divider for vid_pll_dco
  clk: meson: meson8b: fix the offset of vid_pll_dco's N value
  clk: meson: Fix GXL HDMI PLL fractional bits width
  clk: meson: meson8b: add the CPU clock post divider clocks
  clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3
  clk: meson: clk-regmap: add read-only gate ops
  clk: meson: meson8b: allow changing the CPU clock tree
  clk: meson: meson8b: run from the XTAL when changing the CPU frequency
  clk: meson: meson8b: add support for more M/N values in sys_pll
  clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL
  clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel
  clk: meson: clk-pll: check if the clock is already enabled
  clk: meson: meson8b: fix the width of the cpu_scale_div clock
  clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table
  clk: meson: meson8b: use the HHI syscon if available
  dt-bindings: clock: meson8b: use the registers from the HHI syscon
  ...

* clk-rockchip:
  clk: rockchip: add clock-id to gate of ACODEC for rk3328
  clk: rockchip: add clock ID of ACODEC for rk3328
  clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328
  clk: rockchip: fix I2S1 clock gate register for rk3328
  clk: rockchip: make rk3188 hclk_vio_bus critical
  clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering
  clk: rockchip: fix rk3188 sclk_smc gate data
  clk: rockchip: fix typo in rk3188 spdif_frac parent
2018-12-14 13:34:00 -08:00
Stephen Boyd
1a501c8def Merge branches 'clk-managed-registration', 'clk-spdx', 'clk-remove-basic' and 'clk-ops-const' into clk-next
- Make devm_of_clk_add_hw_provider() use parent dt node if necessary
 - Various SPDX taggings
 - Mark clk_ops const when possible

* clk-managed-registration:
  clk: bd718x7: Initial support for ROHM bd71837/bd71847 PMIC clock
  clk: apcs-msm8916: simplify probe cleanup by using devm
  clk: clk-twl6040: Free of_provider at remove
  clk: rk808: use managed version of of_provider registration
  clk: clk-hi655x: Free of_provider at remove
  clk: of-provider: look at parent if registered device has no provider info
  clk: Add kerneldoc to managed of-provider interfaces

* clk-spdx:
  clk: Tag basic clk types with SPDX
  clk: Tag clk core files with SPDX
  clk: bcm2835: Switch to SPDX identifier

* clk-remove-basic:
  clk: Loongson1: Remove usage of CLK_IS_BASIC
  clk: samsung: s3c2410: Remove usage of CLK_IS_BASIC
  clk: versatile: sp810: Remove usage of CLK_IS_BASIC
  clk: hisilicon: Remove usage of CLK_IS_BASIC
  clk: h8300: Remove usage of CLK_IS_BASIC
  clk: axm5516: Remove usage of CLK_IS_BASIC
  clk: st: Remove usage of CLK_IS_BASIC
  clk: renesas: Remove usage of CLK_IS_BASIC

* clk-ops-const:
  clk: s2mps11: constify clk_ops structure
  clk: pxa: constify clk_ops structures
  clk: pistachio: constify clk_ops structures
  clk: palmas: constify clk_ops structure
  clk: max77686: constify clk_ops structure
2018-12-14 13:33:44 -08:00
Robert Yang
08441a9662 clk: tegra: Return the exact clock rate from clk_round_rate
The current behavior is that clk_round_rate would return the same clock
rate passed to it for valid PLL configurations. This change will return
the exact rate the PLL will provide in accordance with clk API.

Signed-off-by: Robert Yang <decatf@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 13:32:55 -08:00
Jon Hunter
b158aeeacc clk: tegra30: Use Tegra CPU powergate helper function
Rather than using the tegra_powergate_is_powered() function for
determining if a CPU is powered, use the tegra_pmc_cpu_is_powered()
instead which was created to get the CPU power status. Internally
tegra_pmc_cpu_is_powered() calls tegra_powergate_is_powered() and so
is equivalent.

The Tegra30 clock driver is the only public user of
tegra_powergate_is_powered() and so by updating the Tegra30 clock
driver to use tegra_pmc_cpu_is_powered(), we can then make
tegra_powergate_is_powered() a non-public function.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 13:32:55 -08:00
Jon Hunter
845d782d91 clk: tegra: Fix maximum audio sync clock for Tegra124/210
The maximum frequency supported for I2S on Tegra124 and Tegra210 is
24.576MHz (as stated in the Tegra TK1 data sheet for Tegra124 and the
Jetson TX1 module data sheet for Tegra210). However, the maximum I2S
frequency is limited to 24MHz because that is the maximum frequency of
the audio sync clock. Increase the maximum audio sync clock frequency
to 24.576MHz for Tegra124 and Tegra210 in order to support 24.576MHz
for I2S.

Update the tegra_clk_register_sync_source() function so that it does
not set the initial rate for the sync clocks and use the clock init
tables to set the initial rate instead.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 13:32:55 -08:00
Marcel Ziswiler
7514557c1c clk: tegra: get rid of duplicate defines
Get rid of 3 duplicate defines.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 13:32:54 -08:00
Stephen Boyd
3315fe5faf Merge branch 'clk-qcom-sdm845-lpass' into clk-next
- Qualcomm SDM845 audio subsystem clks

* clk-qcom-sdm845-lpass:
  clk: qcom: Add lpass clock controller driver for SDM845
  dt-bindings: clock: Introduce QCOM LPASS clock bindings
  dt-bindings: clock: Update GCC bindings for protected-clocks
2018-12-14 13:27:53 -08:00
Stephen Boyd
f4ad7fba06 Merge branches 'clk-qcom-kconfig', 'clk-qcom-gpucc', 'clk-qcom-qcs404-rpm', 'clk-qcom-spi' and 'clk-qcom-videocc-binding' into clk-next
- Qualcomm SDM845 GPU clock controllers
 - Qualcomm QCS404 RPM clk support

* clk-qcom-kconfig:
  clk: qcom: Move to menuconfig and reduce lines

* clk-qcom-gpucc:
  dt-bindings: clock: qcom: Fix the xo parent in gpucc example
  clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6
  clk: qcom: Add a dummy enable function for GX gdsc
  clk: qcom: gdsc: Don't override existing gdsc pd functions
  clk: qcom: Add graphics clock controller driver for SDM845
  dt-bindings: clock: Introduce QCOM Graphics clock bindings

* clk-qcom-qcs404-rpm:
  clk: qcom: smd: Add support for QCS404 rpm clocks

* clk-qcom-spi:
  clk: qcom: msm8916: Additional clock rates for spi

* clk-qcom-videocc-binding:
  dt-bindings: clock: Require #reset-cells in sdm845-videocc
2018-12-14 13:27:11 -08:00
Stephen Boyd
aab184d23b Merge branches 'clk-qoriq-t1023', 'clk-protected-binding', 'clk-define-show-macro' and 'clk-static' into clk-next
- NXP QorIQ T1023 SoC support
 - Introduce a 'protected-clocks' binding for firmware protected clks
 - Shrink code some with DEFINE_SHOW_ATTRIBUTE()

* clk-qoriq-t1023:
  clk: qoriq: add more chips support

* clk-protected-binding:
  clk: qcom: Support 'protected-clocks' property
  dt-bindings: clk: Introduce 'protected-clocks' property

* clk-define-show-macro:
  clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macro
  clk: nomadik: Change to use DEFINE_SHOW_ATTRIBUTE macro

* clk-static:
  clk: stm32mp1: drop pointless static qualifier in stm32_register_hw_clk()
2018-12-14 13:24:54 -08:00
Stephen Boyd
d7d458cb29 Merge branches 'clk-bcm-module-license', 'clk-boston-leak' and 'clk-mtk-mt7629' into clk-next
- Mediatek MT7629 SoC clk controllers

* clk-bcm-module-license:
  clk: bcm2835: make license text and module license match

* clk-boston-leak:
  clk: boston: unregister clks on failure in clk_boston_setup()
  clk: boston: fix possible memory leak in clk_boston_setup()

* clk-mtk-mt7629:
  clk: mediatek: fix the PCIe MAC clock parent
  clk: mediatek: Drop more __init markings for driver probe
  clk: mediatek: Drop __init from mtk_clk_register_cpumuxes()
  dt-bindings: arm: mediatek: document clk bindings for MT7629
  clk: mediatek: add clock support for MT7629 SoC
2018-12-14 13:24:47 -08:00
Aisheng Dong
1e3121bfe5 clk: imx: add imx8qxp lpcg driver
Add imx8qxp lpcg driver support

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 13:01:14 -08:00
Aisheng Dong
2f77296d3d clk: imx: add lpcg clock support
The Low-Power Clock Gate (LPCG) modules contain a local programming
model to control the clock gates for the peripherals. An LPCG module
is used to locally gate the clocks for the associated peripheral.
And they're bedind the SCU clock.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 13:00:51 -08:00
Aisheng Dong
c2cccb6d0b clk: imx: add imx8qxp clk driver
Add imx8qxp clk driver which is based on SCU firmware clock service.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@kernel.org: Move the makefile rule higher in the file]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 13:00:29 -08:00
Abel Vesa
d360b130e2 clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant
Remove the dependency between the i.MX8MQ CCM clock driver
and the CONFIG_SOC_IMX8MQ and use CONFIG_CLK_IMX8MQ instead.
CONFIG_CLK_IMX8MQ depends on ARCH_MXC && ARM64.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14 12:56:27 -08:00
Aisheng Dong
fe37b48204 clk: imx: add scu clock common part
Add SCU clock common part which will be used by client clock drivers.
SCU clocks are totally different from the legacy clocks (No much
legacy things can be reused), it's using a firmware interface now based
on SCU protocol. So a new configuration option CONFIG_MXC_CLK_SCU is added.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@kernel.org: Mark ccm_ipc_handle static]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-13 22:15:49 -08:00
Aisheng Dong
3a48d918a4 clk: imx: add configuration option for mmio clks
The patch introduces CONFIG_MXC_CLK option for legacy MMIO clocks,
this is required to compile legacy MMIO clock conditionally when adding
SCU based clocks for MX8 platforms later.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-13 22:12:46 -08:00
Stephen Boyd
e74581b79d Update for meson clocks targeted at v4.21, round 2:
- Fix GXL HDMI Pll fractional bits (from first round)
 - Add the Meson8/Meson8b video clocks
 - Add clk-input helper and use it for axg-audio clock driver
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Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into clk-meson

Pull more meson clk driver updates from Neil Armstrong:

 - Fix GXL HDMI Pll fractional bits (from first round)
 - Add the Meson8/Meson8b video clocks
 - Add clk-input helper and use it for axg-audio clock driver

* tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson:
  clk: meson: axg-audio: use the clk input helper function
  clk: meson: add clk-input helper function
  clk: meson: meson8b: add the read-only video clock trees
  clk: meson: meson8b: add the fractional divider for vid_pll_dco
  clk: meson: meson8b: fix the offset of vid_pll_dco's N value
  clk: meson: Fix GXL HDMI PLL fractional bits width
2018-12-13 01:05:44 -08:00
Jeffrey Hugo
a1697aba27 clk: qcom: Add missing msm8998 resets
commit c0cb7c7e71 ("clk: qcom: Enumerate remaining msm8998 resets")
missed two USB2 resets.  Add them.

Fixes: c0cb7c7e71 ("clk: qcom: Enumerate remaining msm8998 resets")
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11 13:25:24 -08:00
Stephen Boyd
e1bd55e5a5 clk: Tag basic clk types with SPDX
These are all GPL-2.0 files per the existing license text. Replace the
boiler plate with the tag.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11 09:57:48 -08:00
Stephen Boyd
ebafb63dc7 clk: Tag clk core files with SPDX
These are all GPL-2.0 files per the existing license text. Replace the
boiler plate with the tag.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11 09:57:47 -08:00
Jerome Brunet
f03566d0aa clk: meson: axg-audio: use the clk input helper function
Rework the axg audio clock controller to use the new clk-input helper
function.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: fixed pclk input clock name to axg_audio_pclk]
Link: http://lkml.kernel.org/r/20181204165819.21541-3-jbrunet@baylibre.com
2018-12-11 16:07:03 +01:00
Stephen Boyd
0f51659a43 clk: Loongson1: Remove usage of CLK_IS_BASIC
This flag doesn't look to be used by any code, just set in the clk init
structure and then never tested again. Remove it from this driver as it
doesn't provide any benefit. Also remove parenthesis nearby that are not
needed and include clk.h to fix a sparse warning about static function
definition.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 14:44:08 -08:00
Stephen Boyd
f246affc08 clk: samsung: s3c2410: Remove usage of CLK_IS_BASIC
This flag doesn't look to be used by any code, just set in the clk init
structure and then never tested again. Remove it from this drivers as it
doesn't provide any benefit.

Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 14:44:08 -08:00
Stephen Boyd
354e121006 clk: versatile: sp810: Remove usage of CLK_IS_BASIC
This flag doesn't look to be used by any code, just set in the clk init
structure and then never tested again. Remove it from this driver as it
doesn't provide any benefit.

Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 14:44:05 -08:00
Stephen Boyd
5a727ff630 clk: hisilicon: Remove usage of CLK_IS_BASIC
This flag doesn't look to be used by any code, just set in various clk
init structures and then never tested again. Remove it from these
drivers as it doesn't provide any benefit.

Cc: Jiancheng Xue <xuejiancheng@hisilicon.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Jianguo Sun <sunjianguo1@huawei.com>
Cc: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 14:43:21 -08:00
Stephen Boyd
c0156e5509 clk: h8300: Remove usage of CLK_IS_BASIC
This flag doesn't look to be used by any code, just set in various clk
init structures and then never tested again. Remove it from these
drivers as it doesn't provide any benefit.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 14:43:21 -08:00
Stephen Boyd
2239fe59ac clk: axm5516: Remove usage of CLK_IS_BASIC
This flag doesn't look to be used by any code, just set in various clk
init structures and then never tested again. Remove it from these
drivers as it doesn't provide any benefit.

Cc: Anders Berg <anders.berg@lsi.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 14:43:21 -08:00
Stephen Boyd
c179c21e2c clk: st: Remove usage of CLK_IS_BASIC
This flag doesn't look to be used by any code, just set in various clk
init structures and then never tested again. Remove it from these
drivers as it doesn't provide any benefit.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 14:43:20 -08:00
Stephen Boyd
ddbae6658d clk: renesas: Remove usage of CLK_IS_BASIC
This flag doesn't look to be used by any code, just set in various clk
init structures and then never tested again. Remove it from these
drivers as it doesn't provide any benefit.

Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: <linux-renesas-soc@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 14:43:04 -08:00
Matti Vaittinen
2e62246b08 clk: bd718x7: Initial support for ROHM bd71837/bd71847 PMIC clock
ROHM bd71837 and bd71847 contain 32768Hz clock gate. Support the clock
using generic clock framework. Note, only bd71837 is tested but bd71847
should be identical what comes to clk parts.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 12:44:03 -08:00
Stephen Boyd
f071bcebee clk: qcom: Move to menuconfig and reduce lines
We duplicate the 'depends on' in almost every Kconfig here, and it's
getting out of hand now that we have tens of options for various SoC
drivers here. Let's clean it up a little by making a menuconfig for a
submenu and adding an if wrapper around the driver section.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 11:44:17 -08:00
Lucas Stach
3cc48976e9 clk: imx6q: handle ENET PLL bypass
The ENET PLL is different from the other i.MX6 PLLs, as it has
multiple outputs with different post-dividers, which are all
bypassed if the single bypass bit is activated. The hardware setup
looks something like this:
                                _
refclk-o---PLL---o----DIV1-----| \
       |         |             |M |----OUT1
       o-----------------------|_/
       |         |              _
       |         o----DIV2-----| \
       |         |             |M |----OUT2
       o-----------------------|_/
       |         |              _
       |         `----DIV3-----| \
       |                       |M |----OUT3
       `-----------------------|_/

The bypass bit not only bypasses the PLL, but also the attached
post-dividers. This would be reasonbly straight forward to model
with a single output, or with different bypass bits for each output,
but sadly the HW guys decided that it would be good to actuate all
3 muxes with a single bit.

So the need to have the PLL bypassed for one of the outputs always
affects 2 other (in our model) independent branches of the clock
tree.

This means the decision to bypass this PLL is a system wide design
choice and should not be changed on-the-fly, so we can treat any
bapass configuration as static. As such we can just register the
post-dividiers with a ratio that reflects the bypass status, which
allows us to bypass the PLL without breaking our abstraction model
and with it DT stability.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 11:39:16 -08:00
Lucas Stach
a29be9185d clk: imx6q: optionally get CCM inputs via standard clock handles
When specifying external clock inputs to the CCM the current code
requires the clocks to be in a "clocks" child node of the DT root.
This is not really conformant with DT best practices.

To avoid the need to deviate from those best practices, allow the
clock inputs to be specified via standard clock handles. This is
in line with how drivers of the later CCM driver revisions on
newer i.MX SoCs handle this.

As we can't retroactively change the DT binding, allow this as an
option with a fallback to the old way of how this has been handled.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 11:37:07 -08:00
Lucas Stach
f7542d8177 clk: imx6q: reset exclusive gates on init
The exclusive gates may be set up in the wrong way by software running
before the clock driver comes up. In that case the exclusive setup is
locked in its initial state, as the complementary function can't be
activated without disabling the initial setup first.

To avoid this lock situation, reset the exclusive gates to the off
state and allow the kernel to provide the proper setup.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Dong Aisheng <Aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 11:37:07 -08:00
Anson Huang
929914946f clk: imx6q: add DCICx clocks gate
On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks
gate in CCM_CCGR0 register, add them into clock tree for
clock management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 11:34:50 -08:00
Anson Huang
0efcc2c0fd clk: imx6sl: ensure MMDC CH0 handshake is bypassed
Same as other i.MX6 SoCs, ensure unused MMDC channel's
handshake is bypassed, this is to make sure no request
signal will be generated when periphe_clk_sel is changed
or SRC warm reset is triggered.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 11:34:21 -08:00
Srinivas Kandagatla
8a034aad48 clk: qcom: qcs404: Fix gpll0_out_main parent
gpll0_out_main parent is cxo so fix it.

Fixes: 652f1813c1 ("clk: qcom: gcc: Add global clock controller driver for QCS404")
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 11:31:30 -08:00
Jernej Skrabec
67ee606a6b clk: sunxi-ng: a64: Allow parent change for VE clock
Cedrus driver wants to set VE clock higher than it's possible without
changing parent rate.

Allow changing parent rate for VE clock, so clock rate can be set
freely.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 11:19:26 -08:00
Colin Ian King
33e7a84225 clk: imx: remove redundant initialization of ret to zero
The initialization of ret is redundant as it is being re-assigned to
the return value from the call to imx8m_clk_composite_compute_dividers.
Clean this up by removing the initialization.

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10 09:53:13 -08:00
Stephen Boyd
60baf75e3f clk: renesas: Updates for v4.21 (take two)
- Add support for CPEX (timer) clocks on various R-Car Gen3 and RZ/G2
     SoCs,
   - Add support for SDHI HS400 clocks on early revisions of R-Car H3 and
     M3-W,
   - Miscellaneous fixes based on the Hardware Manual Errata.
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Merge tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for CPEX (timer) clocks on various R-Car Gen3 and RZ/G2 SoCs
 - Add support for SDHI HS400 clocks on early revisions of R-Car H3 and M3-W
 - Miscellaneous fixes based on the Hardware Manual Errata

* tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
  clk: renesas: rcar-gen3: Add documentation for SD clocks
  clk: renesas: rcar-gen3: Set state when registering SD clocks
  clk: renesas: r8a77995: Simplify PLL3 multiplier/divider
  clk: renesas: r8a77995: Add missing CPEX clock
  clk: renesas: r8a77995: Remove non-existent SSP clocks
  clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks
  clk: renesas: r8a77995: Correct parent clock of DU
  clk: renesas: r8a77990: Correct parent clock of DU
  clk: renesas: r8a77970: Add CPEX clock
  clk: renesas: r8a77965: Add CPEX clock
  clk: renesas: r8a7796: Add CPEX clock
  clk: renesas: r8a7795: Add CPEX clock
  clk: renesas: r8a774a1: Add CPEX clock
  dt-bindings: clock: r8a7796: Remove CSIREF clock
  dt-bindings: clock: r8a7795: Remove CSIREF clock
2018-12-07 12:34:11 -08:00
Niklas Söderlund
36c4da4f55 clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400
needs a quirk to function properly. The reason for the quirk is that
there are two settings which produces same divider value for the SDn
clock. On the effected boards the one currently selected results in
HS400 not working.

This change uses the same method as the Gen2 CPG driver and simply
ignores the first clock setting as this is the offending one when
selecting the settings. Which of the two possible settings is used have
no effect for SDR104.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-12-07 11:45:06 +01:00
Niklas Söderlund
e2f4dd1f5b clk: renesas: rcar-gen3: Add documentation for SD clocks
Document the known use cases of the different clock settings. This is
useful as different SoC and ES versions use different settings to do
the same thing as there is more than one combination to achieve the
same SDn clock speed.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-12-07 11:45:03 +01:00
Niklas Söderlund
ecda0a09fa clk: renesas: rcar-gen3: Set state when registering SD clocks
The driver tries to figure out which state a SD clock is in when the
clock is registered, instead of setting a known state. This can be
problematic for two reasons.

1. If the clock driver can't figure out the state of the clock,
   registration of the clock fails, and setting of a known state by a
   clock user is not possible.

2. The state of the clock depends on if and how the bootloader
   configured it. The driver only checks that the rate is known, not if
   the clock is stopped or not for example.

Fix this by setting a known state and making sure the clock is stopped.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-12-07 11:45:00 +01:00
Bjorn Andersson
30bc0b9881 clk: qcom: gcc-msm8998: Add clkref clocks
Add clkref clocks for usb3, hdmi, ufs, pcie, and usb2. They are all
sourced off CXO_IN, so parent them off "xo" until a proper link to the
rpmcc can be described in DT.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 15:57:49 -08:00
Bjorn Andersson
2abf856202 clk: qcom: gcc-msm8998: Disable halt check of UFS clocks
Drop the halt check of the UFS symbol clocks, in accordance with other
platforms. This makes clk_disable_unused() happy and makes it possible
to turn the clocks on again without an error.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 15:57:48 -08:00
Bjorn Andersson
b0d2e8a0cd clk: qcom: gcc-msm8998: Drop hmss_dvm and lpass_at
Disabling gcc_hmss_dvm_bus_clk and gcc_lpass_at_clk causes the board to
lock up, and by that preventing the kernel to boot without
clk_ignore_unused.

gcc_hmss_dvm_bus_clk is marked always-on downstream, but not referenced,
and gcc_lpass_at_clk isn't mentioned. So let's remove them until they
are needed by some client.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 15:57:45 -08:00
Jeffrey Hugo
c0cb7c7e71 clk: qcom: Enumerate remaining msm8998 resets
The current list of defined resets is incomplete compared to what the
hardware implements.  Enumerate the remaining resets according to the
hardware documentation.

Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 15:57:01 -08:00
Stephen Boyd
11832328c5 clk: qcom: Add xo dummy clk on msm8998
We have this dummy factor clk in place to workaround a missing rpm clk
driver that can manage the XO clk state. Add it in to match what we do
on msm8996.

Cc: Jeffrey Hugo <jhugo@codeaurora.org>
Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Tested-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 15:49:43 -08:00
Ryder Lee
d42925189b clk: mediatek: fix the PCIe MAC clock parent
The PCIe function doesn't work as the clock tree of MAC layer is wrong.
Hence fix the clock table.

Fixes: 3b5e748615 ("clk: mediatek: add clock support for MT7629 SoC")
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 12:30:30 -08:00
Matti Vaittinen
7265c3cbbf clk: apcs-msm8916: simplify probe cleanup by using devm
use devm variant for of_provider registration.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
[sboyd@kernel.org: Drop unused parent pointer]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 09:22:33 -08:00
Matti Vaittinen
654dea6ec4 clk: clk-twl6040: Free of_provider at remove
use devm variant for of_provider registration so provider is freed
at exit.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 09:20:43 -08:00
Matti Vaittinen
252246674f clk: rk808: use managed version of of_provider registration
Simplify clean-up for rk808 by using managed version of of_provider
registration.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 09:20:35 -08:00
Matti Vaittinen
1efadbf2fd clk: clk-hi655x: Free of_provider at remove
use devm variant for of_provider registration so provider is freed
at exit.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 09:20:29 -08:00
Matti Vaittinen
05502bf9eb clk: of-provider: look at parent if registered device has no provider info
It seems to be usual for MFD devices that the created 'clock sub-device'
do not have own DT node. The clock provider information is usually in the
main device node which is owned by the MFD device. Change the devm variant
of clk of-provider registration to check the parent device node if given
device has no own node or if the node does not contain the #clock-cells
property. In such case use the parent node if it contains the #clock-cells.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
[sboyd@kernel.org: Add some comment in the code and pull out logic into
a single function to return the provider device_node pointer]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 09:18:33 -08:00
Chen-Yu Tsai
6e6da2039c
clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks
All the audio interfaces on Allwinner SoCs need to change their module
clocks during operation, to switch between support for 44.1 kHz and 48
kHz family sample rates. The clock rate for the module clocks is
governed by their upstream audio PLL. The module clocks themselves only
have a gate, and sometimes a divider or mux. Thus any rate changes need
to be propagated upstream.

Set the CLK_SET_RATE_PARENT flag for all audio module clocks to achieve
this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05 12:08:20 +01:00
Chen-Yu Tsai
37bb18398a
clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL
The audio blocks require specific clock rates. Until now we were using
the closest clock rate possible with integer N-M factors. This resulted
in audio playback being slightly slower than it should be.

The vendor kernel gets around this (for newer SoCs) by using sigma-delta
modulation to generate a fractional-N factor. As the PLL hardware is
identical in most chips, we can back port the settings from the newer
SoC, in this case the H3, onto the A33.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-05 12:08:17 +01:00
Jerome Brunet
e456e6a12b clk: meson: add clk-input helper function
Add the clock input helper function. Several amlogic clock controllers
will now be registering bypass clock input. Instead of copying this
code in every of them, let's make an helper function for it

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: fixed up to apply on Makefile and clkc.h]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181204165819.21541-2-jbrunet@baylibre.com
2018-12-05 11:24:40 +01:00
Matti Vaittinen
e45838b52c clk: Add kerneldoc to managed of-provider interfaces
Document the devm_of_clk_del_provider and the
devm_of_clk_add_hw_provider functions.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
[sboyd@kernel.org: Comply with kernel-doc formatting]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04 11:41:41 -08:00
Geert Uytterhoeven
c0f8584f05 clk: renesas: r8a77995: Simplify PLL3 multiplier/divider
116/6 can be simplified to 58/3.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04 10:30:16 +01:00
Geert Uytterhoeven
6155bfa32c clk: renesas: r8a77995: Add missing CPEX clock
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) added
the CPEX clock on R-Car D3.  This clock can be selected as a clock
source for CMT1 (Compare Match Timer Type 1).

Add the missing clock to the DT bindings header, and implement support
for it in the clock driver.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04 10:30:05 +01:00
Geert Uytterhoeven
846dbb405b clk: renesas: r8a77995: Remove non-existent SSP clocks
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Dec 22, 2017, and
Feb 28, 2018) removed the SSPSRC, SSP1, and SSP2 clocks on R-Car D3, as
this SoC does not have a Stream and Security Processor.

As these definitions were never used, they can just be removed.
The freed slots in the DT bindings header must not be reused, though.

Fixes: 714c53aa2e ("clk: renesas: Add r8a77995 CPG Core Clock Definitions")
Fixes: d71e851d82 ("clk: renesas: cpg-mssr: Add R8A77995 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04 10:30:02 +01:00
Geert Uytterhoeven
a5883a387f clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks
R-Car Gen3 Hardware Manual Errata for Rev 0.80 of February 28, 2018,
removed the module clocks for the Video Input Module (VIN) channels 5-7
on R-Car D3, as they do not exist on this SoC.

Fixes: d71e851d82 ("clk: renesas: cpg-mssr: Add R8A77995 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04 10:29:59 +01:00
Geert Uytterhoeven
515b2915ee clk: renesas: r8a77995: Correct parent clock of DU
According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car D3 is S1D1.

Fixes: d71e851d82 ("clk: renesas: cpg-mssr: Add R8A77995 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2018-12-04 10:29:57 +01:00
Takeshi Kihara
7cf3a216a2 clk: renesas: r8a77990: Correct parent clock of DU
According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car E3 is S1D1.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 3570a2af47 ("clk: renesas: cpg-mssr: Add support for R-Car E3")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2018-12-04 10:29:51 +01:00
Geert Uytterhoeven
396bc9d40d clk: renesas: r8a77970: Add CPEX clock
Implement support for the CPEX clock on R-Car V3M.  This clock can be
selected as a clock source for CMT1 (Compare Match Timer Type 1).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04 10:29:48 +01:00
Geert Uytterhoeven
f70f4be733 clk: renesas: r8a77965: Add CPEX clock
Implement support for the CPEX clock on R-Car M3-N.  This clock can be
selected as a clock source for CMT1 (Compare Match Timer Type 1).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04 10:29:46 +01:00
Geert Uytterhoeven
f51389cb6a clk: renesas: r8a7796: Add CPEX clock
Implement support for the CPEX clock on R-Car M3-W.  This clock can be
selected as a clock source for CMT1 (Compare Match Timer Type 1).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04 10:29:43 +01:00
Geert Uytterhoeven
b9c0ba6614 clk: renesas: r8a7795: Add CPEX clock
Implement support for the CPEX clock on R-Car H3.  This clock can be
selected as a clock source for CMT1 (Compare Match Timer Type 1).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04 10:29:41 +01:00
Geert Uytterhoeven
f845b01d47 clk: renesas: r8a774a1: Add CPEX clock
Implement support for the CPEX clock on RZ/G2M.  This clock can be
selected as a clock source for CMT1 (Compare Match Timer Type 1).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
2018-12-04 10:29:37 +01:00
Jernej Skrabec
64f28430cf
clk: sunxi-ng: h3: Allow parent change for ve clock
Cedrus driver wants to set VE clock higher than it's possible without
changing parent rate.

In order to correct that, allow changing parent rate for VE clock.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-04 08:43:58 +01:00
Mesih Kilinc
0380126eb9
clk: sunxi-ng: add support for suniv F1C100s SoC
The suniv F1C100s SoC (the chip in some new F-series products of
Allwinner)
has a CCU which seems to be a stripped version of the CCU in SoCs after
sun6i.

Add support for the CCU.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-04 08:41:13 +01:00
Stephen Boyd
8913e8a73d clk: meson: Mark some things static
These are missing 'static' so sparse complains:

drivers/clk/meson/vid-pll-div.c:58:26: warning: symbol '_get_table_val' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:1585:12: warning: symbol 'gxbb_vid_pll_parent_names' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:1620:12: warning: symbol 'gxbb_vclk_parent_names' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:1980:12: warning: symbol 'gxbb_cts_parent_names' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:2036:12: warning: symbol 'gxbb_cts_hdmi_tx_parent_names' was not declared. Should it be static?

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 13:52:56 -08:00
A.s. Dong
b1260067ac clk: imx: add imx7ulp clk driver
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks

The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.

M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.

This driver only adds clock support in A7 domain.

Note that most clocks required to be operated when gated, e.g. pll,
pfd, pcc. And more special cases that scs/ddr/nic mux selecting
different clock source requires that clock to be enabled first,
then we need set CLK_OPS_PARENT_ENABLE flag for them properly.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 11:31:36 -08:00
A.s. Dong
3b315214e0 clk: imx: implement new clk_hw based APIs
Clock providers are recommended to use the new struct clk_hw based API,
so implement IMX clk_hw based provider helpers functions to the new
approach.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 11:31:36 -08:00
A.s. Dong
9e5ef7a57c clk: imx: make mux parent strings const
As the commit 2893c37946 ("clk: make strings in parent name arrays
const"), let's make the parent strings const, otherwise we may meet
the following warning when compiling:

drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init':
drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing argument 5 of
	'imx_clk_mux_flags' discards 'const' qualifier from pointer target type

  clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_mux_flags("apll_pre_sel", base + 0x508, 0,
	1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
                                   ^
In file included from drivers/clk/imx/clk-imx7ulp.c:23:0:
drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is
 of type 'const char * const*'
...

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 11:31:36 -08:00
A.s. Dong
76a323c19a clk: imx: add imx7ulp composite clk support
The imx composite clk is designed for Peripheral Clock Control (PCC)
module observed in IMX ULP SoC series.

NOTE pcc can only be operated when clk is gated.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@kernel.org: Include clk.h for sparse warnings]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 11:31:36 -08:00
A.s. Dong
9fcb6be3b6 clk: imx: add pfdv2 support
The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.

NOTE pfdv2 can only be operated when clk is gated.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@kernel.org: Include clk.h for sparse warnings]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 11:31:32 -08:00
A.s. Dong
d9a8f950b2 clk: imx: add pllv4 support
pllv4 is designed for System Clock Generation (SCG) module observed
in IMX ULP SoC series. e.g. i.MX7ULP.

The SCG modules generates clock used to derive processor, system,
peripheral bus and external memory interface clocks while this patch
intends to support the PLL part.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@kernel.org: Include clk.h for sparse warnings]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 11:31:28 -08:00
A.s. Dong
e983da27f7 clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.

This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 11:31:24 -08:00
A.s. Dong
4046807942 clk: imx: add gatable clock divider support
For dividers with zero indicating clock is disabled, instead of giving a
warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
set" in exist code, we'd like to introduce enable/disable function for it.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...

Set rate when the clk is disabled will cache the rate request and only
when the clk is enabled will the driver actually program the hardware to
have the requested divider value. Similarly, when the clk is disabled we'll
write a 0 there, but when the clk is enabled we'll restore whatever rate
(divider) was chosen last.

It does mean that recalc rate will be sort of odd, because when the clk is
off it will return 0, and when the clk is on it will return the right rate.
So to make things work, we'll need to return the cached rate in recalc rate
when the clk is off and read the hardware when the clk is on.

NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@kernel.org: Include clk.h for sparse warnings]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 11:31:23 -08:00
Lucas Stach
ff70fbd0e8 clk: imx: Add SCCG PLL type
The SCCG is a new PLL type introduced on i.MX8.

The description of this SCCG clock can be found here:

https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 10:13:35 -08:00
Lucas Stach
6209624b9a clk: imx: Add fractional PLL output clock
This is a new fractional clock type introduced on i.MX8.

The description of this fractional clock can be found here:

https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 10:13:34 -08:00
Abel Vesa
b80522040c clk: imx: Add clock driver for i.MX8MQ CCM
Add driver for the Clock Control Module found on i.MX8MQ.

Signed-off-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 10:12:50 -08:00
Abel Vesa
d3ff972813 clk: imx: Add imx composite clock
Since a lot of clocks on imx8m are formed by a mux, gate, predivider and
divider, the idea here is to combine all of those into one composite clock,
but we need to deal with both predivider and divider at the same time and
therefore we add the imx8m_clk_composite_divider_ops and register
the composite clock with those.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Suggested-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 10:12:50 -08:00
Jeffrey Hugo
4f89f7b59a clk: qcom: Fix MSM8998 resets
The offsets for the defined BCR reset registers does not match the hardware
documentation.  Update the values to match the hardware documentation.

Fixes: b5f5f525c5 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 09:57:28 -08:00
Dan Carpenter
9a43be9ced clk: zynqmp: Off by one in zynqmp_is_valid_clock()
The > comparison should be >= to prevent reading beyond the end of the
clock[] array.

(The clock[] array is allocated in zynqmp_clk_setup() and has
clock_max_idx elements.)

Fixes: 3fde0e16d0 ("drivers: clk: Add ZynqMP clock driver")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 09:54:48 -08:00
Dan Carpenter
2e85c57493 clk: mmp: Off by one in mmp_clk_add()
The > comparison should be >= or we write one element beyond the end of
the unit->clk_table[] array.

(The unit->clk_table[] array is allocated in the mmp_clk_init() function
and it has unit->nr_clks elements).

Fixes: 4661fda10f ("clk: mmp: add basic support functions for DT support")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 09:54:48 -08:00
Dan Carpenter
d9f5b7f5dd clk: mvebu: Off by one bugs in cp110_of_clk_get()
These > comparisons should be >= to prevent reading beyond the end of
of the clk_data->hws[] buffer.

The clk_data->hws[] array is allocated in cp110_syscon_common_probe()
when we do:
	cp110_clk_data = devm_kzalloc(dev, sizeof(*cp110_clk_data) +
				      sizeof(struct clk_hw *) * CP110_CLK_NUM,
				      GFP_KERNEL);
As you can see, it has CP110_CLK_NUM elements which is equivalent to
CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS.

Fixes: d3da3eaef7 ("clk: mvebu: new driver for Armada CP110 system controller")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 09:54:48 -08:00
Taniya Das
8d3e5b9c1f clk: qcom: Add lpass clock controller driver for SDM845
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
LPASS clocks present on the global clock controller would be registered
with the clock framework based on the protected-clock flag. Also do not
gate these clocks if they are left unused, as the lpass clocks require
the global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03 09:38:05 -08:00
Chen-Yu Tsai
7bb7d29cff clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent
The third parent of CSI_MCLK is PLL_PERIPH1, not PLL_PERIPH0.
Fix it.

Fixes: 0577e4853b ("clk: sunxi-ng: Add H3 clocks")
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-12-03 23:54:07 +08:00
Martin Blumenstingl
6cb57c678b clk: meson: meson8b: add the read-only video clock trees
Add all clocks to give us the final video clocks within the Meson8,
Meson8b and Meson8m2 SoCs. The final video clocks are:
- cts_enct
- cts_encl
- cts_encp
- cts_enci
- cts_vdac0
- hdmi_tx_pixel
- hdmi_sys

Add multiple clocks in between which are needed to implement these
clocks:
- Opposed to GXBB there is no pre-multiplier for the PLL input. The
  assumption here is that the multiplier is required to achieve the HDMI
  2.0 clock rates (which are up to twice the rate of the HDMI 1.4
  rates).
- The main PLL is called "HDMI PLL" or "HPLL" in the datasheet. Rename
  our existing "vid_pll_dco" to "hdmi_pll_dco". The actual VID_PLL clock
  also exists further down the tree.
- Rename the existing "vid_pll" clock (which is the OD divider at
  HHI_VID_PLL_CNTL[17:16]) to "hdmi_pll_lvds_out" to match the naming
  from the datasheet.
- Add the second OD divider called "hdmi_pll_hdmi_out" at
  HHI_VID_PLL_CNTL[19:18].
- Add the "vid_pll_in_sel" which can choose between "hdmi_pll_dco" and
  another parent. However, the second parent is not use on Amlogic's
  3.10 kernel for HDMI or CVBS output so just leave a TODO in the code.
- Add the "vid_pll_in_en" which is located after "vid_pll_in_sel"
  according to the datasheet.
- Add "vid_pll_pre_div" which is used for divide-by-5 and divide-by-6 in
  Amlogic's 3.10 kernel sources.
- Add "vid_pll_post_div" which divides the output of "vid_pll_pre_div"
  further down. The Amlogic 3.10 kernel configures this as divide-by-2
  with "vid_pll_pre_div" being configured as divide-by-5 to achieve a
  total divider of 10.
- Add the real "vid_pll" clock which selects between "vid_pll_pre_div",
  "vid_pll_post_div" and a third "vid_pll_pre_div_mult7_div2" (which is
  "vid_pll_pre_div" divided by 3.5). The latter is not supported yet
  because it's not used in Amlogic's 3.10 kernel. The "vid_pll" clock
  rate can also be measured by clkmsr to check whether this
  implementation is correct.
- Add "vid_pll_final_div" which is a post-divider for "vid_pll" and it's
  used as input for "vclk" and "vclk2"
- Add the two symmetric "vclk" and "vclk" clock trees, each with a
  divide-by-1, divide-by-2, divide-by-4, divide-by-6 and divide-by-12
  clock and a divider for each clock.
- Add the "cts_enct", "cts_encp" and "hdmi_tx_pixel" clocks which each
  have their own gate and can select between any of the five "vclk"
  dividers.
- Add the "cts_encl" and "cts_vdac0" clocks which each have their own
  gate and can select between any of the five "vclk2" dividers.

The "hdmi_sys" clock is a different than these video clocks. It takes
"xtal" as input (there are three more but unknown parents). Add this
clock as well as it's used by the HDMI controller. Amlogic's 3.10 kernel
always configures this as "xtal divided by 1", so we can ignore the
other parents for now.

This was tested on Meson8b and Meson8m2 boards by comparing the common
clock framework output with the clock measurer output. The following
video modes were first set in u-boot (by running "video dev open $mode")
before booting Linux:
4K2K30HZ (only supported by Meson8m2, not tested on Meson8b):
- vid_pll: 297000000Hz
- cts_encp: 297000000Hz
- hdmi_tx_pixel: 297000000Hz
1080P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 148500000Hz
720P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 74250000Hz
480P:
- vid_pll: 216000000Hz
- cts_encp: 54000000Hz
- hdmi_tx_pixel: 27000000Hz

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-4-martin.blumenstingl@googlemail.com
2018-12-03 11:50:06 +01:00
Martin Blumenstingl
007f3da7d3 clk: meson: meson8b: add the fractional divider for vid_pll_dco
This "vid_pll_dco" (which should be named HDMI_PLL or - as the datasheet
calls it - HPLL) has a 12-bit wide fractional parameter at
HHI_VID_PLL_CNTL2[11:0]. Add this so we correctly calculate the rate of
this PLL when u-boot is configured for a video mode which uses this
fractional parameter.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-3-martin.blumenstingl@googlemail.com
2018-12-03 11:49:51 +01:00
Martin Blumenstingl
376d8c45bd clk: meson: meson8b: fix the offset of vid_pll_dco's N value
Unlike the other PLLs on Meson8b the N value "vid_pll_dco" (a better
name would be hdmi_pll_dco or - as the datasheet calls it - HPLL) is
located at HHI_VID_PLL_CNTL[14:10] instead of [13:9].
This results in an incorrect calculation of the rate of this PLL because
the value seen by the kernel is double the actual N (divider) value.
Update the offset of the N value to fix the calculation of the PLL rate.

Fixes: 28b9fcd016 ("clk: meson8b: Add support for Meson8b clocks")
Reported-by: Jianxin Pan <jianxin.pan@amlogic.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-2-martin.blumenstingl@googlemail.com
2018-12-03 11:49:13 +01:00