Some drivers use disable_irq / enable_irq and do the work
clearing the source in another thread instead of using a threaded
interrupt handler.
The irqchip used not having irq_disable and irq_enable
callbacks in this case, will lead to unnecessary spurious
interrupts:
On a disable_irq in a chip without a handler for this, the irq
core will remember the disable, but not actually call into the
irqchip. With a level triggered interrupt (where the source has
not been cleared) this will lead to an immediate retrigger, at
which point the irq-core will mask the irq. So having an
irq_disable callback in the irqchip will save us the interrupt
firing a 2nd time for nothing.
Drivers using disable / enable_irq like this, will call
enable_irq when they finally have cleared the interrupt source,
without an enable_irq callback, this will turn into an unmask,
at which point the irq will trigger immediately because when it
was originally acked the level was still high, so the ack was
a nop.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
For level triggered gpio interrupts we need to use handle_fasteoi_irq,
like we do with the irq-sunxi-nmi driver. This is necessary to give threaded
interrupt handlers a chance to actuall clear the source of the interrupt
(which may involve sleeping waiting for i2c / spi / mmc transfers), before
acknowledging the interrupt.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
With level triggered interrupt mask / unmask will get called for each
interrupt, doing the somewhat expensive mux setting on each unmask thus is
not a good idea. Instead add a request_resources callback and do it there.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The sunxi pinctrl irq chip driver does not support wakeup at the
moment. Adding IRQCHIP_SKIP_SET_WAKE lets the irqs work with drivers
using wakeup.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The A23 and A31 support multiple interrupt banks. Support it by adding a linear
domain covering all the banks. It's trickier than it should because there's an
interrupt per bank, so we have multiple interrupts using the same domain.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If irq_mask_ack is not defined, mask_ack_irq will call irq_mask and then
irq_ack. In order to avoid code duplication, between irq_mask_ack and irq_mask,
just declare irq_ack.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The irq/pin mapping is used to lookup the pin to mux to the irq
function when the irq is enabled. It is created when gpio_to_irq
is called. Creating the mapping during init allows us to map the
interrupts directly from the device tree.
Originally the IRQ to pin mapping was created when gpio_to_irq
was called with a GPIO handle. The mapping in turn is used to mux
the pin into EINT mode.
If the mapping is created during gpio_to_irq, we can't use the
interrupts directly, i.e. through the DT with "interrupts = <&pio A 4>".
Instead we'd have to use "gpios = <&pio A B>", then pass the gpio
through to gpio_to_irq.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pin numbers passed to sunxi_*_reg helpers to get the correct
registers should be the pin offset for the PIO block, not the
absolute number we use that is based on the alphanumeric labels
Allwinner uses.
This patch subtracts .pin_base from the pin number passed to these
functions, so the driver accesses the correct registers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When the support for the PRCM muxer on the A31 has been added, the global
static pinctl_desc definition has been left as is. Unfortunately, this
structure is used to register the pinctrl device, and prior to this
registration, we set the name and pins field.
Since this structure is shared across instances, that means that the latest
registered pinctrl device wins in setting the name, pins and pins numbers,
which is not really a good thing.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The way that reset is handled right now is that it is made optional for every
pinctrl driver, while actually, it isn't used at all for the main pin
controllers so far, and while it's mandatory for the A31's secondary pin
controller.
Move the reset functions out of the core and in the driver, where they can be
made mandatory.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Move the pin description to a driver specific to be.
This is the final step toward retiring pinctrl-sunxi-pins.h that used to define
all the pins for all the Allwinner SoCs in a single header, that would have in
turn result in having these structures in the final binary as many times as the
header was included.
We can finally remove that header, and remove all the driver part of the
pinctrl-sunxi core.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This will allow to have multiple drivers using the same core code, and
eventually, retire pinctrl-sunxi-pins.h
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The previous code was calling of_iomap, which doesn't do any resource
management, and doesn't call request_mem_region either. Use
devm_ioremap_resource that do both.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
