The congestion_count was introduced into the struct cgroup by
commit d09d8df3a2 ("blkcg: add generic throttling mechanism"),
but since it is closely related to the blkio subsys, it is not
appropriate to put it in the struct cgroup, so let's move it to
struct blkcg. There should be no functional changes because blkcg
is per cgroup.
Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com>
Acked-by: Tejun Heo <tj@kernel.org>
Link: https://lore.kernel.org/r/20240716133058.3491350-1-xiujianfeng@huawei.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Configuration for sbq:
depth=64, wake_batch=6, shift=6, map_nr=1
1. There are 64 requests in progress:
map->word = 0xFFFFFFFFFFFFFFFF
2. After all the 64 requests complete, and no more requests come:
map->word = 0xFFFFFFFFFFFFFFFF, map->cleared = 0xFFFFFFFFFFFFFFFF
3. Now two tasks try to allocate requests:
T1: T2:
__blk_mq_get_tag .
__sbitmap_queue_get .
sbitmap_get .
sbitmap_find_bit .
sbitmap_find_bit_in_word .
__sbitmap_get_word -> nr=-1 __blk_mq_get_tag
sbitmap_deferred_clear __sbitmap_queue_get
/* map->cleared=0xFFFFFFFFFFFFFFFF */ sbitmap_find_bit
if (!READ_ONCE(map->cleared)) sbitmap_find_bit_in_word
return false; __sbitmap_get_word -> nr=-1
mask = xchg(&map->cleared, 0) sbitmap_deferred_clear
atomic_long_andnot() /* map->cleared=0 */
if (!(map->cleared))
return false;
/*
* map->cleared is cleared by T1
* T2 fail to acquire the tag
*/
4. T2 is the sole tag waiter. When T1 puts the tag, T2 cannot be woken
up due to the wake_batch being set at 6. If no more requests come, T1
will wait here indefinitely.
This patch achieves two purposes:
1. Check on ->cleared and update on both ->cleared and ->word need to
be done atomically, and using spinlock could be the simplest solution.
2. Add extra check in sbitmap_deferred_clear(), to identify whether
->word has free bits.
Fixes: ea86ea2cdc ("sbitmap: ammortize cost of clearing bits")
Signed-off-by: Yang Yang <yang.yang@vivo.com>
Reviewed-by: Ming Lei <ming.lei@redhat.com>
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Link: https://lore.kernel.org/r/20240716082644.659566-1-yang.yang@vivo.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
This patch adds a poll queue check, aiming to help users use polled IO
accurately.
If users do polled IO but the device doesn't have poll queues, they will
get suboptimal performance data and waste CPU resources. Add a poll queue
check batching this. If users don't have the device properly configured,
or if it simply doesn't support polled IO, it will error the IO with
-EOPNOTSUPP. This is similar to what we used to do for sync polled IO,
which is no longer supported.
Signed-off-by: hexue <xue01.he@samsung.com>
Link: https://lore.kernel.org/r/20240718070817.1031494-1-xue01.he@samsung.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Add a BUILD_BUG_ON() call to ensure that we are not missing entries in
rqf_name[].
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: John Garry <john.g.garry@oracle.com>
Link: https://lore.kernel.org/r/20240719112912.3830443-16-john.g.garry@oracle.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Now that we have a bit index for RQF_x in __RQF_x, use __RQF_x to simplify
the definition of RQF_NAME() by not using ilog2((__force u32()).
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: John Garry <john.g.garry@oracle.com>
Link: https://lore.kernel.org/r/20240719112912.3830443-15-john.g.garry@oracle.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Similar to what we do for enum req_flag_bits, divide the definition of
RQF_x flags into an enum to declare the bits and an actual flag.
Tweak some comments to not spill onto new lines.
Signed-off-by: John Garry <john.g.garry@oracle.com>
Link: https://lore.kernel.org/r/20240719112912.3830443-14-john.g.garry@oracle.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Add a BUILD_BUG_ON() call to ensure that we are not missing entries in
cmd_flag_name[].
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: John Garry <john.g.garry@oracle.com>
Link: https://lore.kernel.org/r/20240719112912.3830443-13-john.g.garry@oracle.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Make BLK_TAG_ALLOC_x an enum and add a "max" entry.
Add a BUILD_BUG_ON() call to ensure that we are not missing entries in
hctx_flag_name[].
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: John Garry <john.g.garry@oracle.com>
Link: https://lore.kernel.org/r/20240719112912.3830443-12-john.g.garry@oracle.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Refresh values in BLK_MQ_F_x enum, and then re-arrange members in
hctx_flag_name[] to match that enum. Renumber
BLK_MQ_F_ALLOC_POLICY_START_BIT to match the value refresh.
Add a BUILD_BUG_ON() call to ensure that we are not missing entries in
hctx_flag_name[].
Signed-off-by: John Garry <john.g.garry@oracle.com>
Link: https://lore.kernel.org/r/20240719112912.3830443-11-john.g.garry@oracle.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Add a build-time assert that we are not missing entries from
hctx_state_name[]. For this, create a separate enum for state flags and add
a "max" entry for BLK_MQ_S_x flags.
The numbering for those enum values is as default, so don't explicitly
number.
Signed-off-by: John Garry <john.g.garry@oracle.com>
Link: https://lore.kernel.org/r/20240719112912.3830443-10-john.g.garry@oracle.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Assert that we are not missing flag entries in blk_queue_flag_name[].
Signed-off-by: John Garry <john.g.garry@oracle.com>
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Link: https://lore.kernel.org/r/20240719112912.3830443-9-john.g.garry@oracle.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
BLK_MQ_MAX_DEPTH is defined as an enumerated value, but has no real
relation to the other members in its enum, so just use #define to provide
the definition.
Signed-off-by: John Garry <john.g.garry@oracle.com>
Link: https://lore.kernel.org/r/20240719112912.3830443-7-john.g.garry@oracle.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Currently the BTRFS_MOUNT_* flags are already beyond 32 bits, this is
going to cause compilation errors for some 32 bit systems, as their
unsigned long is only 32 bits long, thus flag
BTRFS_MOUNT_IGNORESUPERFLAGS overflows and can lead to errors.
Fix the problem by:
- Migrate all existing BTRFS_MOUNT_* flags to unsigned long long
- Migrate all mount option related variables to unsigned long long
* btrfs_fs_info::mount_opt
* btrfs_fs_context::mount_opt
* mount_opt parameter of btrfs_check_options()
* old_opts parameter of btrfs_remount_begin()
* old_opts parameter of btrfs_remount_cleanup()
* mount_opt parameter of btrfs_check_mountopts_zoned()
* mount_opt and opt parameters of check_ro_option()
Fixes: 32e6216512 ("btrfs: introduce new "rescue=ignoresuperflags" mount option")
Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
- Remove unused struct 'acpi_handle_node' (Dr. David Alan Gilbert)
- Use array notation for portdrv .id_table consistently (Masahiro Yamada)
- Switch to new Intel CPU model defines (Tony Luck)
- Add missing MODULE_DESCRIPTION() macros (Jeff Johnson)
* pci/misc:
PCI: controller: Add missing MODULE_DESCRIPTION() macros
PCI: Add missing MODULE_DESCRIPTION() macros
PCI/PM: Switch to new Intel CPU model defines
PCI: Use array for .id_table consistently
ACPI: PCI: Remove unused struct 'acpi_handle_node'
- Create "domain" symlink for vmd before adding devices below the VMD
bridge so it's available when mdadm assembles RAID devices from them
(Jiwei Sun)
* pci/controller/vmd:
PCI: vmd: Create domain symlink before pci_bus_add_devices()
- Ensure Tegra194 and Tegra234 inbound ATU entries are 64KB-aligned to
match the hardware restriction (Jon Hunter)
- Remove unused struct 'tegra_pcie_soc' (Dr. David Alan Gilbert)
* pci/controller/tegra194:
PCI: tegra: Remove unused struct 'tegra_pcie_soc'
PCI: tegra194: Set EP alignment restriction for inbound ATU
- Use dev_err_probe() in dw-rockchip probe error path so the failures
aren't silent (Uwe Kleine-König)
- Sleep PCIE_T_PVPERL_MS (100ms) before deasserting PERST# (Damien Le Moal)
- Sleep PCIE_T_RRS_READY_MS (100ms) after conventional reset, before a
config access (Damien Le Moal)
- Request the PERST# GPIO with GPIOD_OUT_LOW so it matches the POR value,
which avoids a spurious PERST# assertion and fixes a Qcom modem firmware
crash and issues with WLAN controllers, e.g., RTL8822CE (Manivannan
Sadhasivam for rockchip, Niklas Cassel for dw-rockchip)
- Refactor dw-rockchip and add support for Endpoint mode for rk3568 and
rk3588 (Niklas Cassel)
* pci/controller/rockchip:
PCI: dw-rockchip: Use pci_epc_init_notify() directly
PCI: dw-rockchip: Add endpoint mode support
PCI: dw-rockchip: Refactor the driver to prepare for EP mode
PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
PCI: dw-rockchip: Fix weird indentation
PCI: dw-rockchip: Fix initial PERST# GPIO value
PCI: dw-rockchip: Add error messages in .probe() error paths
PCI: rockchip: Use GPIOD_OUT_LOW flag while requesting ep_gpio
PCI: rockchip-host: Wait 100ms after reset before starting configuration
PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling
- Add Synopsys DWC macros for lane skew configuration (Yoshihiro Shimoda)
- Add struct rcar_gen4_pcie_drvdata to provide for future SoCs with
different initialization requirements (Yoshihiro Shimoda)
- Add .ltssm_control() method for SoC dependencies (Yoshihiro Shimoda)
- Add r8a779g0 (R-Car V4H) support (Yoshihiro Shimoda)
* pci/controller/rcar-gen4:
PCI: rcar-gen4: Add support for R-Car V4H
PCI: rcar-gen4: Add .ltssm_control() for other SoC support
PCI: rcar-gen4: Add struct rcar_gen4_pcie_drvdata
PCI: dwc: Add PCIE_PORT_{FORCE,LANE_SKEW} macros
- Demote WARN() to dev_warn_ratelimited() in rcar_pcie_wakeup() to avoid
excessive warnings when the driver is confused about link state when
resuming (Marek Vasut)
* pci/controller/rcar:
PCI: rcar: Demote WARN() to dev_warn_ratelimited() in rcar_pcie_wakeup()
- Use devm_clk_bulk_get_all() to get all the clocks from DT to avoid
writing out all the clock names (Manivannan Sadhasivam)
- Add DT binding and driver support for the SA8775P SoC (Mrinmay Sarkar)
- Refactor dw_pcie_edma_find_chip() to enable adding support for Hyper DMA
(HDMA) (Manivannan Sadhasivam)
- Enable drivers to supply the eDMA channel count since some can't auto
detect this (Manivannan Sadhasivam)
- Add HDMA support for the SA8775P SoC (Mrinmay Sarkar)
- Override the SA8775P NO_SNOOP default to avoid possible memory corruption
(Mrinmay Sarkar)
- Make sure resources are disabled during PERST# assertion, even if the
link is already disabled (Manivannan Sadhasivam)
- Vote for the CPU-PCIe ICC (interconnect) path to ensure it stays active
even if other drivers don't vote for it (Krishna chaitanya chundru)
- Add Operating Performance Points (OPP) to scale performance state based
on aggregate link bandwidth to improve SoC power efficiency (Krishna
chaitanya chundru)
- Return failure instead of success if dev_pm_opp_find_freq_floor() fails
(Dan Carpenter)
- Avoid an error pointer dereference if dev_pm_opp_find_freq_exact() fails
(Dan Carpenter)
- Prevent use of uninitialized data in qcom_pcie_suspend_noirq() (Dan
Carpenter)
* pci/controller/qcom:
PCI: qcom: Prevent use of uninitialized data in qcom_pcie_suspend_noirq()
PCI: qcom: Prevent potential error pointer dereference
PCI: qcom: Fix missing error code in qcom_pcie_probe()
PCI: qcom: Add OPP support to scale performance
PCI: Bring the PCIe speed to MBps logic to new pcie_dev_speed_mbps()
PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path
PCI: qcom-ep: Disable resources unconditionally during PERST# assert
PCI: qcom-ep: Override NO_SNOOP attribute for SA8775P EP
PCI: qcom: Override NO_SNOOP attribute for SA8775P RC
PCI: epf-mhi: Enable HDMA for SA8775P SoC
PCI: qcom-ep: Add HDMA support for SA8775P SoC
PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers
PCI: dwc: Skip finding eDMA channels count for HDMA platforms
PCI: dwc: Refactor dw_pcie_edma_find_chip() API
PCI: qcom-ep: Add support for SA8775P SOC
dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC
PCI: qcom: Use devm_clk_bulk_get_all() API
- Move PLDA XpressRICH generic DT binding properties to
plda,xpressrich3-axi-common.yaml where they can be shared across
PLDA-based drivers (Minda Chen)
- Create a drivers/pci/controller/plda/ directory for PLDA-based drivers
and move pcie-microchip-host.c there (Minda Chen)
- Move PLDA generic macros to pcie-plda.h where they can be shared across
drivers (Minda Chen)
- Extract PLDA generic structures from pcie-microchip-host.c, rename them
to be generic, and move them to pcie-plda-host.c where they can be shared
across drivers (Minda Chen)
- Add a .request_event_irq() callback for requesting device-specific
interrupts in addition to PLDA-generic interrupts (Minda Chen)
- Add DT binding and driver for the StarFive JH7110 SoC, based on PLDA IP
(Minda Chen)
* pci/controller/microchip:
PCI: starfive: Add JH7110 PCIe controller
dt-bindings: PCI: Add StarFive JH7110 PCIe controller
PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value
PCI: plda: Pass pci_host_bridge to plda_pcie_setup_iomems()
PCI: plda: Add host init/deinit and map bus functions
PCI: plda: Add event bitmap field to struct plda_pcie_rp
PCI: microchip: Move IRQ functions to pcie-plda-host.c
PCI: microchip: Add event irqchip field to host port and add PLDA irqchip
PCI: microchip: Add get_events() callback and PLDA get_event()
PCI: microchip: Add INTx and MSI event num to struct plda_event
PCI: microchip: Add request_event_irq() callback function
PCI: microchip: Add num_events field to struct plda_pcie_rp
PCI: microchip: Rename interrupt related functions
PCI: microchip: Move PLDA functions to pcie-plda-host.c
PCI: microchip: Rename PLDA functions to be generic
PCI: microchip: Move PLDA structures to plda-pcie.h
PCI: microchip: Rename PLDA structures to be generic
PCI: microchip: Add bridge_addr field to struct mc_pcie
PCI: microchip: Move PLDA IP register macros to pcie-plda.h
PCI: microchip: Move pcie-microchip-host.c to PLDA directory
dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties
# Conflicts:
# drivers/pci/pci.h
- Enable BAR 0 only for v3.65a to avoid Completion Timeouts that
cause a 45 second boot delay on the v4.90a-based AM654x SoC (Siddharth
Vadapalli)
- Avoid a NULL pointer dereference if DT failed to provide a host bridge
memory window (Aleksandr Mishin)
* pci/controller/keystone:
PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
PCI: keystone: Fix NULL pointer dereference in case of DT error in ks_pcie_setup_rc_app_regs()
PCI: keystone: Don't enable BAR 0 for AM654x
PCI: keystone: Relocate ks_pcie_set/clear_dbi_mode()
- Return zero, not garbage, when reading PCI_INTERRUPT_PIN from a Hyper-V
device (Wei Liu)
* pci/controller/hyperv:
PCI: hv: Return zero, not garbage, when reading PCI_INTERRUPT_PIN
- Correct the dra7xx_pcie_cpu_addr_fixup() parameter name, which takes a
CPU address but called it "pci_addr" (Niklas Cassel)
* pci/controller/dra7xx:
PCI: dra7xx: Fix dra7xx_pcie_cpu_addr_fixup() parameter name
- Correct the artpec6_pcie_cpu_addr_fixup() parameter name, which takes a
CPU address but called it "pci_addr" (Niklas Cassel)
* pci/controller/artpec6:
PCI: artpec6: Fix artpec6_pcie_cpu_addr_fixup() parameter name
- Check IORESOURCE_BUS existence to avoid NULL pointer dereference
(Aleksandr Mishin)
* pci/controller/al:
PCI: al: Check IORESOURCE_BUS existence during probe
- Use msleep() in DWC core instead of usleep_range() for ~100 ms sleep
(Konrad Dybcio)
- Fix iATU slot management to avoid using the wrong slot after PERST#
assert/deassert, which could potentially cause DMA to go the wrong place
(Frank Li)
- Consolidate dw_pcie_prog_outbound_atu() arguments into a struct to ease
adding new functionality like initiating Message TLPs (Yoshihiro Shimoda)
- Add support for endpoints to initiate PCIe messages (Yoshihiro Shimoda)
- Add #defines for PCIe INTx messages (Yoshihiro Shimoda)
- Add support for endpoints to initiate PCIe PME_Turn_Off messages for
system suspend (Frank Li)
- Add dw_pcie_ep_linkdown() to reinitialize registers that are lost when
the link goes down (Manivannan Sadhasivam)
- Use dw_pcie_ep_linkdown() to reinitialize qcom non-sticky registers that
are lost when the link goes down (Manivannan Sadhasivam)
- Enforce DWC limitation that 64-bit BARs must start with the even numbered
BAR (Niklas Cassel)
* pci/controller/dwc:
PCI: dwc: ep: Enforce DWC specific 64-bit BAR limitation
PCI: layerscape-ep: Use the generic dw_pcie_ep_linkdown() API to handle Link Down event
PCI: qcom-ep: Use the generic dw_pcie_ep_linkdown() API to handle Link Down event
PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper
PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown() API to handle Link Down event
PCI: dwc: Add generic MSG TLP support for sending PME_Turn_Off when system suspend
PCI: Add PCIE_MSG_CODE_PME_TURN_OFF message macro
PCI: Add PCIE_MSG_CODE_ASSERT_INTx message macros
PCI: dwc: Add outbound MSG TLPs support
PCI: dwc: Consolidate args of dw_pcie_prog_outbound_atu() into a structure
PCI: dwc: Fix index 0 incorrectly being interpreted as a free ATU slot
PCI: dwc: Use msleep() in dw_pcie_wait_for_link()
- Include <linux/irqchip/chained_irq.h> in dra7xx to avoid implicitly
including it elsewhere (Andy Shevchenko)
- Remove unused <linux/of_gpio.h> from aardvark and dwc drivers (dra7xx,
meson, qcom, tegra194) (Andy Shevchenko)
- Convert kirin to use scoped for_each_available_child_of_node() to ease
future error exits (Javier Carrasco)
- Convert imx6 and kirin to use the agnostic GPIO API to simplify GPIO
setup and remove usage of the deprecated of_gpio.h API (Andy Shevchenko)
* pci/controller/gpio:
PCI: kirin: Convert to use agnostic GPIO API
PCI: kirin: Convert kirin_pcie_parse_port() to scoped iterator
PCI: imx6: Convert to use agnostic GPIO API
PCI: dwc: Remove unused of_gpio.h inclusion
PCI: aardvark: Remove unused of_gpio.h inclusion
PCI: dra7xx: Add missing chained IRQ header inclusion
- Remove unused struct pci_epf_group.type_group (Christophe JAILLET)
- Use cached epc_features instead of pci_epc_get_features() to avoid having
to check for failure (potential NULL pointer dereference) (Manivannan
Sadhasivam)
- Drop pointless local msix_capable variable in pci_epf_test_alloc_space()
(Manivannan Sadhasivam)
- Rename struct pci_epc_event_ops.core_init to .epc_init, since "core" is
no longer meaningful here (Manivannan Sadhasivam)
- Rename pci_epc_bme_notify(), pci_epf_mhi_bme(), pci_epc_bme_notify() to
spell out "bus_master_enable" instead of "bme" (Manivannan Sadhasivam)
- Factor pci_epf_test_clear_bar() and pci_epf_test_free_space() out of
pci_epf_test_unbind() so they can be reused elsewhere (Manivannan
Sadhasivam)
- Move DMA initialization to the pci_epf_mhi_epc_init() callback so
endpoint drivers do this uniformly (Manivannan Sadhasivam)
- Add endpoint testing for Link Down events (Manivannan Sadhasivam)
- Add 'epc_deinit' event so endpoints that can be reset via PERST# (qcom,
tegra194) can notify EPF drivers when this happens (Manivannan
Sadhasivam)
- Make pci_epc_class constant (Greg Kroah-Hartman)
- Fix vpci_scan_bus() error checking to print error for failure (not
success) and clean up after failure (Dan Carpenter)
- Fix epf_ntb_epc_cleanup() error handling to clean up scratchpad BARs and
clean up in mirror order of allocation (Dan Carpenter)
- Add rk3588, which requires 64KB BAR alignment, to pci_endpoint_test
(Niklas Cassel)
- Use memcpy_toio()/memcpy_fromio() for endpoint BAR tests to improve
performance (Niklas Cassel)
- Set DMA mask to 48 bits always to simplify endpoint test, since there's
there's no need to check for error or to fallback to 32 bits (Frank Li)
- Suggest using programmable Vendor/Device ID (when supported) to use
pci_endpoint_test without having to add new entries (Yoshihiro Shimoda)
- Remove unused pci_endpoint_test_bar_{readl,writel}() (Jiapeng Chong)
- Remove 'linkup' and add 'add_cfs' to the endpoint function driver 'ops'
documentation to match the code (Alexander Stein)
-
* pci/endpoint:
Documentation: PCI: pci-endpoint: Fix EPF ops list
misc: pci_endpoint_test: Remove unused pci_endpoint_test_bar_{readl,writel} functions
misc: pci_endpoint_test: Document policy about adding pci_device_id
misc: pci_endpoint_test: Refactor dma_set_mask_and_coherent() logic
misc: pci_endpoint_test: Use memcpy_toio()/memcpy_fromio() for BAR tests
misc: pci_endpoint_test: Add support for Rockchip rk3588
PCI: endpoint: Fix error handling in epf_ntb_epc_cleanup()
PCI: endpoint: Clean up error handling in vpci_scan_bus()
PCI: endpoint: Make pci_epc_class struct constant
PCI: endpoint: Introduce 'epc_deinit' event and notify the EPF drivers
PCI: endpoint: pci-epf-test: Handle Link Down event
PCI: endpoint: pci-epf-{mhi/test}: Move DMA initialization to EPC init callback
PCI: endpoint: pci-epf-test: Refactor pci_epf_test_unbind() function
PCI: endpoint: Rename BME to Bus Master Enable
PCI: endpoint: Rename core_init() callback in 'struct pci_epc_event_ops' to epc_init()
PCI: endpoint: pci-epf-test: Use 'msix_capable' flag directly in pci_epf_test_alloc_space()
PCI: endpoint: pci-epf-test: Make use of cached 'epc_features' in pci_epf_test_core_init()
PCI: endpoint: Remove unused field in struct pci_epf_group
- Add "apb", "sys", "pmc", "msg", "err" for Endpoint descriptions as well
as for Root Complexes (Niklas Cassel)
- Add "tx_inta", "tx_intb", "tx_intc", "tx_intd" for interrupt signals
triggered in response to PCIe Assert_INTx messages (Niklas Cassel)
- Refactor rockchip-dw-pcie binding to move generic properties to a new
rockchip-dw-pcie-common binding that can be shared by both RC and EP mode
(Niklas Cassel)
- Fix rockchip-dw-pcie description of INTx signals (Niklas Cassel)
- Add rockchip-dw-pcie description of Endpoint controller (Niklas Cassel)
- Avoid xilinx-versal-cpm overlapping of bridge registers and 32-bit BAR
addresses (Thippeswamy Havalige)
- Add qcom Operating Performance Points (OPP) table (Krishna chaitanya
chundru)
- Add a picture of mediatek,mt7621-pcie topology (Sergio Paracuellos)
- Add a generic "ats-supported" property so the OS can discover whether a
Root Complex supports ATS (Jean-Philippe Brucker)
- Make the qcom,pcie-x1e80100 MHI register region mandatory (Abel Vesa)
* pci/dt-bindings:
dt-bindings: PCI: qcom: x1e80100: Make the MHI reg region mandatory
dt-bindings: PCI: generic: Add ats-supported property
dt-bindings: PCI: mediatek,mt7621-pcie: Add PCIe host topology ASCII graph
dt-bindings: PCI: qcom: Add OPP table
dt-bindings: PCI: xilinx-cpm: Fix overlapping of bridge register and 32-bit BAR addresses
dt-bindings: PCI: rockchip: Add DesignWare based PCIe Endpoint controller
dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy IRQ
dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support
dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy IRQs
dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names
dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name
- Rename find_resource() to find_resource_space() to make it more
descriptive for exporting outside resource.c (Ilpo Järvinen)
- Document find_resource_space() and the resource_constraint struct it uses
(Ilpo Järvinen)
- Add typedef resource_alignf to make it simpler to declare allocation
constraint alignf callbacks (Ilpo Järvinen)
- Open-code the no-constraint simple alignment case to make the
simple_align_resource() default callback unnecessary (Ilpo Järvinen)
- Export find_resource_space() because PCI bridge window allocation needs
to learn whether there's space for a window (Ilpo Järvinen)
- Fix a double-counting problem in PCI calculate_memsize() that led to
allocating larger windows each time a bus was removed and rescanned (Ilpo
Järvinen)
- When we don't have space to allocate larger bridge windows, allocate
windows only large enough for the downstream devices to prevent cases
where a device worked originally, but not after being removed and
re-added (Ilpo Järvinen)
* pci/resource:
PCI: Relax bridge window tail sizing rules
PCI: Make minimum bridge window alignment reference more obvious
PCI: Fix resource double counting on remove & rescan
resource: Export find_resource_space()
resource: Handle simple alignment inside __find_resource_space()
resource: Use typedef for alignf callback
resource: Document find_resource_space() and resource_constraint
resource: Rename find_resource() to find_resource_space()
- Warn about doing a Secondary Bus Reset without holding the device lock
(Dan Williams)
- Lock bridge in addition to downstream hierarchy before doing a Secondary
Bus Reset (Dan Williams)
* pci/reset:
PCI: Add missing bridge lock to pci_bus_lock()
PCI: Warn on missing cfg_access_lock during secondary bus reset
- Detect if a device was removed or replaced during system sleep so we
don't assume a new device is the one that used to be there. This uses
Vendor/Device/Subsystem/Class/Revision and Device Serial Number (if
implemented), so it's not fool-proof and drivers may know how to detect
more cases (Lukas Wunner)
- Add missing MODULE_DESCRIPTION() macro (Jeff Johnson)
* pci/hotplug:
PCI: acpiphp: Add missing MODULE_DESCRIPTION() macro
PCI: pciehp: Detect device replacement during system sleep
- Disable AER and DPC during suspend so that if they share an interrupt
with PME and errors occur during suspend, the AER or DPC interrupt
doesn't cause spurious wakeups (Kai-Heng Feng)
* pci/err:
PCI/DPC: Disable DPC service on suspend
PCI/AER: Disable AER service on suspend
- Move the PRESERVE_BOOT_CONFIG ACPI _DSM evaluation from drivers/acpi to
drivers/pci so we can unify with similar DT functionality (Vidya Sagar)
- Add of_pci_preserve_config() to check for a DT "linux,pci-probe-only"
property on a per-host bridge basis in addition to a global basis (Vidya
Sagar)
- Unify ACPI PRESERVE_BOOT_CONFIG _DSM and DT "linux,pci-probe-only" in a
generic pci_preserve_config() path (Vidya Sagar)
* pci/enumeration:
PCI: Use preserve_config in place of pci_flags
PCI: Unify ACPI and DT 'preserve config' support
PCI: of: Add of_pci_preserve_config() for per-host bridge support
PCI: Move PRESERVE_BOOT_CONFIG _DSM evaluation to pci_register_host_bridge()
- If there's a device below a bridge, prevent a use-after-free by holding a
reference to the device while waiting for the secondary bus to be ready
in case the device is concurrently removed, e.g., by DPC (Lukas Wunner)
* pci/dpc:
PCI/DPC: Fix use-after-free on concurrent DPC and hot-removal
- Add pcim_add_mapping_to_legacy_table() and
pcim_remove_mapping_from_legacy_table() helper functions to simplify
devres iomap table (Philipp Stanner)
- Reimplement devres that take a bit mask of BARs in a way that can be used
to map partial BARs as well as entire BARs (Philipp Stanner)
- Deprecate pcim_iomap_table() and pcim_iomap_regions_request_all() in
favor of pcim_* request plus pcim_* mapping (Philipp Stanner)
- Add pcim_request_region(), a managed interface to request a single BAR
(Philipp Stanner)
- Use the existing pci_is_enabled() interface to replace the struct
devres.enabled bit (Philipp Stanner)
- Move the struct pci_devres.pinned bit to struct pci_dev (Philipp Stanner)
- Reimplement pcim_set_mwi() so it uses its own devres cleanup callback
instead of a special-purpose bit in struct pci_devres (Philipp Stanner)
- Add pcim_intx(), which is unambiguously managed, unlike pci_intx(), which
is managed if pcim_enable_device() has been called but unmanaged
otherwise (Philipp Stanner)
- Remove pcim_release(), which is no longer needed after previous cleanups
of pcim_set_mwi() and pci_intx() (Philipp Stanner)
- Add pcim_iomap_range(), a managed interface to map part of a BAR (Philipp
Stanner)
- Fix vboxvideo leak by using the new pcim_iomap_range() instead of the
unmanaged pci_iomap_range() (Philipp Stanner)
* pci/devres:
drm/vboxvideo: fix mapping leaks
PCI: Add managed pcim_iomap_range()
PCI: Remove legacy pcim_release()
PCI: Add managed pcim_intx()
PCI: Give pcim_set_mwi() its own devres cleanup callback
PCI: Move struct pci_devres.pinned bit to struct pci_dev
PCI: Remove struct pci_devres.enabled status bit
PCI: Document hybrid devres hazards
PCI: Add managed pcim_request_region()
PCI: Deprecate pcim_iomap_table(), pcim_iomap_regions_request_all()
PCI: Add managed partial-BAR request and map infrastructure
PCI: Add devres helpers for iomap table
PCI: Add and use devres helper for bit masks
The LS7A chipset can be used as part of a PCIe Root Complex with
Loongson-3C6000 and similar CPUs. In this case, DEV_LS7A_PCIE_PORT5 has a
PCI_CLASS_BRIDGE_HOST class code, and it is a Type 0 Function whose config
space provides access to Root Complex registers.
The DEV_LS7A_PCIE_PORT5 has an MSI Capability, and its MSI Enable bit must
be set before other devices below the Root Complex can use MSI. This is
not the standard PCI behavior of MSI Enable, so the normal PCI MSI code
does not set it.
Set the DEV_LS7A_PCIE_PORT5 MSI Enable bit via a quirk so other devices
below the Root Complex can use MSI.
[kwilczynski: exit early to reduce indentation; commit log]
Link: https://lore.kernel.org/linux-pci/20240612065315.2048110-1-chenhuacai@loongson.cn
Signed-off-by: Sheng Wu <wusheng@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org
