Commit Graph

6 Commits

Author SHA1 Message Date
Chen-Yu Tsai
63d8c7b9c3 clk: sunxi: usb: Sort clk providers by chip family and name
The latest addition of H3 USB clocks placed them at the bottom. Move it
before A80 (sun9i), so they are sorted by SoC family then name.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-25 10:26:03 +01:00
Reinder de Haan
7bec0200ac clk: sunxi: Add support for the H3 usb phy clocks
The H3 has a usb-phy clk register which is similar to that of earlier
SoCs, but with support for a larger number of phys. So we can simply add
a new set of clk-data and a new compatible and be done with it.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-11-20 13:50:19 +01:00
Stephen Boyd
9dfefe8c76 clk: sunxi: Include clk.h and remove unused clkdev.h includes
This clock provider uses the consumer API, so include clk.h
explicitly. Also remove clkdev.h in files that aren't using it
and include slab.h when clkdev.h was being used to implicitly
include it.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20 11:11:26 -07:00
Hans de Goede
ec80749dfd clk: sunxi: Add support for the usb-clk on sun8i a23 and a33 SoCs
The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found
on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic
interface which gets enabled by almost the same bits as used on
the a31 for the 3rd phy, but not exactly the same bits so we need
a new compatible for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-06-02 10:24:39 +02:00
Chen-Yu Tsai
71f32f56cb clk: sunxi: Add support for sun9i A80 USB clocks and resets
The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
controller. Also, access to the address block is controlled by a
clock gate to AHB.

Add support for resets requiring a clock to be enabled when
asserting/deasserting the reset controls, and add the sun9i USB
clocks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-02-23 09:25:54 +01:00
Chen-Yu Tsai
6089ef19c9 clk: sunxi: Move USB clocks to separate file
The USB clocks originally shared code with the gates clocks, but had
additional reset controllers. Move these to a separate file. This will
allow us to add new support for slightly different USB clocks, such as
on the A80, without affecting gates clocks, and also facilitate the
migration of gates clocks to a generic solution.

This also cleans up the USB clocks code slightly, such as adding
newlines, getting rid of the unused clkdev call, using a simple
u32 instead of BITMAP for the clock masks, using BIT() macro to
declare the clock bitmasks, and using of_io_request_and_map() to
get the I/O address.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-02-23 09:25:54 +01:00