This switches the abx500 driver to use the pin control helper
utils for allocating and free:ing maps.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We refactor the DT parser to look for either a config or a
function and then look for further nodes and reserve maps,
not the two things mixed up like prior to this patch.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
By converting to the restart_notifier mechanism for restart, we allow
for other mechanisms, like the watchdog, to be used for restart in the
case where PS_HOLD has failed to reset the chip.
Since this mechanism may be one of several mechanisms registered, change
the post-ps_hold write timeout to be a more reasonable 1 second instead
of 10 seconds.
Choose priority 128, as according to documentation, this mechanism "is
sufficient to restart the entire system".
Tested-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The SoC data structure allocated at init time only holds a regulator
pointer that is only used in the init function. Replace it with a local
variable and get rid of the SoC data structure allocation altogether.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The berlin_pinctrl_dt_free_map function tries to free memory
allocated and handled by the of subsystem. This is wrong and
already handled by pinctrl_dt_free_maps() which calls
of_node_put().
This patch fixes the Berlin pinctrl way of freeing its maps,
avoiding a kernel BUG(), by using the common
pinctrl_utils_dt_free_map function instead.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Disable Pull-Down or Pull-Up property before enabling Pull-Up or
Pull-Down, because the pin's Pull-Up and Pull-Down property is
mutually exclusive.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch removes a call to panic function when gpiochio_irqchip_add
fails and just returns the error to the calling function.
Same return value is used to handle the error case and adds a lable
to release resources on error.
The error message has been improved to indicate failure to add irqchip
to gpiochip.
This also changes first argument to function at91_gpio_of_irq_setup from
struct device_node to struct platform_device. Because The device_node
argument was anyway not being used. Passed pdev so that on failure dev_err
can use &pdev->dev and log can be associated with proper device.
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
CC: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This fixes the whole error handling in probe function by capturing and
returning error values on kernel function like clk_prepare,
clk_enable, gpiochip_add etc.
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
CC: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pinctrl driver initialized the register offsets for the pins
with 0. On Vybrid an offset of 0 is a valid offset for the pinctrl
mux register. So far, this was solved using the ZERO_OFFSET_VALID
flag which allowed offsets of 0. However, this does not allow to
verify whether a pins struct imx_pmx_func was initialized or not.
Use signed offset values for register offsets and initialize those
with -1 in order to detect uninitialized offset values reliable.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds MIPI CSI/DSIB pad control mux register
from the APB misc block to tegra pinctrl.
Without writing to this register, the dsib pads are
muxed as csi, and cannot be used.
The register is not yet documented in the TRM, here is
the description:
70000820: APB_MISC_GP_MIPI_PAD_CTRL_0
[31:02] RESERVED
[01:01] DSIB_MODE [CSI=0,DSIB=1]
[00:00] RESERVED
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch switches to using managed version of clk_get and hence
removes clk_put from failure path.
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
CC: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch removes call to gpiochip_remove_pin_ranges() from
platform_driver remove function as it will anway be called
by gpiochip_remove().
CC: Sonic Zhang <sonic.zhang@analog.com>
CC: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
commit 03e9f0cac5
"pinctrl: clean up after enable refactoring"
renamed the vtable callback .enable to .set_mux. The
renaming was done manually, and one of the alterations
contained a freudian slip. I confess, I am human.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The SAMA5 and SAM9x5 series both have drive strength
options for the PIOs. This patch adds the ability to set
one of three hardware options for drive strengths of low,
medium or high for the each pin. The actual current output
of the chip based on the setting is defined in the datasheets
and varies per pins separate from banks and with supply
voltage.
This patch adds three new dt-bindings that allow setting the
strength when configuring pins. By default, no change will
be made to the drive strength of a pin from its reset value.
Due to the difference between the register addresses of the
SAMA5 and SAM9x5 series, a new sama5d3-pinctrl id was added.
Signed-off-by: Marek Roszko <mark.roszko@gmail.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
we have done that for atlas6 in commit ed36c1a, 086b8904 etc. here we
do same things for prima2.
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Currently the value used to specify that interrupts from the gpio should
be routed to the application processor is hardcoded for all Qualcomm SoCs.
But the new APQ8084 SoC uses a different value. To resolve this, we make
this value configurable for each SoC. For all existing SoCs we continue
to use the current value, and only for APQ8084 we use the new value.
Suggested-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patchset adds pinctrl support for the Qualcomm APQ8084 platform.
This set of patches adds pinctrl support for the Qualcomm APQ8084 platform.
The first patch adds the pin definitions. The second patch contains the
devicetree binding documentation. The third patch adds the DT node.
The last patch makes the INTR_TARGET_PROC_APPS value configurable and
defines it for each existing SoC.
Tested on IFC6540 board.
Changes since v3:
- Fixed the sdc valid pin values in the binding documentation - sdc2
instead of sdc3. (suggested by Bjorn Andersson)
Changes since v2:
- Fixed some incorrect bits and offsets. (suggested by Bjorn Andersson)
- Updated binding documentation to follow the format of msm8960.
(suggested by Bjorn Andersson)
- Added fourth patch, which removes the hardcoded INTR_TARGET_PROC_APPS
value and makes it configurable. Also we keep the current value for
existing SoCs. (suggested by Bjorn Andersson)
Changes since v1:
- Updated the total number of pins (suggested by Bjorn Andersson)
- Added the missing pin info (provided by Andy Gross)
- Updated groups and functions to be consistent with other pinctrls.
(suggested by Andy Gross)
- Removed unused functions, qdss and test pins. (suggested by Andy Gross)
- Updated the documentation with the possible functions.
Reviewed-by: Andy Gross <agross@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The vtable named *pinmux_ops in the affected files are not really
about pin multiplexing, but a struct related to some PFC-specific
operations, inclusing pin config (bias setting). Rename the variable
so as to avoid confusions.
Acked-by: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This moves all the Freescale-related drivers (i.MX and MXS) to
its own subdirectory to clear the view.
Cc: Alexander Shiyan <shc_work@mail.ru>
Cc: Anson Huang <b20788@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Denis Carikli <denis@eukrea.com>
Cc: Markus Pargmann <mpa@pengutronix.de>
Cc: Greg Ungerer <gerg@uclinux.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
commit 2243a87d90
"pinctrl: avoid duplicated calling enable_pinmux_setting for a pin"
removed the .disable callback from the struct pinmux_ops,
making the .enable() callback the only remaining callback.
However .enable() is a bad name as it seems to imply that a
muxing can also be disabled. Rename the callback to .set_mux()
and also take this opportunity to clean out any remaining
mentions of .disable() from the documentation.
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Acked-by: Fan Wu <fwu@marvell.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds support for reset functions to reboot the boards
with soc apq8064.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: "Ivan T. Ivanov" <iivanov@mm-sol.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Andy Gross <agross@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch releases gpiochip related resources by calling
gpiochip_remove when either of gpiochip_add_pin_range and
gpiochip_irqchip_add fails.
CC: Linus Walleij <linus.walleij@linaro.org>
CC: "Ivan T. Ivanov" <iivanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is currently a kludge to get the Makefile to move down
to sh-pfc:s drivers: the arch definitions are used twice to
get it done. However we can very well use the Kconfig symbol
for the SH PFC pin control feature itself: it doesn't matter
that it comes from a lower leaf in the Kconfig hierarchy which
is completely orthogonal.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samsung Exynos7 is a ARM64bit processor. Which does not select
the CONFIG_PLAT_SAMSUNG symbol. CONFIG_PINCTRL_SAMSUNG is being
selected for both PLAT_SAMSUNG and ARCH_EXYNOS7 symbols.
This patch modifes the pinctrl/Makefile to use
CONFIG_PINCTRL_SAMSUNG symbol to compile the pinctrl/samsung/*.c
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: linus.walleij@linaro.org
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
AM437x pinctrl definitions now differ from traditional 16 bit OMAP pin
ctrl definitions, in that all 32 bits are used to describe a single pin
Also the location of wakeupenable and event bits have changed.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[nm@ti.com: minor updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
DRA7 pinctrl definitions now differ from traditional 16 bit OMAP pin
ctrl definitions, in that all 32 bits are used to describe a single pin
Also the location of wakeupenable and event bits have changed.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The I2S controller can use the external clock as reference clock with
master mode. But based on different hardware or software design, this
external clock might be needed or not needed.
So the external input pin can be an independent pinctrl group, and the
card driver can decice to get it or not.
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The I2S controller can output mclk to external audio codec. But by
hardware design, some codecs need mclk and some codecs do not need
mclk. So the mclk pin can be an independent pinctrl group, and the
card driver can get it or not based on boards.
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
According to key customer's requirement, fix "line over 80
characters".
Signed-off-by: Bin Shi <Bin.Shi@csr.com>
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Enable autoloading of pinctrl-imx6sl module when a corresponing DT entry is present.
Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Make of_device_id array const, because all OF functions handle it as
const.
Signed-off-by: Kiran Padwal <kiran.padwal21@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A handful of driver-related changes. We've had a bunch of them going in through
other branches as well, so it's only a part of what we really have this release.
Larger pieces are:
* Removal of a now unused PWM driver for atmel
- This includes AVR32 changes that have been appropriately acked.
* Performance counter support for the arm CCN interconnect
* OMAP mailbox driver cleanups and consolidation
* PCI and SATA PHY drivers for SPEAr 13xx platforms
* Redefinition (with backwards compatibility!) of PCI DT bindings for Tegra to
better model regulators/power.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJT5DrJAAoJEIwa5zzehBx3wkkP/iwEfEK5mMon9KEe4DcKTKNq
Z6xyWuMQNHKdfBFpABs6AsHQCKDc7KK6gN3+2zLLHEJ4XGDPZ2g2NaX3oRPJlaay
BDK7rQfIZyi4tmbOnlEv1BDTYgirYBPMwk9RyNo/04Ug3W+Y67aSVo44zkNFBWaJ
GbcX/zYsrsfvdawuQMW6V/A835s3Kq5Zhv1ikPr8gDDjswZRBAT6i7FYpBSHQ8K8
bH6C1891Xit6rxXSLXJyrtM8CAet7PtLTqNr/IKdUaJnGD+fJm5EonxW+g8gvhN8
gOEkm3nM60++kdDlzZCQVNr0m1+ih6NNCr6bDLO6rIRpAJM2O+YrN1rWuZaJOu1A
pIvifk+wWHT+o52pXk8g9fK4n/ZJydK3IBzDePHMrIROOEiW5tLE3WA+u3NSfMfH
WegMt9E2dcB+5gXPeejZ9gFbAHnh2S1oVTZfCYXtuOHrYiEU9U0FA3eRYvJEE2po
k8sdiOn7Vc65O1QZ+xZNbLABpAHaye7X2evOJyhSutzHE/AtUvT4vuCAZ0tggXyD
E1qVKngVW/NvcoFbwYeidq4bOVgiAEn3idZgF5gEq1mq7LzetXUQAcZAOQfLWHLQ
RrXufS7Ez8pSCG74y0AFReVfQH2PgWHPqGUGj99NXgQauexc/vR1Hc5Iqb8liGNJ
n6i8RqvvQ4KYcmHEXDIT
=fsP6
-----END PGP SIGNATURE-----
Merge tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson:
"A handful of driver-related changes. We've had a bunch of them going
in through other branches as well, so it's only a part of what we
really have this release.
Larger pieces are:
- Removal of a now unused PWM driver for atmel
[ This includes AVR32 changes that have been appropriately acked ]
- Performance counter support for the arm CCN interconnect
- OMAP mailbox driver cleanups and consolidation
- PCI and SATA PHY drivers for SPEAr 13xx platforms
- Redefinition (with backwards compatibility!) of PCI DT bindings for
Tegra to better model regulators/power"
Note: this merge also fixes up the semantic conflict with the new
calling convention for devm_phy_create(), see commit f0ed817638 ("phy:
core: Let node ptr of PHY point to PHY and not of PHY provider") that
came in through Greg's USB tree.
Semantic merge patch by Stephen Rothwell <sfr@canb.auug.org.au> through
the next tree.
* tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits)
bus: arm-ccn: Fix error handling at event allocation
mailbox/omap: add a parent structure for every IP instance
mailbox/omap: remove the private mailbox structure
mailbox/omap: consolidate OMAP mailbox driver
mailbox/omap: simplify the fifo assignment by using macros
mailbox/omap: remove omap_mbox_type_t from mailbox ops
mailbox/omap: remove OMAP1 mailbox driver
mailbox/omap: use devm_* interfaces
bus: ARM CCN: add PERF_EVENTS dependency
bus: ARM CCN PMU driver
PCI: spear: Remove spear13xx_pcie_remove()
PCI: spear: Fix Section mismatch compilation warning for probe()
ARM: tegra: Remove legacy PCIe power supply properties
PCI: tegra: Remove deprecated power supply properties
PCI: tegra: Implement accurate power supply scheme
ARM: SPEAr13xx: Update defconfigs
ARM: SPEAr13xx: Add pcie and miphy DT nodes
ARM: SPEAr13xx: Add bindings and dt node for misc block
ARM: SPEAr13xx: Fix static mapping table
phy: Add drivers for PCIe and SATA phy on SPEAr13xx
...
Unlike the board branch, this keeps having large sets of changes for
every release, but that's quite expected and is so far working well.
Most of this is plumbing for various device bindings and new platforms,
but there's also a bit of cleanup and code removal for things that
are moved from platform code to DT contents (some OMAP clock code in
particular).
There's also a pinctrl driver for tegra here (appropriately acked),
that's introduced this way to make it more bisectable.
I'm happy to say that there were no conflicts at all with this branch
this release, which means that changes are flowing through our tree as
expected instead of merged through driver maintainers (or at least not
done with conflicts).
There are several new boards added, and a couple of SoCs. In no particular
order:
* Rockchip RK3288 SoC support, including DTS for a dev board that they
have seeded with some community developers.
* Better support for Hardkernel Exynos4-based ODROID boards.
* CCF conversions (and dtsi contents) for several Renesas platforms.
* Gumstix Pepper (TI AM335x) board support
* TI eval board support for AM437x
* Allwinner A23 SoC, very similar to existing ones which mostly has
resulted in DT changes for support. Also includes support for an Ippo
tablet with the chipset.
* Allwinner A31 Hummingbird board support, not to be confused with the
SolidRun i.MX-based Hummingboard.
* Tegra30 Apalis board support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJT5DqvAAoJEIwa5zzehBx3tm0QAJk8zFyZuMhUPz6SoZTtO9ti
zojZ2218oqLRDfLSYdJx/3QE7gb2ef0e2S6FrthecdAY8sqZzDddL7M/cCf1WSgy
+D4dD1UEq+W/hOeEwIWyo3GR/71exgo/LMTIw8HOJh5c9fanQ2wNChNetCgh8b4u
sVOEMmP1UTO2W7mH9cCRhWXFifBNi0yNl1QBYnLPzM2CbSEa4qQRarTn/94NSEiY
U9XgzysklvYEW/30wcEkz8ZonKbJrtP+zEjODU4wN/muhHECeTehDrkJq0WEK/3C
3ptko2xQGURNaLM6HVvQS9qkXxyhCeZxqkELpjkjjM+YPFN8wdHu7gDctGZlDr39
LQ2pZF6K8vaFvxp3UM2wzdDeoNi3rxguzpFoBmfRP5NWguDrOvjT3w8W4hO9q04J
8SqMGca0av9myHmeSjtRRg5rmcC3kBbOgSN6siVJ8W80rHT7tnFjl6eCawDreQzn
szFzGaOOUnf/kJ/00vzm1dCuluowFPdSYgW3aamZhfkqu2qYJ8Ztuooz5eZGKtex
zlUfKtpL26gnamoUT42K7E8J968AjHjUc/zimwYzIgHCzTTApYGJQcbD/Y28b8QH
gTvhRxP+0kFb+NNq4IHStVMvJrFOPvzOHXcL8x07HqTxrl7W4XoW+KJxCJOk433W
5NJ9s4tEmiTRMtFL1kv6
=xxlY
-----END PGP SIGNATURE-----
Merge tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device-tree changes from Olof Johansson:
"Unlike the board branch, this keeps having large sets of changes for
every release, but that's quite expected and is so far working well.
Most of this is plumbing for various device bindings and new
platforms, but there's also a bit of cleanup and code removal for
things that are moved from platform code to DT contents (some OMAP
clock code in particular).
There's also a pinctrl driver for tegra here (appropriately acked),
that's introduced this way to make it more bisectable.
I'm happy to say that there were no conflicts at all with this branch
this release, which means that changes are flowing through our tree as
expected instead of merged through driver maintainers (or at least not
done with conflicts).
There are several new boards added, and a couple of SoCs. In no
particular order:
- Rockchip RK3288 SoC support, including DTS for a dev board that
they have seeded with some community developers.
- Better support for Hardkernel Exynos4-based ODROID boards.
- CCF conversions (and dtsi contents) for several Renesas platforms.
- Gumstix Pepper (TI AM335x) board support
- TI eval board support for AM437x
- Allwinner A23 SoC, very similar to existing ones which mostly has
resulted in DT changes for support. Also includes support for an
Ippo tablet with the chipset.
- Allwinner A31 Hummingbird board support, not to be confused with
the SolidRun i.MX-based Hummingboard.
- Tegra30 Apalis board support"
* tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits)
ARM: dts: Enable USB host0 (EHCI) on rk3288-evb
ARM: dts: add rk3288 ehci usb devices
ARM: dts: Turn on USB host vbus on rk3288-evb
ARM: tegra: apalis t30: fix device tree compatible node
ARM: tegra: paz00: Fix some indentation inconsistencies
ARM: zynq: DT: Clarify Xilinx Zynq platform
ARM: dts: rockchip: add watchdog node
ARM: dts: rockchip: remove pinctrl setting from radxarock uart2
ARM: dts: Add missing pinctrl for uart0/1 for exynos3250
ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250
ARM: dts: Add TMU dt node to monitor the temperature for exynos3250
ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250
ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only
ARM: dts: max77686 is exynos5250-snow only
ARM: zynq: DT: Remove DMA from board DTs
ARM: zynq: DT: Add CAN node
ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table
ARM: dts: Add PMU DT node for exynos5260 SoC
ARM: EXYNOS: Add support for Exynos5410 PMU
ARM: dts: Add PMU to exynos5410
...
development cycle:
- Get rid of the .disable() callback from the driver callback
vtable. This callback was abused and counterintuitive since
a pin or group of pins can be said to always be in some
setting, and never really disabled. We now only enable a
certain muxing, and move between some certain muxings, we
never "disable" a mux setting.
- Some janitorial moving the MSM, Samsung and Nomadik and
drivers to their own subdirectories for a clearer view in
the subsystem. This will continue.
- Kill off the use of the return value from gpiochip_remove(),
this will be done in parallel in the GPIO subsystem and
hopefully not trigger too many unchecked return value
warnings before we get rid of this altogether.
- A huge set of changes and improvements to the Allwinner
sunxi drivers especially for their latest A23 and A31 SoCs,
and some ground work for the new sun8i platform family.
- A large set of Rockchip driver improvements adding support
for the RK3288 SoC.
- Advances in migration of older Freescale platforms to pin
control, especially i.MX1.
- Samsung and Exynos improvements.
- Support for the Qualcomm MSM8960 SoC.
- Use the gpiolib irqchip helpers for the ST SPEAr and
Intel Baytrail drivers.
- A bunch of nice janitorial work done with cppcheck.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT41HwAAoJEEEQszewGV1zVN0QAMJOJcsjYyHG+b/y0upJ5n1c
tyPelyxKrpGUUTvTsO5LiqvoIfa2E/DrwXupRAC4zAXvb+x3TUGkiluK4Yxl5e56
AqjePnSydqqHiRZOK4Q06W7VwGUoxLltDmDPTcra+DAaijIeKUPMQE1MvcPxisMe
IR7PZN58JYCG3ZV5yjwfBBxcRAm8KiiwHvQdBywPIGGvvmpy1X+U96U869nQgUH2
70lpJVPx75bhyAFk99bE9nAnroZeRR7mvijjf26ssyAFNqeJ0K7Xlom+NtpHdiw0
lsDKdBiAWVbZON/7Pc24gpHzhBoIYdA/6LxPA8Xz4QVFRmfxmNkZhuXZnZ7Dbuj2
xv9HtnjExqjZcfeNyUlO0iQDEQIUN/oPkaBS2G8DNZ/bmQqC8EzkIFh6F72KO1s2
7FU214LcuBYuAa3HvNLmgtjSkgou8tTMj58rnZ1XDr2mI9tzlrwI3i6ZrJZWKDur
NIoRAcUZkFiMpXxqLbk4UXzDvuJgrzaFiQ2PkxTXAlC2DjXz+gXPzPIOSD5LTaHE
k3WvZfuGK2iPoKeDHaLx2qEl9PoD5hz1JH3o+bgOKkRZG2gEJWd02JwhuPyRPLfc
TeBgmdYS2t2MBS21VsqoObw8336oCHJu7tDAxTkAalLsZy9MV2WqThhZoYggZ/Rq
yMqCr8vfd2pRVtwYe7Wc
=t1pR
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl updates from Linus Walleij:
"This is the bulk pin control changes for the v3.17 merge development
cycle:
- get rid of the .disable() callback from the driver callback vtable.
This callback was abused and counterintuitive since a pin or group
of pins can be said to always be in some setting, and never really
disabled. We now only enable a certain muxing, and move between
some certain muxings, we never "disable" a mux setting
- some janitorial moving the MSM, Samsung and Nomadik and drivers to
their own subdirectories for a clearer view in the subsystem. This
will continue
- kill off the use of the return value from gpiochip_remove(), this
will be done in parallel in the GPIO subsystem and hopefully not
trigger too many unchecked return value warnings before we get rid
of this altogether
- a huge set of changes and improvements to the Allwinner sunxi
drivers especially for their latest A23 and A31 SoCs, and some
ground work for the new sun8i platform family
- a large set of Rockchip driver improvements adding support for the
RK3288 SoC
- advances in migration of older Freescale platforms to pin control,
especially i.MX1
- Samsung and Exynos improvements
- support for the Qualcomm MSM8960 SoC
- use the gpiolib irqchip helpers for the ST SPEAr and Intel Baytrail
drivers
- a bunch of nice janitorial work done with cppcheck"
* tag 'pinctrl-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (61 commits)
pinctrl: baytrail: Convert to use gpiolib irqchip
pinctrl: sunxi: number gpio ranges starting from 0
pinctrl: sunxi: use gpiolib API to mark a GPIO used as an IRQ
pinctrl: rockchip: add drive-strength control for rk3288
pinctrl: rockchip: add separate type for rk3288
pinctrl: rockchip: set is_generic in pinconf_ops
pinctrl: msm: drop negativity check on unsigned value
pinctrl: remove all usage of gpio_remove ret val in driver/pinctl
pinctrl: qcom: Make muxing of gpio function explicit
pinctrl: nomadik: move all Nomadik drivers to subdir
pinctrl: samsung: Group all drivers in a sub-dir
sh-pfc: sh73a0: Introduce the use of devm_regulator_register
sh-pfc: Add renesas,pfc-r8a7791 to binding documentation
pinctrl: msm: move all qualcomm drivers to subdir
pinctrl: msm: Add msm8960 definitions
pinctrl: samsung: Allow pin value to be initialized using pinfunc
pinctrl: samsung: Allow grouping multiple pinmux/pinconf nodes
pinctrl: exynos: Consolidate irq_chips of GPIO and WKUP EINTs
pinctrl: samsung: Handle GPIO request and free using pinctrl helpers
pinctrl: samsung: Decouple direction setting from pinctrl
...
Instead of open-coding irqchip handling in the driver we can take advantage
of the new irqchip helpers provided by the gpiolib core.
While doing this we also make sure that we call gpiochip_irqchip_add()
after the gpiochip itself is registered as required.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pinctrl-sunxi driver originally used the pin number as the gpio
range offset. This resulted in large, bogus gpio numbers for the
new sun6i-a31-r pinctrl devices.
This patch makes the driver number the gpios ranges starting from an
offset of 0, by subtracting the pin_base number from the pin number.
This also makes the system-wide gpio number match the pin number.
Tested on sun8i with sysfs exported gpios.
This patch also changes the GPIO bindings for R_PIO:
gpios = <&r_pio B N flag>;
Where B originally was the pinbank label (L or M) counted from A,
with this patch it becomes (L or M) counted from its pinbank base (L).
Thus
gpios = <&r_pio 10 11 0>; /* PL11 */
becomes
gpios = <&r_pio 0 11 0>; /* PL11 */
IMO this is correct, as the binding shows the bank offset and pin offset
within the bank for the GPIO controller. But I'm worried it might be a
bit confusing.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The rk3288 is the first Rockchip soc handling the drive strength on a per-pin
basis, while the older ones can set the drive-strength only for specific
pin-groups. Therefore limit setting the drive-strength to this soc for now.
Signed-off-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
An upcoming pinctrl function of the rk3288 differs again from everything else,
so we'll need a separate type for it.
Signed-off-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The rockchip pinctrl driver implements the generic pinconfig, therefore
also state this, so that the default pinconf dump functions work.
Signed-off-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Instead of relying on pinmux->disable(), make the gpio function an
explicit function for all pins that supports it.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
