Commit Graph

11 Commits

Author SHA1 Message Date
Stefan Roese
c40c7a990a mtd: spinand: Add support for GigaDevice GD5F1GQ4UExxG
Add support for GigaDevice GD5F1GQ4UExxG SPI NAND chip.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chuanhong Guo <gch981213@gmail.com>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-02-05 16:56:12 +01:00
Yoshio Furuyama
db214513f6 mtd: spinand: Add support for all Toshiba Memory products
Add device table for Toshiba Memory products.
Also, generalize OOB layout structure and function names.

Signed-off-by: Yoshio Furuyama <tmcmc-mb-yfuruyama7@ml.toshiba.co.jp>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-02-05 16:56:10 +01:00
Emil Lenngren
f4cb4d7b46 mtd: spinand: macronix: Fix ECC Status Read
The datasheet specifies the upper four bits are reserved.
Testing on real hardware shows that these bits can indeed be nonzero.

Signed-off-by: Emil Lenngren <emil.lenngren@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-02-05 15:39:39 +01:00
Chuanhong Guo
c93c613214 mtd: spinand: add support for GigaDevice GD5FxGQ4xA
Add support for GigaDevice GD5F1G/2G/4GQ4xA SPI NAND.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-12-07 10:59:23 +01:00
Schrempf Frieder
10949af168 mtd: spinand: Add initial support for Toshiba TC58CVG2S0H
Add minimal support for the Toshiba TC58CVG2S0H SPI NAND chip.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-12-07 10:38:23 +01:00
Robert Marko
9a4d830747 mtd: spinand: winbond: Add support for W25N01GV
W25N01GV is a single die version of the already supported
W25M02GV with half the capacity. Everything else is the
same so introduce support for W25N01GV.

Datasheet:http://www.winbond.com/resource-files/w25n01gv%20revl%20050918%20unsecured.pdf

Tested on 8devices Jalapeno dev board under OpenWrt running 4.19-rc5.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-11-05 10:56:56 +01:00
Miquel Raynal
3dfa025f89 mtd: spinand: macronix: Add support for MX35LF2GE4AB
MX35LF2GE4AB is almost identical to MX35LF1GE4AB except it has 2 times
more eraseblocks per LUN and exposes 2 planes instead of 1.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-07-18 09:24:12 +02:00
Boris Brezillon
b02308af05 mtd: spinand: Add initial support for the MX35LF1GE4AB chip
Add minimal support for the MX35LF1GE4AB SPI NAND chip.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-07-18 09:24:12 +02:00
Frieder Schrempf
1075492bb9 mtd: spinand: Add initial support for Winbond W25M02GV
Add support for the W25M02GV chip.

Signed-off-by: Frieder Schrempf <frieder.schrempf@exceet.de>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-07-18 09:24:11 +02:00
Peter Pan
a508e8875e mtd: spinand: Add initial support for Micron MT29F2G01ABAGD
Add a basic driver for Micron SPI NANDs. Only one device is supported
right now, but the driver will be extended to support more devices
afterwards.

Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-07-18 09:24:11 +02:00
Peter Pan
7529df4652 mtd: nand: Add core infrastructure to support SPI NANDs
Add a SPI NAND framework based on the generic NAND framework and the
spi-mem infrastructure.

In its current state, this framework supports the following features:

- single/dual/quad IO modes
- on-die ECC

Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-07-18 09:24:10 +02:00