This matches the datasheets and is less confusing since the register
has nothing to with advancing anything.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The code assumes 8-bit or 16-bit width registers, but three of the
chips (sx1501/sx1504/sx1507) are 4-bit. So, try to handle 4-bit chips as
well, they leave the high part of each register unused.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
the default mode of GPIO16 pin is gpio, when set EINT16 to
IRQ_TYPE_LEVEL_HIGH, no interrupt is triggered, it can be
fixed when set its default mode as usb iddig.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It should be possible to use the GPIOLIB_IRQCHIP helper
library with the BCM2835 driver since it is a pretty straight
forward cascaded irqchip.
The only difference from other drivers is that the BCM2835
has several banks for a single gpiochip, and each bank has
a separate IRQ line. Instead of creating one gpiochip per
bank, a single gpiochip covers all banks GPIO lines. This
makes it necessary to resolve the bank ID in the IRQ
handler.
The GPIOLIB_IRQCHIP allows several IRQs to be cascaded off
the same gpiochip by calling gpiochip_set_chained_irqchip()
repeatedly, but we have been a bit short on examples
for how this should be handled in practice, so this is intended
as an example of how this can be achieved.
The old code did not model the chip as a chained interrupt
handler, but this patch also rectifies that situation.
Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Tested-by: Eric Anholt <eric@anholt.net>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a new driver for pinconf on TI DA850/OMAP-L138/AM18XX. These
SoCs have a separate controller for controlling pullup/pulldown groups.
Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We switch the default handler to be handle_bad_irq() instead of
handle_simple_irq() (which was not correct anyway).
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
please pull the following:
- Rafal adds support for the Netgear R8500 routers, adds basic support
for the Tenda AC9 router which uses the new BCM53573 SoC (single core Cortex
A7). He also enables the UART on the Netgear R8000 and restructures the
include files a bit for the BCM47094 SoC, finally he adds USB 3.0 PHY nodes
which enables USB 3.0 on BCM5301X devices that support it. Finally he adds
support for the TP-LINK Archer C9 V1 router.
- Kamal adds support for the QSPI controller on the Northstar Plus SoCs and updates
the bcm958625k reference board to have it enabled
- Dan adds support for the Luxul XAP-1510 (using a BCM4708) and XWR-3100 (using
a BCM47094)
- Scott fixes the pinctrl names in the Cygnus DTS files
- Jonathan enables the Broadcom iProc mailbox controller for Broadcom Cygnus/iProc
SoCs, he adds interrupt support for the GPIO CRMU hardware block and finally adds
the node for the OTP controller found on Cygnus SoCs
- Dhananjay enables the GPIO B controller on Norstarh Plus SoCs
- Eric defines standard pinctrl groups in the BCM2835 GPIO node
- Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes
to use their appropriate pinctrl functions
- Linus adds names for the Raspberry Pi GPIO lines based on the datasheet
- Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block
- Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and
Device Tree nodes he also fixes the Raspberry Pi GPIO lines names and finally
adds names for the Raspberry Zero GPIO lines
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Merge tag 'arm-soc/for-4.10/devicetree' of http://github.com/Broadcom/stblinux into next/dt
Pull "Broadcom devicetree changes for 4.10" from Florian Fainelli:
This pull request contains Broadcom ARM-based SoC Device Tree changes for 4.10,
please pull the following:
- Rafal adds support for the Netgear R8500 routers, adds basic support
for the Tenda AC9 router which uses the new BCM53573 SoC (single core Cortex
A7). He also enables the UART on the Netgear R8000 and restructures the
include files a bit for the BCM47094 SoC, finally he adds USB 3.0 PHY nodes
which enables USB 3.0 on BCM5301X devices that support it. Finally he adds
support for the TP-LINK Archer C9 V1 router.
- Kamal adds support for the QSPI controller on the Northstar Plus SoCs and updates
the bcm958625k reference board to have it enabled
- Dan adds support for the Luxul XAP-1510 (using a BCM4708) and XWR-3100 (using
a BCM47094)
- Scott fixes the pinctrl names in the Cygnus DTS files
- Jonathan enables the Broadcom iProc mailbox controller for Broadcom Cygnus/iProc
SoCs, he adds interrupt support for the GPIO CRMU hardware block and finally adds
the node for the OTP controller found on Cygnus SoCs
- Dhananjay enables the GPIO B controller on Norstarh Plus SoCs
- Eric defines standard pinctrl groups in the BCM2835 GPIO node
- Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes
to use their appropriate pinctrl functions
- Linus adds names for the Raspberry Pi GPIO lines based on the datasheet
- Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block
- Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and
Device Tree nodes he also fixes the Raspberry Pi GPIO lines names and finally
adds names for the Raspberry Zero GPIO lines
* tag 'arm-soc/for-4.10/devicetree' of http://github.com/Broadcom/stblinux: (29 commits)
ARM: bcm2835: Add names for the RPi Zero GPIO lines
ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines
ARM: dts: enable GPIO-b for Broadcom NSP
ARM: BCM5301X: Add DT for TP-LINK Archer C9 V1
ARM: dts: Add node for Broadcom OTP controller driver
ARM: dts: Enable interrupt support for cygnus crmu gpio driver
ARM: dts: Enable Broadcom iProc mailbox controller
ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
ARM: bcm2835: dts: add thermal node to device-tree of bcm283x
dt: bindings: add thermal device driver for bcm2835
ARM: dts: bcm283x: fix typo in mailbox address
DT: binding: bcm2835-mbox: fix address typo in example
ARM: dts: cygnus: fix naming of pinctrl node
ARM: BCM53573: Specify PMU and its ILP clock in the DT
ARM: BCM5301X: Add DT for Luxul XWR-3100
ARM: BCM5301X: Add DT for Luxul XAP-1510
ARM: BCM5301X: Specify USB 3.0 PHY in DT
ARM: BCM5301X: Enable UART on Netgear R8000
ARM: BCM5301X: Add separated DTS include file for BCM47094
ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes
...
All other registers on these chips are 8-bit, but reg_sense is 16-bits
and therefore needs to be moved down one notch.
This was apparently overlooked in the conversion to regmap, which only
updated the register locations for the 16-bit chips.
Fixes: 6489677f86 ("pinctrl-sx150x: Replace sx150x_*_cfg by means of regmap API")
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If the chip does not have an oscio pin, all pins are configured in
the same regmap register making it trivial to update all pins at
once, so do that. If an oscio pin is present, there needs to be
more locking in place to handle all cases correctly, so this is
skipped.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use builtin_platform_driver() helper to simplify the code.
Signed-off-by: Geliang Tang <geliangtang@gmail.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use builtin_platform_driver() helper to simplify the code.
Signed-off-by: Geliang Tang <geliangtang@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Smatch complains that we dereference "map" before testing it for NULL
which is true. We should be testing "*map" instead. Also on the error
path, we should free *map and set it to NULL.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We should return -ENOMEM instead of success if pcs_add_function() fails.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
gcc warns about a way that it could use an uninitialized variable:
drivers/pinctrl/sunxi/pinctrl-sunxi.c: In function 'sunxi_pinctrl_init':
drivers/pinctrl/sunxi/pinctrl-sunxi.c:1191:8: error: 'best_div' may be used uninitialized in this function [-Werror=maybe-uninitialized]
This cannot really happen except if 'freq' is UINT_MAX and 'clock' is
zero, and both of these are forbidden. To shut up the warning anyway,
this changes the logic to initialize the return code to the first
divider value before looking at the others.
Fixes: 7c926492d3 ("pinctrl: sunxi: Add support for interrupt debouncing")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- DU and EtherAVB pin groups for R-Car M3-W,
- Bias handling cleanups and bug fixes,
- Drive-strength for non-GPIO pins for R-Car H3,
- EtherAVB MDIO & MII, and QSPI pin groups for R-Car H3.
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Merge tag 'sh-pfc-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.10 (take two)
- DU and EtherAVB pin groups for R-Car M3-W,
- Bias handling cleanups and bug fixes,
- Drive-strength for non-GPIO pins for R-Car H3,
- EtherAVB MDIO & MII, and QSPI pin groups for R-Car H3.
This add pinctrl support for Rockchip RK1108 Soc.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Series-changes: 2
- add pull and drive-strength functionality
Series-changes: 3
- two minor CodingStyle fixes adviced by Heiko
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc
drivers. The pins can not be muxed between functions other than QSPI,
but their drive strength can be controlled.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Group the AVB pins into similar groups found in other sh-pfc drivers.
The pins can not be muxed between functions other then AVB but their
drive strength can be controlled.
The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs
called avb_mdio. In pfc-r8a7795 the avb_mdc group already existed and
is in use in DT. Therefore add the ADV_MDIO pin to the existing group
instead of renaming it.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
There are pins on the r8a7795 which are not part of a GPIO bank nor
can be muxed between different functions. They do however allow for the
drive-strength to be configured. Add those pins to the list of pins and
to the drive-strength configuration registers.
The pins can now be referred to in DT by function names and their
drive-strength modified.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Pins not associated with a GPIO port can still have other configuration
parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named
pins to be declared with a set of configurations. The new macro is an
modification of SH_PFC_PIN_NAMED to allow for optional configuration to
be assigned.
The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be
used to define pins not associated with a GPIO port.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Change the data structure and use the generic sh_pfc_pin_to_bias_info()
function to get the register offset and bit information.
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
There is a bug in the r8a7795 bias code where a WARN() is trigged
anytime a pin from PUEN0/PUD0 is accessed.
# cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8
[..]
Call trace:
[<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
[<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
[<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
[<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
[<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
[<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
[<ffff0000081fe3bc>] seq_read+0x16c/0x420
[<ffff00000831a110>] full_proxy_read+0x58/0x88
[<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
[<ffff0000081d8874>] vfs_read+0x84/0x148
[<ffff0000081d9d64>] SyS_read+0x44/0xa0
[<ffff000008082f4c>] __sys_trace_return+0x0/0x4
This is due to the WARN() check if the reg field of the pullups struct
is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
registers since PU0 is defined as 0. Change the data structure and use
the generic sh_pfc_pin_to_bias_info() function to get the register
offset and bit information.
Fixes: 560655247b ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The last else statement is missing braces, and the indentation level can
be reduced.
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
On some SoC there are no simple mapping of pins to bias register bits
and a lookup table is needed. This logic is already implemented in some
SoC specific drivers that could benefit from a generic implementation.
Add helpers to deal with the lookup which later can be used by the SoC
specific drivers. The logic used to lookup are different from the one it
aims to replace, this is intentional. This new method reduces the memory
consumption at the cost of increased CPU usage and fix a bug where a
WARN() would incorrectly be triggered if the register offset is 0.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output
when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if
the operation get_bias() is implemented but the pin is not handled by
the get_bias() implementation. In that case the output will state that
"input bias disabled" indicating that this pin has bias control
support.
Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either
supports SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also
solves the issue where SoC specific implementations print error messages
if their particular implementation of {set,get}_bias() is called with a
pin it does not know about.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Only the DU parallel RGB output signals are included, HDMI and TCON pins
will be added in separate groups. Based on a similar patch from Laurent
Pinchart for the r8a7795 PFC driver.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The pin controller found in the Allwinner SoCs has support for interrupts
debouncing.
However, this is not done per-pin, preventing us from using the generic
pinconf binding for that, but per irq bank, which, depending on the SoC,
ranges from one to five.
Introduce a device-wide property to deal with this using a microsecond
resolution. We can re-use the per-pin input-debounce property for that, so
let's do it!
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The sunxi_pconf_reg helper introduced in the last patch gives us the
chance to rework sunxi_pconf_group_set to have it match the structure
of sunxi_pconf_(group_)get and make it easier to understand.
For each config to set, it:
1. checks if the parameter is supported.
2. checks if the argument is within limits.
3. converts argument to the register value.
4. writes to the register with spinlock held.
As a result the function now blocks unsupported config parameters,
instead of silently ignoring them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The sunxi pinctrl driver only caches whatever pinconf setting was last
set on a given pingroup. This is not particularly helpful, nor is it
correct.
Fix this by actually reading the hardware registers and returning
the correct results or error codes. Also filter out unsupported
pinconf settings. Since this driver has a peculiar setup of 1 pin
per group, we can support both pin and pingroup pinconf setting
read back with the same code. The sunxi_pconf_reg helper and code
structure is inspired by pinctrl-msm.
With this done we can also claim to support generic pinconf, by
setting .is_generic = true in pinconf_ops.
Also remove the cached config value. The behavior of this was never
correct, as it only cached 1 setting instead of all of them. Since
we can now read back settings directly from the hardware, it is no
longer required.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
According to pinconf-generic.h, the argument for
PIN_CONFIG_BIAS_PULL_{DOWN,UP} is non-zero if the bias is enabled
with a pull up/down resistor, zero if it is directly connected
to VDD or ground.
Since Allwinner hardware uses a weak pull resistor internally,
the argument should be 1.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In the recently refactored sunxi pinctrl library, we are only allocating
one set of pin configs for each pinmux setting node. When the pinctrl_map
structure is freed, the pin configs should also be freed. However the
code assumed the first map would contain the configs, which actually
never happens, as the mux function map gets added first.
The proper way to do this is to look through all the maps and free the
first one whose type is actually PIN_MAP_TYPE_CONFIGS_GROUP.
Also slightly expand the comment explaining this.
Fixes: f233dbca62 ("pinctrl: sunxi: Rework the pin config building code")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
None of the Kconfigs for any of these drivers are tristate, meaning
that they currently are not being built as a module by anyone.
Lets remove the modular code that is essentially orphaned, so that
when reading the drivers there is no doubt they are builtin-only. All
drivers get the exact same change, so they are handled in batch.
Changes are (1) use builtin_platform_driver, (2) use init.h header
(3) delete module_exit related code, (4) delete MODULE_DEVICE_TABLE,
(5) delete MODULE_LICENCE/MODULE_AUTHOR and associated tags and (6)
drop ".remove" code and prevent sysfs unbind attempts to call ".remove".
Once this is done, the shared remove function in wmt.[ch] is no longer
used and hence it is removed as well.
Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.
Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
We also delete the MODULE_LICENSE etc. tags since all that information
is already contained at the top of each file in the comments.
Cc: Tony Prisk <linux@prisktech.co.nz>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need
to support the multiple memory map because the registers of GPFx are located
in the different domain.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch supports the multiple IORESOURCE_MEM resources for one pin-bank.
In the pre-existing Exynos series, the registers of the gpio bank are included
in the one memory map. But, some gpio bank need to support the one more memory
map (IORESOURCE_MEM) because the registers of gpio bank are separated into
the different memory map.
For example,
The both ALIVE and IMEM domain have the different memory base address.
The GFP[1-5] of exynos5433 are composed as following:
- ALIVE domain : WEINT_* registers
- IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-gpio@vger.kernel.org
Suggested-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When dynamically unloading overlays, it is important that freed pins are
restored to being inputs to prevent functions from being enabled in
multiple places at once.
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Contrary to the documentation, the BCM2835 GPIO controller actually
has four interrupt lines - one each for the three IRQ groups and one
common. Confusingly, the GPIO interrupt groups don't correspond
directly with the GPIO control banks. Instead, GPIOs 0-27 generate IRQ
GPIO0, 28-45 IRQ GPIO1 and 46-53 IRQ GPIO2.
Awkwardly, the GPIOs for IRQ GPIO1 straddle two 32-entry GPIO banks,
so split out a function to process the interrupts for a single GPIO
bank.
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pcs_parse_bits_in_pinctrl_entry function should search
for the "pinctrl-single,bits" and not "pinctrl-single,pins"
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl_count_index_with_args returns -ENOENT not
-EINVAL. The return check would pass, and we would
try to kzalloc with a negative error size throwing
a warning.
Instead of checking for -EINVAL specifically, lets
check for any error and avoid negative size allocations.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
for_each_property_of_node(pins, pp) checks that pp is not NULL.
So there is no need to check it inside the loop.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
function is defined as unsigned int.
So we need %u to print it.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- I2C and DRIF pin groups for R-Car M3-W,
- Bug fixes for SDHI2/3 on R-Car M3-W.
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Merge tag 'sh-pfc-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.10
- I2C and DRIF pin groups for R-Car M3-W,
- Bug fixes for SDHI2/3 on R-Car M3-W.
Include <linux/gpio/driver.h> rather than <linux/gpio.h>
Drop <linux/pinctrl/machine.h>.
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Althought the function passed as a "handler" during GPIO chip
instantiation is not going to ever be called, specifying handle_edge_irq
there makes for a rather confusing read, both because no "ack" callback
in specified for irqchip and because there's no acking action is
necessary.
Specify handle_bad_irq instead a make a note of the situation. This
commit should be a no-op behaviour wise.
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Make use of for_each_set_bit macro and reduce boilerplate code.
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Move actual code that configures oscio pin into a separate function and
use it instead of calling sx150x_gpio_set to avoid calling
sx150x_pin_is_oscio twice and correctly propagte error code in
sx150x_gpio_direction_output.
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gpiochip and irqchip aspects of this driver do not access any shared
registers on the chip itself and atomicity of various regmap operations
is ensured by that API's implementation, so there doesn't seem to be a
reason to hold the lock in as many places as it is held now.
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The difference between 8 and 16 pin GPIO expanders can be accomodated by
the means of regmap API without resorting to using driver-specific
read/write accessors. This change, IMHO, brings the following benefits:
- Replaces driver's idiosyncratic way of dealing with
mult-register fields with regmap API, which, hopefuly,
makes the code a bit easier for a new reader to understand
- Removes various multi-read for-loop register read logic
from various places in the code and puts it in a signle
place
- Removes ad-hoc IRQ register caching code in
sx150x_irq_bus_sync_unlock, since that functionality is
provided by regmap
Besided aforementioned benefits this change also implements necessary
RegSense byte swap necessary for SX1503 and SX1506 variants of the chip.
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
For Sx1504/5/6 only SX1506 has RegAdvanced, so put some code in place to
account for that.
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Move the code configuring explicit IRQ acking into a standalone function
to declutter sx150x_init_hw a bit and make that code somewhat less
repetitious.
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
According to the datasheet for SX1504/5/6, RegAdvanced's
"Autoclear NINT" bit that turns the feature when set and disables it
when cleared, so writing 0x04 to the register will have the opposite
from desirable effect.
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add proper device specific information to of_device_id table of the
driver and add code to match against and fetch said data from it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix off-by-one (row and/or register) errors in links to Peripheral
Function Select Register bitfields from GPIO/Peripheral Function Select
Register 4 macros for SDHI2 and SDHI3 pins.
Based on rev. 0.52E of the R-Car Gen3 User's Manual.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
If a pin depending on bit 6 in SCU90 is requested for GPIO, the export
will succeed but changes to the GPIO's value will not be accepted by the
hardware. This is because the pinmux driver has misconfigured the SCU by
writing 1 to the reserved bit.
The description of SCU90[6] from the datasheet is 'Reserved, must keep
at value ”0”'. The fix is to switch pinmux from the bit-flipping macro
to explicitly configuring the .enable and .disable values to zero.
The patch has been tested on an AST2500 EVB.
Fixes: 56e57cb6c0 (pinctrl: Add pinctrl-aspeed-g5 driver)
Reported-by: Uma Yadlapati <yadlapat@us.ibm.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Initial pinctrl driver for QCOM msm8994 platforms.
In order to continue the initial board support for QCOM msm8994/msm8992
presented in patches from Jeremy McNicoll <jeremymc@redhat.com>, let's put
a proper pinctrl driver in place.
Currently, the DT for these platforms uses the msm8x74 pinctrl driver to
enable basic UART. Beyond the first few pins the rest are different enough
to justify it's own driver.
Note: This driver is also used by QCOM's msm8992 platform as it's TLM block
is the same.
- Initial formatting and style was taken from the msm8x74 pinctrl driver
added by Björn Andersson <bjorn.andersson@linaro.org>
- Data was then adjusted per QCOM MSM8994v2 documentation for Top Level
Multiplexing
- Bindings documentation was based on qcom,msm8996-pinctrl.txt by
Joonwoo Park <joonwoop@codeaurora.org> and then modified for msm8994
content
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Tested-by: Jeremy McNicoll <jeremymc@redhat.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
None of the Kconfigs for any of these drivers are tristate,
meaning that they currently are not being built as a module by anyone.
Lets remove the modular code that is essentially orphaned, so that
when reading the drivers there is no doubt they are builtin-only. All
drivers get essentially the same change, so they are handled in batch.
Changes are (1) use builtin_platform_driver, (2) use init.h header
(3) delete module_exit related code, (4) delete MODULE_DEVICE_TABLE,
and (5) delete MODULE_LICENCE/MODULE_AUTHOR and associated tags.
Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.
Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
We do delete the MODULE_LICENSE etc. tags since all that information
is already contained at the top of each file in the comments.
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Hongzhou Yang <hongzhou.yang@mediatek.com>
Cc: Fabian Frederick <fabf@skynet.be>
Cc: Maxime Coquelin <maxime.coquelin@st.com>
Cc: Vishnu Patekar <vishnupatekar0510@gmail.com>
Cc: Mylene Josserand <mylene.josserand@free-electrons.com>
Cc: linux-gpio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for the Amlogic Meson GXL SoC, this is a partially complete
definition only based on the Amlogic Vendor tree.
This definition differs a lot from the GXBB and needs a separate entry.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We can now use generic parser and keep things compatible with the
old binding.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We can now use generic parser. To support the legacy binding without
#pinctrl-cells, add pcs_quirk_missing_pinctrl_cells() and warn about
missing #pinctrl-cells.
Let's also update the documentation for struct pcs_soc_data while at it
as that seems to be out of date.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When the system is suspended to S3 the BIOS might re-initialize certain
GPIO pins back to their original state or it may re-program interrupt mask
of others. For example Acer TravelMate B116-M had BIOS bug where certain
GPIO pin (MF_ISH_GPIO_5) was programmed to trigger on high level, and the
pin state was high once the BIOS gave control to the OS on resume.
This triggers lots of messages like:
irq 117, desc: ffff88017a61e600, depth: 1, count: 0, unhandled: 0
->handle_irq(): ffffffff8109b613, handle_bad_irq+0x0/0x1e0
->irq_data.chip(): ffffffffa0020180, chv_pinctrl_exit+0x2d84/0x12 [pinctrl_cherryview]
->action(): (null)
IRQ_NOPROBE set
We reset the mask back to known state in chv_pinctrl_resume() but that is
called only after device interrupts have already been enabled.
Now, this particular issue was fixed by upgrading the BIOS to the latest
(v1.23) but not everybody upgrades their BIOSes so we fix it up in the
driver as well.
Prevent the possible interrupt storm by moving suspend and resume hooks to
be called at _noirq time instead. Since device interrupts are still
disabled we can restore the mask back to known state before interrupt storm
happens.
Cc: stable@vger.kernel.org
Reported-by: Christian Steiner <christian.steiner@outlook.de>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If async suspend is enabled, the driver may access registers concurrently
with another instance which may fail because of the bug in Cherryview GPIO
hardware. Prevent this by taking the shared lock while accessing the
hardware in suspend and resume hooks.
Cc: stable@vger.kernel.org
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since the BCM2835 datasheet doesn't exactly specify the set-up time for
the GPIO Pull-up/down Clock Registers there was an assumption of 150 cycles
at a clock rate of 1 MHz. During a discussion [1] in the Raspberry Pi forum
it turns out that clock rate refers to the VPU which has a rate of 250 MHz.
So we can reduce the delay to a sensible value and update the comment above.
I tested this optimization with a Raspberry Pi B and a multimeter.
[1] - https://www.raspberrypi.org/forums/viewtopic.php?f=72&t=163352
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Printing the prefix does not provide any additional information. In
addition this makes the output look more consistent with pinctrl-intel.c.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The hardware supports a 16 and 8 bit wide NAND bus, let users pick
either.
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Group index is incremented on every new group parsed. Since the
field is part of struct imx_pinctrl_soc_info, which is typically
a global variable passed by the individual pinctrl-imx.c based
driver, it does not get cleared automatically when re-probing the
driver. This lead imx_pinctrl_parse_functions passing a group
pointer which is outside of the allocated group space on second
probe and onwards. Typically this ended up in a NULL pointer
dereference when accessing the name field like this:
Unable to handle kernel NULL pointer dereference at virtual address 00000000
...
PC is at strcmp+0x18/0x44
LR is at imx_dt_node_to_map+0xc4/0x290
Avoid this by setting group_index to 0 on probe.
This has been observed when using DEBUG_TEST_DRIVER_REMOVE.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch allows to probe stm32 pinctrl driver even if no interrupt
controller is defined to manage gpio irqs.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Thanks to 332e99d5ae which now alerts of default
trigger usage when configuring interrupts.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since commit 44a7185c2a ("of/platform: Add common method to populate
default bus"), ARM64 platform devices are populated at the
arch_initcall_sync level; as a result, the platform_driver_probe calls
in both the iProc and NSP GPIO drivers fail with -ENODEV since by that
time the platform device was not yet registered.
Replace platform_driver_probe with platform_driver_register, that allow
the device to be register later
Fixes: 44a7185c2a ("of/platform: Add common method to populate default bus")
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Tested-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for pin output control through the pinctrl config:
- support enabling/disabling output on a given pin
- support output level setting (high or low)
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Even though the our binding had the assumption that the allwinner,pull and
allwinner,drive properties were optional, the code never took that into
account.
Fix that.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pin config get() and set() handlers for pin groups were previously not
implemented by this driver. The pin_config_group_set() is particularly useful
for applying a common config setting to all pins in a specified group with a
single call, without the caller needing to reference each individual pin by
name.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
During pinmux registration, pinmux table is parsed from DT
for making the pinmux table configuration of pins.
Parse the only those node whose status is not disabled.
This will help on reusing the pin configuration table across
platform and disabling the node by status property if that node
is not needed on given platform.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Drivers using pinconf_generic_params tables cannot be built with
CONFIG_OF disabled:
drivers/pinctrl/pinctrl-max77620.c:53:44: error: array type has incomplete element type ‘struct pinconf_generic_params’
drivers/pinctrl/pinctrl-max77620.c:55:3: error: field name not in record or union initializer
drivers/pinctrl/pinctrl-max77620.c:55:3: note: (near initialization for ‘max77620_cfg_params’)
drivers/pinctrl/pinctrl-max77620.c:56:3: error: field name not in record or union initializer
This adds a dependency for max77620 to disallow that configuration.
Alternatively, we could rework the pinctrl infrastructure to make the
configuration valid for compile-testing.
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Lee Jones <lee.jones@linaro.org>
Fixes: 453943dc8f45 ("mfd: Enable compile testing for max77620 and max77686")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This is left over from initial experiments with more properties.
It's only used in one place, so let's just get rid of it to make
the code more readable.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
>From tony Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Tue, 25 Oct 2016 08:33:34 -0700
Subject: [PATCHv2] pinctrl: single: Drop custom names
We no longer need to allocate custom names as those are dynamically
generated in pinctrl_register_one_pin() if no name is passed to
pinctrl_register_pins().
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since the I2C sx150x GPIO expander driver uses platform_data to manage
the pins configurations, rewrite the driver as a pinctrl driver using
pinconf to get/set pin configurations from DT or debugfs.
The pinctrl driver is functionnally equivalent as the gpio-only driver
and can use DT for pinconf. The platform_data confirmation is dropped.
This patchset removed the gpio-only driver and selects the Pinctrl driver
config instead. This patchset also migrates the gpio dt-bindings to pinctrl
and add the pinctrl optional properties.
The driver was tested with a SX1509 device on a BeagleBone black with
interrupt support and on an X86_64 machine over an I2C to USB converter.
This is a fixed version that builds and runs on non-OF platforms and on
arm based OF. The GPIO version is removed and the bindings are also moved
to the pinctrl bindings.
Changes since v2
- rebased on v4.9-rc1
- removed MODULE_DEVICE_TABLE as in upstream bb411e771b
("gpio: sx150x: fix implicit assumption module.h is present")
Changes since v1
- Fix Kconfig descriptions on pinctrl and gpio
- Fix Kconfig dependency
- Remove oscio support for non-789 devices
- correct typo in dt bindings
- remove probe reset for non-789 devices
Changes since RFC
- Put #ifdef CONFIG_OF/CONFIG_OF_GPIO to remove OF code for non-of platforms
- No more rely on OF_GPIO config
- Moved and enhanced bindings to pinctrl bindings
- Removed gpio-sx150x.c
- Temporary select PINCTRL_SX150X when GPIO_SX150X
- Temporary mark GPIO_SX150X as deprecated
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Peter Rosin <peda@axentia.se>
Acked-by: Rob Herring <robh@kernel.org>
ested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Our bindings are mostly irrelevant now that we have generic pinctrl
bindings that cover exactly the same uses cases.
Add support for the new ones, and obviously keep our old binding support in
order to keep the ABI stable.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for the Oxford Semiconductor OX820 which is similar as OX810 but
has 50 pins and two registers banks to setup alternate functions.
Add specific pins, groups and functions structures.
Add DT match data to select corresponding support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add refactoring to move ox810se specific functions into specific ops structures
an add support for the dt match data to get soc specific structures.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
So far, putting NO_PULL in allwinner,pull was ignored, behaving like if
that property was not there at all.
Obviously, this is not the right thing to do, and in that case, we really
need to just disable the bias.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since we have some bindings header for our hardcoded flags, let's use them
when we can.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In order to support more easily the generic pinctrl properties, rework the
pinctrl maps configuration and split it into several sub-functions.
One of the side-effects from that rework is that we only parse the pin
configuration once, since it's going to be common to every pin, instead of
having to parsing once for each pin.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dell XPS 13 (and maybe some others) uses a GPIO (CPU_GP_1) during suspend
to explicitly disable USB touchscreen interrupt. This is done to prevent
situation where the lid is closed the touchscreen is left functional.
The pinctrl driver (wrongly) assumes it owns all pins which are owned by
host and not locked down. It is perfectly fine for BIOS to use those pins
as it is also considered as host in this context.
What happens is that when the lid of Dell XPS 13 is closed, the BIOS
configures CPU_GP_1 low disabling the touchscreen interrupt. During resume
we restore all host owned pins to the known state which includes CPU_GP_1
and this overwrites what the BIOS has programmed there causing the
touchscreen to fail as no interrupts are reaching the CPU anymore.
Fix this by restoring only those pins we know are explicitly requested by
the kernel one way or other.
Cc: stable@vger.kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=176361
Reported-by: AceLan Kao <acelan.kao@canonical.com>
Tested-by: AceLan Kao <acelan.kao@canonical.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Initialize the spinlock before using it.
INFO: trying to register non-static key.
the code is fine but needs lockdep annotation.
turning off the locking correctness validator.
CPU: 2 PID: 1 Comm: swapper/0 Not tainted 4.8.0-dwc-bisect #4
Hardware name: Intel Corp. VALLEYVIEW C0 PLATFORM/BYT-T FFD8, BIOS BLAKFF81.X64.0088.R10.1403240443 FFD8_X64_R_2014_13_1_00 03/24/2014
0000000000000000 ffff8800788ff770 ffffffff8133d597 0000000000000000
0000000000000000 ffff8800788ff7e0 ffffffff810cfb9e 0000000000000002
ffff8800788ff7d0 ffffffff8205b600 0000000000000002 ffff8800788ff7f0
Call Trace:
[<ffffffff8133d597>] dump_stack+0x67/0x90
[<ffffffff810cfb9e>] register_lock_class+0x52e/0x540
[<ffffffff810d2081>] __lock_acquire+0x81/0x16b0
[<ffffffff810cede1>] ? save_trace+0x41/0xd0
[<ffffffff810d33b2>] ? __lock_acquire+0x13b2/0x16b0
[<ffffffff810cf05a>] ? __lock_is_held+0x4a/0x70
[<ffffffff810d3b1a>] lock_acquire+0xba/0x220
[<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
[<ffffffff81631567>] _raw_spin_lock_irqsave+0x47/0x60
[<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
[<ffffffff8136f1fe>] byt_gpio_get_direction+0x3e/0x80
[<ffffffff813740a9>] gpiochip_add_data+0x319/0x7d0
[<ffffffff81631723>] ? _raw_spin_unlock_irqrestore+0x43/0x70
[<ffffffff8136fe3b>] byt_pinctrl_probe+0x2fb/0x620
[<ffffffff8142fb0c>] platform_drv_probe+0x3c/0xa0
...
Based on the diff it looks like the problem was introduced in
commit 71e6ca61e8 ("pinctrl: baytrail: Register pin control handling")
but I wasn't able to verify that empirically as the parent commit
just oopsed when I tried to boot it.
Cc: Cristina Ciocan <cristina.ciocan@intel.com>
Cc: stable@vger.kernel.org
Fixes: 71e6ca61e8 ("pinctrl: baytrail: Register pin control handling")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The SPI1 function was associated with the wrong pins: The functions that
those pins provide is either an SPI debug or passthrough function
coupled to SPI1. Make the SPI1 mux function configure the relevant pins
and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins
that were already defined.
The notation used in the datasheet's multi-function pin table for the SoC is
often creative: in this case the SYS* signals are enabled by a single bit,
which is nothing unusual on its own, but in this case the bit was also
participating in a multi-bit bitfield and therefore represented multiple
functions. This fact was overlooked in the original patch.
Fixes: 56e57cb6c0 (pinctrl: Add pinctrl-aspeed-g5 driver)
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This prevented C20 from successfully being muxed as GPIO.
Fixes: 56e57cb6c0 (pinctrl: Add pinctrl-aspeed-g5 driver)
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes simple typos in the initial commit. There is no behavioural
change.
Fixes: 56e57cb6c0 (pinctrl: Add pinctrl-aspeed-g5 driver)
Reported-by: Xo Wang <xow@google.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Consider a scenario with one pin P that has two signals A and B, where A
is defined to be higher priority than B: That is, if the mux IP is in a
state that would consider both A and B to be active on P, then A will be
the active signal.
To instead configure B as the active signal we must configure the mux so
that A is inactive. The mux state for signals can be described by
logical operations on one or more bits from one or more registers (a
"signal expression"), which in some cases leads to aliased mux states for
a particular signal. Further, signals described by multi-bit bitfields
often do not only need to record the states that would make them active
(the "enable" expressions), but also the states that makes them inactive
(the "disable" expressions). All of this combined leads to four possible
states for a signal:
1. A signal is active with respect to an "enable" expression
2. A signal is not active with respect to an "enable" expression
3. A signal is inactive with respect to a "disable" expression
4. A signal is not inactive with respect to a "disable" expression
In the case of P, if we are looking to activate B without explicitly
having configured A it's enough to consider A inactive if all of A's
"enable" signal expressions evaluate to "not active". If any evaluate to
"active" then the corresponding "disable" states must be applied so it
becomes inactive.
For example, on the AST2400 the pins composing GPIO bank H provide
signals ROMD8 through ROMD15 (high priority) and those for UART6 (low
priority). The mux states for ROMD8 through ROMD15 are aliased, i.e.
there are two mux states that result in the respective signals being
configured:
A. SCU90[6]=1
B. Strap[4,1:0]=100
Further, the second mux state is a 3-bit bitfield that explicitly
defines the enabled state but the disabled state is implicit, i.e. if
Strap[4,1:0] is not exactly "100" then ROMD8 through ROMD15 are not
considered active. This requires the mux function evaluation logic to
use approach 2. above, however the existing code was using approach 3.
The problem was brought to light on the Palmetto machines where the
strap register value is 0x120ce416, and prevented GPIO requests in bank
H from succeeding despite the hardware being in a position to allow
them.
Fixes: 318398c09a8d ("pinctrl: Add core pinctrl support for Aspeed SoCs")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Also delete (unused) private enum from driver.
The pull defines can be used instead if needed.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Driver updates for ARM SoCs, including a couple of newly added drivers:
- The Qualcomm external bus interface 2 (EBI2), used in some of their
mobile phone chips for connecting flash memory, LCD displays or
other peripherals
- Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for the
EFUSE based on that firmware interface.
- Perf support for the AppliedMicro X-Gene performance monitor unit
- Reset driver for STMicroelectronics STM32
- Reset driver for SocioNext UniPhier SoCs
Aside from these, there are minor updates to SoC-specific bus,
clocksource, firmware, pinctrl, reset, rtc and pmic drivers.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"Driver updates for ARM SoCs, including a couple of newly added
drivers:
- The Qualcomm external bus interface 2 (EBI2), used in some of their
mobile phone chips for connecting flash memory, LCD displays or
other peripherals
- Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for
the EFUSE based on that firmware interface.
- Perf support for the AppliedMicro X-Gene performance monitor unit
- Reset driver for STMicroelectronics STM32
- Reset driver for SocioNext UniPhier SoCs
Aside from these, there are minor updates to SoC-specific bus,
clocksource, firmware, pinctrl, reset, rtc and pmic drivers"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits)
bus: qcom-ebi2: depend on HAS_IOMEM
pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181
clk: mvebu: Add clk support for the orion5x SoC mv88f5181
dt-bindings: EXYNOS: Add Exynos5433 PMU compatible
clocksource: exynos_mct: Add the support for ARM64
perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver
Documentation: Add documentation for APM X-Gene SoC PMU DTS binding
MAINTAINERS: Add entry for APM X-Gene SoC PMU driver
bus: qcom: add EBI2 driver
bus: qcom: add EBI2 device tree bindings
rtc: rtc-pm8xxx: Add support for pm8018 rtc
nvmem: amlogic: Add Amlogic Meson EFUSE driver
firmware: Amlogic: Add secure monitor driver
soc: qcom: smd: Reset rx tail rather than tx
memory: atmel-sdramc: fix a possible NULL dereference
reset: hi6220: allow to compile test driver on other architectures
reset: zynq: add driver Kconfig option
reset: sunxi: add driver Kconfig option
reset: stm32: add driver Kconfig option
reset: socfpga: add driver Kconfig option
...
Subsystem improvements:
- Do away with the last users of the obsolete Kconfig options
ARCH_REQUIRE_GPIOLIB and ARCH_WANT_OPTIONAL_GPIOLIB (the latter
always sounded like an item on a wishlist to Santa Claus to
me). We can now select GPIOLIB and be done with it, for all
archs. After some struggle it even work on UM. Not that it has
GPIO, but if it wants to, it can select the library.
- Continued efforts to make drivers properly either tristate or
bool.
- Introduce a warning for drivers assigning default triggers to
their irqchip lines when probed from device tree, so we find and
fix these ambigous drivers. It is agreed that in the OF config
path, the device tree defines trigger characteristics.
- The same warning, mutatis mutandis, for ACPI-probed GPIO
irqchips.
- We introduce the ability to mark certain IRQ lines as "unusable"
as they can be taken by BIOS/firmware, unrouted in silicon and
generally nasty if you use them, and such things. This is
put to good use in the STMPE driver and also in the Cherryview
pin control driver.
- A new "mockup" virtual GPIO device that can be used for testing.
The plan is to add unit tests under tools/* for exercising this
device and verify that the kernel code paths are working as they
should.
- Make memory-mapped I/O-drivers depend on HAS_IOMEM. This was
implicit all the time, but when people started building UM
with allyesconfig or allmodconfig it exploded in their face.
- Move some stray bits of device tree and ACPI HW description
callbacks down into their respective implementation silo. These
were causing issues when compiling on !HAS_IOMEM as well, so
now eventually UM compiles the GPIOLIB library if it wants to.
New drivers:
- New driver for the Aspeed GPIO front-end companion to the
pin controller merged through the pin control tree.
- New driver for the LP873x PMIC GPIO portions.
- New driver for Technologic Systems' I2C FPGA GPIO such as
TS4900, TS-7970, TS-7990 and TS-4100.
- New driver for the Broadcom BCM63xx series including BCM6338
and BCM6345.
- New driver for the Intel WhiskeyCove PMIC GPIO.
- New driver for the Allwinner AXP209 PMIC GPIO portions.
- New driver for Diamond Systems 48 line GPIO-MM, another of
these port-mapped I/O expansion cards.
- Support the STMicroelectronics STMPE1600 variant in the STMPE
driver.
Driver improvements:
- The STMPE driver now supports rising/falling edge detection
properly for IRQs.
- The PCA954x will now fetch and enable its VCC regulator properly.
- Major rework of the PCA953x driver with the goal of eventually
switching it over to use regmap and thus modernize it even more.
- Switch the IOP driver to use the generic MMIO GPIO library.
- Move the ages old HTC EGPIO (extended GPIO) GPIO expander driver
over to this subsystem from MFD, achieveing some separation of
concerns.
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Merge tag 'gpio-v4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v4.9 series:
Subsystem improvements:
- do away with the last users of the obsolete Kconfig options
ARCH_REQUIRE_GPIOLIB and ARCH_WANT_OPTIONAL_GPIOLIB (the latter
always sounded like an item on a wishlist to Santa Claus to me). We
can now select GPIOLIB and be done with it, for all archs. After
some struggle it even work on UM. Not that it has GPIO, but if it
wants to, it can select the library.
- continued efforts to make drivers properly either tristate or bool.
- introduce a warning for drivers assigning default triggers to their
irqchip lines when probed from device tree, so we find and fix
these ambigous drivers. It is agreed that in the OF config path,
the device tree defines trigger characteristics.
- the same warning, mutatis mutandis, for ACPI-probed GPIO irqchips.
- we introduce the ability to mark certain IRQ lines as "unusable" as
they can be taken by BIOS/firmware, unrouted in silicon and
generally nasty if you use them, and such things. This is put to
good use in the STMPE driver and also in the Cherryview pin control
driver.
- a new "mockup" virtual GPIO device that can be used for testing.
The plan is to add unit tests under tools/* for exercising this
device and verify that the kernel code paths are working as they
should.
- make memory-mapped I/O-drivers depend on HAS_IOMEM. This was
implicit all the time, but when people started building UM with
allyesconfig or allmodconfig it exploded in their face.
- move some stray bits of device tree and ACPI HW description
callbacks down into their respective implementation silo. These
were causing issues when compiling on !HAS_IOMEM as well, so now
eventually UM compiles the GPIOLIB library if it wants to.
New drivers:
- new driver for the Aspeed GPIO front-end companion to the pin
controller merged through the pin control tree.
- new driver for the LP873x PMIC GPIO portions.
- new driver for Technologic Systems' I2C FPGA GPIO such as TS4900,
TS-7970, TS-7990 and TS-4100.
- new driver for the Broadcom BCM63xx series including BCM6338 and
BCM6345.
- new driver for the Intel WhiskeyCove PMIC GPIO.
- new driver for the Allwinner AXP209 PMIC GPIO portions.
- new driver for Diamond Systems 48 line GPIO-MM, another of these
port-mapped I/O expansion cards.
- support the STMicroelectronics STMPE1600 variant in the STMPE
driver.
Driver improvements:
- the STMPE driver now supports rising/falling edge detection
properly for IRQs.
- the PCA954x will now fetch and enable its VCC regulator properly.
- major rework of the PCA953x driver with the goal of eventually
switching it over to use regmap and thus modernize it even more.
- switch the IOP driver to use the generic MMIO GPIO library.
- move the ages old HTC EGPIO (extended GPIO) GPIO expander driver
over to this subsystem from MFD, achieveing some separation of
concerns"
* tag 'gpio-v4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (81 commits)
gpio: add missing static inline
gpio: OF: localize some gpiochip init functions
gpio: acpi: separation of concerns
gpio: OF: separation of concerns
gpio: make memory-mapped drivers depend on HAS_IOMEM
gpio: stmpe: use BIT() macro
gpio: stmpe: forbid unused lines to be mapped as IRQs
mfd/gpio: Move HTC GPIO driver to GPIO subsystem
gpio: MAINTAINERS: Add an entry for GPIO mockup driver
gpio/mockup: add virtual gpio device
gpio: Added zynq specific check for special pins on bank zero
gpio: axp209: Implement get_direction
gpio: aspeed: remove redundant return value check
gpio: loongson1: remove redundant return value check
ARM: omap2: fix missing include
gpio: tc3589x: fix up complaints on unsigned
gpio: tc3589x: add .get_direction() and small cleanup
gpio: f7188x: use gpiochip_get_data instead of container_of
gpio: tps65218: use devm_gpiochip_add_data() for gpio registration
gpio: aspeed: fix return value check in aspeed_gpio_probe()
...
The following commit introduced a regression by not properly masking the
calculated value.
Fixes: 47a01ee9a6 ("pinctrl: qcom: Clear all function selection bits")
Signed-off-by: John Crispin <john@phrozen.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The generic GPIO library directly implement code for acpi_find_gpio()
which is only used with CONFIG_ACPI. This was probably done because
OF did the same thing, but I removed that so remove this too.
Rename the internal acpi_find_gpio() in gpiolib-acpi.c to
acpi_populate_gpio_lookup() which seems to be more appropriate anyway
so as to avoid a namespace clash with the same function.
Make the stub return -ENOENT rather than -ENOSYS (as that is for
syscalls!).
For some reason the sunxi pin control driver was including the private
gpiolib header, it works just fine without it so remove that oneliner.
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On some Intel BXT platform, wake-up from suspend-to-idle on pressing
power-button is not working. Its noticed that gpio-keys driver marking the
second level IRQ/power-button as wake capable but Intel pintctrl
driver is missing to mark GPIO chip/controller IRQ which first level IRQ
as wake cable if its GPIO pin IRQ is wakeble. So, though the first level
IRQ gets generated on power-button press, since it is not marked as
wake capable resume/wake-up flow is not happening.
Intel pintctrl/GPIO driver need to mark GPIO chip/controller IRQ (first
level IRQ) as wake capable iff GPIO pin's IRQ (second level IRQ) is marked
as wake cable.
Changes in v2:
- Add missing irq initialisation.
Signed-off-by: Nilesh Bacchewar <nilesh.bacchewar@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This simplifies the error handling and allows us to drop the whole
chv_pinctrl_remove() function.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It turns out that for north and southwest communities, they can only
generate GPIO interrupts for lower 8 interrupts (IntSel value). The upper
part (8-15) can only generate GPEs (General Purpose Events).
Now the reason why EC events such as pressing hotkeys does not work if we
mask all the interrupts is that in order to generate either interrupts or
GPEs the INTMASK register must have that particular interrupt unmasked. In
case of GPEs the CPU does not trigger normal interrupt (and thus the GPIO
driver does not see it) but instead it causes SCI (System Control
Interrupt) to be triggered with the GPE in question set.
To make this all work as expected we only add those GPIOs to the IRQ domain
that can actually generate interrupts (IntSel value 0-7) and skip others.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add pinctrl and clk support for the Orion5x SoC mv88f5181 variant
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Merge tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu into next/drivers
Pull "mvebu drivers for 4.9 (part 1)" from Gregory CLEMENT:
- Add pinctrl and clk support for the Orion5x SoC mv88f5181 variant
* tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu:
pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181
clk: mvebu: Add clk support for the orion5x SoC mv88f5181
As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.
[gregory.clement@free-electrons.com: fix commit title]
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
There is no point in adding any default trigger for these
GPIO interrupts: the device tree should contain all trigger
information and the platforms using the driver boots
exclusively from device tree.
Also the boot log is nagging me to fix this:
[ 0.771057] ------------[ cut here ]------------
[ 0.775695] WARNING: CPU: 0 PID: 1 at
../drivers/gpio/gpiolib.c:1622 _gpiochip_irqchip_add+0x138/0x160
[ 0.785034] /soc/gpio@8012e000: Ignoring 2 default trigger
(...)
[ 0.942962] gpio 8012e000.gpio: at address e08f8000
(etc ad nauseam)
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
STiH415/6 SoC support is being removed from the kernel.
This patch updates the ST pinctrl driver and removes
references to these obsolete platforms. As some structures
referenced by STiH407 based configuration were shared with
STiH416 we update these names to match the remaining
supported platform.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Cc: <linus.walleij@linaro.org>
Cc: <linux-gpio@vger.kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The newly added irqchip support for the stm32 pinctrl driver uses
hierarchical IRQ domains as provided by the NVIC primary irqchip.
This works great for any configuration that may be relevant on
stm32, but when doing compile-testing (randconfig), we can
enable it without NVIC or any other primary irqchip that
enables IRQ_DOMAIN_HIERARCHY:
drivers/pinctrl/stm32/pinctrl-stm32.c:212:13: error: 'irq_chip_eoi_parent' undeclared here (not in a function)
drivers/pinctrl/stm32/pinctrl-stm32.c:213:20: error: 'irq_chip_mask_parent' undeclared here (not in a function)
drivers/pinctrl/stm32/pinctrl-stm32.c:214:20: error: 'irq_chip_unmask_parent' undeclared here (not in a function)
drivers/pinctrl/stm32/pinctrl-stm32.c:215:20: error: 'irq_chip_set_type_parent' undeclared here (not in a function)
This adds a Kconfig dependency to limit compile-testing to
configurations that have IRQ_DOMAIN_HIERARCHY already enabled.
It's not obvious whether we should use 'depends on' or 'select'
here, I think either one works, with 'depends on' being more
intuitive, while 'select' would be less likely to cause dependency
loops.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 0eb9f68333 ("pinctrl: Add IRQ support to STM32 gpios")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Return pinconf with arguments in packed format,
- MSIOF and QSPI pin groups on R-Car V2H,
- Voltage switching for SDHI on R-Car M2-W, E2, and M3-W.
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Merge tag 'sh-pfc-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.9 (take three)
- Return pinconf with arguments in packed format,
- MSIOF and QSPI pin groups on R-Car V2H,
- Voltage switching for SDHI on R-Car M2-W, E2, and M3-W.
All the SHDIs can operate with either 3.3V or 1.8V signals, depending
on negotiation with the card.
Based on work by Wolfram Sang for the r8a7790.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
All the SHDIs can operate with either 3.3V or 1.8V signals, depending
on negotiation with the card.
Based on work by Wolfram Sang for the r8a7790.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This follows the style of existing PORT_GP_X macros and
will be used by a follow-up patch for the r8a7791 SoC.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This adds the SDIO interrupt pin which can be used by sd_emmc_a.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
Fixes: 29885a6565 ("pinctrl: meson-gxbb: add the pins for the
SDIO/sd_emmc_a controller")
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The newly added aspeed driver tries to check for a negative return
value from a pinctrl function, but stores the intermediate value in
a 'bool' variable, which cannot work:
drivers/pinctrl/aspeed/pinctrl-aspeed.c: In function 'aspeed_sig_expr_set':
drivers/pinctrl/aspeed/pinctrl-aspeed.c:192:11: error: comparison of constant '0' with boolean expression is always false [-Werror=bool-compare]
This slightly reworks the logic to use an explicit comparison with zero
before assigning to the temporary variable.
Reported-by: Colin King <colin.king@canonical.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These structures are only used to copy into other structures, so declare
them as const.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These structures are only used to copy into other structures, so declare
them as const.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The earlier patch can be simplified by using a bool
to indicate level trigger.
Reviewed-by: Pankaj Sen <Pankaj.Sen@amd.com>
Signed-off-by: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com>
[Fixup to earlier manually applied patch]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds IRQ support to STM32 gpios.
The EXTI controller has 16 lines dedicated to GPIOs.
EXTI line n can be connected to only line n of one of the GPIO ports, for
example EXTI0 can be connected to either PA0, or PB0, or PC0...
This port selection is done by specifying the port number into System
Config registers.
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
samsung_pinctrl_probe() can be called only after matching
the driver by the compatible string so this already implies
a non null dev->of_node. Remove the always false test
and related error trace. While at it drop another error log
in case of memory allocation failure - any errors are logged
by the memory subsystem.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In function mrfld_pinctrl_probe(), when duplicating the mrfld_families
array the requested memory region length is multiplied once too many by the
number of elements in the original array. Fix this to spare some memory.
Fixes: 4e80c8f505 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Signed-off-by: Vincent Stehlé <vincent.stehle@intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
While only Freescale Vybrid SoC has settings of GPIO capabilities done
by iomux controller, it is only a matter of GPIO controller driver
implementation for the rest of Freescale/NXP SoCs from iMX series.
As a practical example on GPIO request a pad function should be
switched to GPIO, but because this requires updates to all particular
iMX pinctrl drivers, for simplicity at the moment add only a proper
connection between shared pinctrl-imx and pinctrl/pinmux core, namely
.gpio_request_enable/.gpio_disable_free/.gpio_set_direction callbacks
should return success to a caller. This change allows to progress by
adding request/free callbacks into gpio-mxc.c driver.
Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
at91 used to set a default trigger type for GPIO interrupts in
order to cope with the old board files. These days are long gone,
and it all gets probed through DT.
Andras Szemzo reported that the Ethernet device on his board was
bailing to be probed, due to a conflict in interrupt trigger.
Surely enough, this is due to this default trigger still being
present, and turning this into a IRQ_TYPE_NONE fixes the issue.
Reported-by: Andras Szemzo <szemzo.andras@gmail.com>
Tested-by: Andras Szemzo <szemzo.andras@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch supports the {get,set}_io_voltage operations of SDHI.
This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v
voltage switch.
Based on work by Takeshi Kihara and Wolfram Sang.
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The pinconf-generic code expects configurations with arguments to be
returned in a packed format in order to be displayed properly by
pinconf_generic_dump_one().
Reading /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins on
r8a7795/salvator-x now shows:
pin 101 (GP_3_5): output drive strength (9 mA), pin power source (3300 selector)
Instead of:
pin 101 (GP_3_5): output drive strength (0 mA), pin power source (0 selector)
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add MSIOF0/1 pin groups to the R8A7792 PFC driver.
Based on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add QSPI pin groups to the R8A7792 PFC driver.
Based on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
H3 has single PWM channel. The second PWM channel is not supported,
so the pinctrl function should be removed.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Check for pinctrl_ops and pinmux_ops structures that are only stored in the
pctlops field and the pmxops field, respectively, of a pinctrl_desc
structure. These fields are declared const, so pinctrl_ops and pinmux_ops
structures that have this property can be declared as const also.
The semantic patch that makes this change in the pinctrl_ops is as
follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/)
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct pinctrl_ops i@p = { ... };
@ok@
identifier r.i;
struct pinctrl_desc e;
position p;
@@
e.pctlops = &i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct pinctrl_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct pinctrl_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Check for pinctrl_ops and pinmux_ops structures that are only stored in the
pctlops field and the pmxops field, respectively, of a pinctrl_desc
structure. These fields are declared const, so pinctrl_ops and pinmux_ops
structures that have this property can be declared as const also.
The semantic patch that makes this change in the pinctrl_ops is as
follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/)
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct pinctrl_ops i@p = { ... };
@ok@
identifier r.i;
struct pinctrl_desc e;
position p;
@@
e.pctlops = &i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct pinctrl_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct pinctrl_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Check for pinctrl_ops and pinmux_ops structures that are only stored in the
pctlops field and the pmxops field, respectively, of a pinctrl_desc
structure. These fields are declared const, so pinctrl_ops and pinmux_ops
structures that have this property can be declared as const also.
The semantic patch that makes this change in the pinctrl_ops is as
follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/)
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct pinctrl_ops i@p = { ... };
@ok@
identifier r.i;
struct pinctrl_desc e;
position p;
@@
e.pctlops = &i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct pinctrl_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct pinctrl_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In the function amd_gpio_irq_set_type, use the settings provided by
the BIOS,when the LevelTrig is Edge and activeLevel is HIGH, to configure
the GPIO registers. Ignore the settings from client.
Reviewed-by: Pankaj Sen <Pankaj.Sen@amd.com>
Signed-off-by:Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Just like the other member of the sunxi family, let's add a pinctrl table
for the muxing options.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A small subset of pins and functions are exposed. The selection of pins
and functions is driven by the development of OpenBMC[1] on the
AST2500 SoC, particularly around booting the IBM Witherspoon platform.
[1] https://github.com/openbmc/docs
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A subset of the pins and functions are exposed. The selection of
functions and pins is driven by the development of OpenBMC[1] on the
AST2400 SoC, particularly around booting the OpenPOWER Palmetto
development machine.
[1] https://github.com/openbmc/docs
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Aspeed SoCs typically provide more than 200 pins for GPIO and other
functions. The signal enabled on a pin is determined on a priority
basis, where a given pin can provide a number of different signal types.
In addition to the priority levels, the Aspeed pin controllers describe
the signal active on a pin by compound logical expressions involving
multiple operators, registers and bits. Some difficulty arises as a
pin's function bit masks for each priority level are frequently not the
same (i.e. we cannot just flip a bit to change from a high to low
priority signal), or even in the same register(s). Some configuration
bits affect multiple pins, while in other cases the signals for a bus
must each be enabled individually.
Together, these features give rise to some complexity in the
implementation. A more complete description of the complexities is
provided in the associated header file.
The patch doesn't implement pinctrl/pinmux/pinconf for any particular
Aspeed SoC, rather it adds the framework for defining pinmux
configurations.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
sd_emmc_a is used a controller for the SDIO modules. This adds the pin
configuration for the SDIO controller.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add initial support for the Pin Function Controller on the Renesas R-Car
M3-W SoC:
- Basic definitions,
- SCIF (serial) pins, groups and functions,
- SDHI pins, groups and functions.
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Merge tag 'sh-pfc-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Add support for R-Car M3-W
Add initial support for the Pin Function Controller on the Renesas R-Car
M3-W SoC:
- Basic definitions,
- SCIF (serial) pins, groups and functions,
- SDHI pins, groups and functions.
