Commit Graph

45 Commits

Author SHA1 Message Date
Linus Walleij
88057d6e4a pinctrl: sunxi: use gpiochip data pointer
This makes the driver use the data pointer added to the gpio_chip
to store a pointer to the state container instead of relying on
container_of().

Cc: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-05 14:15:03 +01:00
Linus Walleij
39e24ac3c3 pinctrl: sunxi: Be sure to clamp return value
As we want gpio_chip .get() calls to be able to return negative
error codes and propagate to drivers, we need to go over all
drivers and make sure their return values are clamped to [0,1].
We do this by using the ret = !!(val) design pattern.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-26 22:28:41 +01:00
Linus Walleij
58383c7842 gpio: change member .dev to .parent
The name .dev in a struct is normally reserved for a struct device
that is let us say a superclass to the thing described by the struct.
struct gpio_chip stands out by confusingly using a struct device *dev
to point to the parent device (such as a platform_device) that
represents the hardware. As we want to give gpio_chip:s real devices,
this is not working. We need to rename this member to parent.

This was done by two coccinelle scripts, I guess it is possible to
combine them into one, but I don't know such stuff. They look like
this:

@@
struct gpio_chip *var;
@@
-var->dev
+var->parent

and:

@@
struct gpio_chip var;
@@
-var.dev
+var.parent

and:

@@
struct bgpio_chip *var;
@@
-var->gc.dev
+var->gc.parent

Plus a few instances of bgpio that I couldn't figure out how
to teach Coccinelle to rewrite.

This patch hits all over the place, but I *strongly* prefer this
solution to any piecemal approaches that just exercise patch
mechanics all over the place. It mainly hits drivers/gpio and
drivers/pinctrl which is my own backyard anyway.

Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: Alek Du <alek.du@intel.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Jiri Kosina <jkosina@suse.cz>
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Acked-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-11-19 09:24:35 +01:00
Linus Torvalds
e86328c489 This is the bulk of GPIO changes for v4.4:
GPIO core:
 - Define and handle flags for open drain/open collector
   and open source/open emitter, also know as "single-ended"
   configurations.
 - Generic request/free operations that handle calling out
   to the (optional) pin control backend.
 - Some refactoring related to an ABI change that did not
   happen, yet provide useful.
 - Added a real-time compliance checklist. Many GPIO chips
   have irqchips, and need to think this over with the RT
   patches going upstream.
 - Restructure, fix and clean up Kconfig menus a bit.
 
 New drivers:
 - New driver for AMD Promony.
 - New driver for ACCES 104-IDIO-16, a port-mapped I/O
   card, ISA-style. Very retro.
 
 Subdriver changes:
 - OMAP changes to handle real time requirements.
 - Handle trigger types for edge and level IRQs on PL061
   properly. As this hardware is very common it needs to
   set a proper example for others to follow.
 - Some container_of() cleanups.
 - Delete the unused MSM driver in favor of the driver that
   is embedded inside the pin control driver.
 - Cleanup of the ath79 GPIO driver used by many, many
   OpenWRT router targets.
 - A consolidated IT87xx driver replacing the earlier
   very specific IT8761e driver.
 - Handle the TI TCA9539 in the PCA953x driver. Also
   handle ACPI devices in this subdriver.
 - Drop xilinx arch dependencies as these FPGAs seem to
   profilate over a few different architectures. MIPS and
   ARM come to mind.
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Merge tag 'gpio-v4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Linus Walleij:
 "Here is the bulk of GPIO changes for the v4.4 development cycle.

  The only changes hitting outside drivers/gpio are in the pin control
  subsystem and these seem to have settled nicely in linux-next.

  Development mistakes and catfights are nicely documented in the
  reverts as you can see.  The outcome of the ABI fight is that we're
  working on a chardev ABI for GPIO now, where hope to show results for
  the v4.5 kernel.

  Summary of changes:

  GPIO core:
   - Define and handle flags for open drain/open collector and open
     source/open emitter, also know as "single-ended" configurations.
   - Generic request/free operations that handle calling out to the
     (optional) pin control backend.
   - Some refactoring related to an ABI change that did not happen, yet
     provide useful.
   - Added a real-time compliance checklist.  Many GPIO chips have
     irqchips, and need to think this over with the RT patches going
     upstream.
   - Restructure, fix and clean up Kconfig menus a bit.

  New drivers:
   - New driver for AMD Promony.
   - New driver for ACCES 104-IDIO-16, a port-mapped I/O card,
     ISA-style.  Very retro.

  Subdriver changes:
   - OMAP changes to handle real time requirements.
   - Handle trigger types for edge and level IRQs on PL061 properly.  As
     this hardware is very common it needs to set a proper example for
     others to follow.
   - Some container_of() cleanups.
   - Delete the unused MSM driver in favor of the driver that is
     embedded inside the pin control driver.
   - Cleanup of the ath79 GPIO driver used by many, many OpenWRT router
     targets.
   - A consolidated IT87xx driver replacing the earlier very specific
     IT8761e driver.
   - Handle the TI TCA9539 in the PCA953x driver.  Also handle ACPI
     devices in this subdriver.
   - Drop xilinx arch dependencies as these FPGAs seem to profilate over
     a few different architectures.  MIPS and ARM come to mind"

* tag 'gpio-v4.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (57 commits)
  gpio: fix up SPI submenu
  gpio: drop surplus I2C dependencies
  gpio: drop surplus X86 dependencies
  gpio: dt-bindings: document the official use of "ngpios"
  gpio: MAINTAINERS: Add an entry for the ATH79 GPIO driver
  gpio / ACPI: Allow shared GPIO event to be read via operation region
  gpio: group port-mapped I/O drivers in a menu
  gpio: Add ACCES 104-IDIO-16 driver maintainer entry
  gpio: zynq: Document interrupt-controller DT binding
  gpio: xilinx: Drop architecture dependencies
  gpio: generic: Revert to old error handling in bgpio_map
  gpio: add a real time compliance notes
  Revert "gpio: add a real time compliance checklist"
  gpio: Add GPIO support for the ACCES 104-IDIO-16
  gpio: driver for AMD Promontory
  gpio: xlp: Convert to use gpiolib irqchip helpers
  gpio: add a real time compliance checklist
  gpio/xilinx: enable for MIPS
  gpiolib: Add and use OF_GPIO_SINGLE_ENDED flag
  gpiolib: Split GPIO flags parsing and GPIO configuration
  ...
2015-11-02 12:59:12 -08:00
Hans de Goede
8297992cad pinctrl: sunxi: Fix irq_of_xlate for the r_pio pinctrl block
The r_pio gpio / pin controller has a pin_base of non 0, we need to
adjust for this before calling sunxi_pinctrl_desc_find_function_by_pin.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-23 10:11:34 +02:00
Jonas Gorski
98c85d583a pinctrl: replace trivial implementations of gpio_chip request/free
Replace all trivial request/free callbacks that do nothing but call into
pinctrl code with the generic versions.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-16 22:20:21 +02:00
Javier Martinez Canillas
5c99c0ffa4 pinctrl: sunxi: Remove unneeded semicolon
It's not needed an is just creating a null statement, so remove it.

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-02 04:06:47 -07:00
Thomas Gleixner
bd0b9ac405 genirq: Remove irq argument from irq flow handlers
Most interrupt flow handlers do not use the irq argument. Those few
which use it can retrieve the irq number from the irq descriptor.

Remove the argument.

Search and replace was done with coccinelle and some extra helper
scripts around it. Thanks to Julia for her help!

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
2015-09-16 15:47:51 +02:00
Thomas Gleixner
b9a5ec33e3 pinctrl: sunxi: Use irq_set_chip_handler_name_locked()
__irq_set_chip_handler_name_locked() is about to be replaced. Use
irq_set_chip_handler_name_locked() instead.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
2015-09-16 12:42:49 +02:00
Maxime Ripard
d8323c6b03 pinctrl: sunxi: Add custom irq_domain_ops
The current interrupt parsing code was working by accident, because the
default was actually parsing the first node of interrupts.

While that was mostly working (and the flags were actually ignored), this
binding has never been documented, and doesn't work with SoCs that have
multiple interrupt banks anyway.

Add a proper interrupt xlate function, that uses the same description than
the GPIOs (<bank> <pin> <flags>), that will make things less confusing.

The EINT number will still be used as the hwirq number, but won't be
exposed through the DT.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-27 14:56:30 +02:00
Maxime Ripard
fb5b778808 pinctrl: sunxi: Add irq_chip name
In order to ease the debugging, add a name to the irq_chips.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-27 14:05:16 +02:00
Maxime Ripard
a0d6de9bdf pinctrl: sunxi: Use common functions to change irq_chip and handler
The current code uses some custom variable affectations, while we have
common functions to do exactly that. Move to the common functions.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-27 14:05:04 +02:00
Thomas Gleixner
eeef97b182 pinctrl/sunxi: Prepare sunxi_pinctrl_irq_handler for irq argument removal
The irq argument of most interrupt flow handlers is unused or merily
used instead of a local variable. The handlers which need the irq
argument can retrieve the irq number from the irq descriptor.

Search and update was done with coccinelle and the invaluable help of
Julia Lawall.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
2015-07-17 21:56:23 +02:00
Jiang Liu
5663bb27de pinctrl: Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc
Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we
already have a pointer to corresponding irq_desc.

Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-17 21:56:20 +02:00
Linus Torvalds
d5fb82137b Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner:
 "This contains:

   - a series of fixes for interrupt drivers to prevent a potential race
     when installing a chained interrupt handler

   - a fix for cpumask pointer misuse

   - a fix for using the wrong interrupt number from struct irq_data

   - removal of unused code and outdated comments

   - a few new helper functions which allow us to cleanup the interrupt
     handling code further in 4.3

   I decided against doing the cleanup at the end of this merge window
   and rather do the preparatory steps for 4.3, so we can run the final
   ABI change at the end of the 4.3 merge window with less risk"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (26 commits)
  ARM/LPC32xx: Use irq not hwirq for __irq_set_handler_locked()
  genirq: Implement irq_set_handler_locked()/irq_set_chip_handler_name_locked()
  genirq: Introduce helper irq_desc_get_irq()
  genirq: Remove irq_node()
  genirq: Clean up outdated comments related to include/linux/irqdesc.h
  mn10300: Fix incorrect use of irq_data->affinity
  MIPS/ralink: Fix race in installing chained IRQ handler
  MIPS/pci: Fix race in installing chained IRQ handler
  MIPS/ath25: Fix race in installing chained IRQ handler
  MIPS/ath25: Fix race in installing chained IRQ handler
  m68k/psc: Fix race in installing chained IRQ handler
  avr32/at32ap: Fix race in installing chained IRQ handler
  sh/intc: Fix race in installing chained IRQ handler
  sh/intc: Fix potential race in installing chained IRQ handler
  pinctrl/sun4i: Fix race in installing chained IRQ handler
  pinctrl/samsung: Fix race in installing chained IRQ handler
  pinctrl/samsung: Fix race in installing chained IRQ handler
  pinctrl/exynos: Fix race in installing chained IRQ handler
  pinctrl/st: Fix race in installing chained IRQ handler
  pinctrl/adi2: Fix race in installing chained IRQ handler
  ...
2015-07-01 15:19:35 -07:00
Thomas Gleixner
ef80e87d20 pinctrl/sun4i: Fix race in installing chained IRQ handler
Fix a race where a pending interrupt could be received and the handler
called before the handler's data has been setup, by converting to
irq_set_chained_handler_and_data().

Search and conversion was done with coccinelle:

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
|
-irq_set_chained_handler(E1, E3);
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

@@
expression E1, E2, E3;
@@
(
-if (irq_set_chained_handler(E1, E3) != 0)
-   BUG();
...
|
-irq_set_chained_handler(E1, E3);
...
)
-irq_set_handler_data(E1, E2);
+irq_set_chained_handler_and_data(E1, E3, E2);

Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Fan Wu <fwu@marvell.com>
Cc: abdoulaye berthe <berthe.ab@gmail.com>
Cc: Alexandre Courbot <acourbot@nvidia.com>
Cc: linux-gpio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
2015-06-25 11:57:17 +02:00
Masahiro Yamada
323de9efdf pinctrl: make pinctrl_register() return proper error code
Currently, pinctrl_register() just returns NULL on error, so the
callers can not know the exact reason of the failure.

Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some
-ENOMEM on error of pinctrl_register(), although the error code
might be different from the real cause of the error.

This commit reworks pinctrl_register() to return the appropriate
error code and modifies all of the pinctrl drivers to use IS_ERR()
for the error checking and PTR_ERR() for getting the error code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Ray Jui <rjui@broadcom.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Acked-by: Wei Chen <Wei.Chen@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 14:49:52 +02:00
Hans de Goede
ef6d24cc7f pinctrl: sun4i: GPIOs configured as irq must be set to input before reading
On sun4i-a10, when GPIOs are configured as external interrupt the value for
them in the data register does not seem to get updated, so set their mux to
input (and restore afterwards) when reading the pin.

Missed edges seem to be buffered, so this does not introduce a race
condition.

I've also tested this on sun5i-a13 and sun7i-a20 and those do not seem to
be affected, the input value representation in the data register does seem
to correctly get updated to the actual pin value while in irq mode there.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 10:56:46 +01:00
Alexandre Courbot
e3a2e87893 gpio: rename gpio_lock_as_irq to gpiochip_lock_as_irq
This function actually operates on a gpio_chip, so its prefix should
reflect that fact for consistency with other functions defined in
gpio/driver.h.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-28 17:30:59 +01:00
Linus Walleij
03e9f0cac5 pinctrl: clean up after enable refactoring
commit 2243a87d90
"pinctrl: avoid duplicated calling enable_pinmux_setting for a pin"
removed the .disable callback from the struct pinmux_ops,
making the .enable() callback the only remaining callback.

However .enable() is a bad name as it seems to imply that a
muxing can also be disabled. Rename the callback to .set_mux()
and also take this opportunity to clean out any remaining
mentions of .disable() from the documentation.

Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Acked-by: Fan Wu <fwu@marvell.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-09-04 10:05:07 +02:00
Linus Torvalds
e0b8b78651 This is the bulk pin control changes for the v3.17 merge
development cycle:
 
 - Get rid of the .disable() callback from the driver callback
   vtable. This callback was abused and counterintuitive since
   a pin or group of pins can be said to always be in some
   setting, and never really disabled. We now only enable a
   certain muxing, and move between some certain muxings, we
   never "disable" a mux setting.
 
 - Some janitorial moving the MSM, Samsung and Nomadik and
   drivers to their own subdirectories for a clearer view in
   the subsystem. This will continue.
 
 - Kill off the use of the return value from gpiochip_remove(),
   this will be done in parallel in the GPIO subsystem and
   hopefully not trigger too many unchecked return value
   warnings before we get rid of this altogether.
 
 - A huge set of changes and improvements to the Allwinner
   sunxi drivers especially for their latest A23 and A31 SoCs,
   and some ground work for the new sun8i platform family.
 
 - A large set of Rockchip driver improvements adding support
   for the RK3288 SoC.
 
 - Advances in migration of older Freescale platforms to pin
   control, especially i.MX1.
 
 - Samsung and Exynos improvements.
 
 - Support for the Qualcomm MSM8960 SoC.
 
 - Use the gpiolib irqchip helpers for the ST SPEAr and
   Intel Baytrail drivers.
 
 - A bunch of nice janitorial work done with cppcheck.
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Merge tag 'pinctrl-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pinctrl updates from Linus Walleij:
 "This is the bulk pin control changes for the v3.17 merge development
  cycle:

   - get rid of the .disable() callback from the driver callback vtable.

     This callback was abused and counterintuitive since a pin or group
     of pins can be said to always be in some setting, and never really
     disabled.  We now only enable a certain muxing, and move between
     some certain muxings, we never "disable" a mux setting

   - some janitorial moving the MSM, Samsung and Nomadik and drivers to
     their own subdirectories for a clearer view in the subsystem.  This
     will continue

   - kill off the use of the return value from gpiochip_remove(), this
     will be done in parallel in the GPIO subsystem and hopefully not
     trigger too many unchecked return value warnings before we get rid
     of this altogether

   - a huge set of changes and improvements to the Allwinner sunxi
     drivers especially for their latest A23 and A31 SoCs, and some
     ground work for the new sun8i platform family

   - a large set of Rockchip driver improvements adding support for the
     RK3288 SoC

   - advances in migration of older Freescale platforms to pin control,
     especially i.MX1

   - Samsung and Exynos improvements

   - support for the Qualcomm MSM8960 SoC

   - use the gpiolib irqchip helpers for the ST SPEAr and Intel Baytrail
     drivers

   - a bunch of nice janitorial work done with cppcheck"

* tag 'pinctrl-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (61 commits)
  pinctrl: baytrail: Convert to use gpiolib irqchip
  pinctrl: sunxi: number gpio ranges starting from 0
  pinctrl: sunxi: use gpiolib API to mark a GPIO used as an IRQ
  pinctrl: rockchip: add drive-strength control for rk3288
  pinctrl: rockchip: add separate type for rk3288
  pinctrl: rockchip: set is_generic in pinconf_ops
  pinctrl: msm: drop negativity check on unsigned value
  pinctrl: remove all usage of gpio_remove ret val in driver/pinctl
  pinctrl: qcom: Make muxing of gpio function explicit
  pinctrl: nomadik: move all Nomadik drivers to subdir
  pinctrl: samsung: Group all drivers in a sub-dir
  sh-pfc: sh73a0: Introduce the use of devm_regulator_register
  sh-pfc: Add renesas,pfc-r8a7791 to binding documentation
  pinctrl: msm: move all qualcomm drivers to subdir
  pinctrl: msm: Add msm8960 definitions
  pinctrl: samsung: Allow pin value to be initialized using pinfunc
  pinctrl: samsung: Allow grouping multiple pinmux/pinconf nodes
  pinctrl: exynos: Consolidate irq_chips of GPIO and WKUP EINTs
  pinctrl: samsung: Handle GPIO request and free using pinctrl helpers
  pinctrl: samsung: Decouple direction setting from pinctrl
  ...
2014-08-07 17:20:53 -07:00
Chen-Yu Tsai
343f132752 pinctrl: sunxi: number gpio ranges starting from 0
The pinctrl-sunxi driver originally used the pin number as the gpio
range offset. This resulted in large, bogus gpio numbers for the
new sun6i-a31-r pinctrl devices.

This patch makes the driver number the gpios ranges starting from an
offset of 0, by subtracting the pin_base number from the pin number.
This also makes the system-wide gpio number match the pin number.

Tested on sun8i with sysfs exported gpios.

This patch also changes the GPIO bindings for R_PIO:

    gpios = <&r_pio B N flag>;

Where B originally was the pinbank label (L or M) counted from A,
with this patch it becomes (L or M) counted from its pinbank base (L).

Thus

    gpios = <&r_pio 10 11 0>; /* PL11 */

becomes

    gpios = <&r_pio 0 11 0>; /* PL11 */

IMO this is correct, as the binding shows the bank offset and pin offset
within the bank for the GPIO controller. But I'm worried it might be a
bit confusing.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-28 12:14:33 +02:00
Chen-Yu Tsai
f83549d61d pinctrl: sunxi: use gpiolib API to mark a GPIO used as an IRQ
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-28 12:10:46 +02:00
abdoulaye berthe
b4e7c55dab pinctrl: remove all usage of gpio_remove ret val in driver/pinctl
Signed-off-by: abdoulaye berthe <berthe.ab@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-22 16:34:12 +02:00
Chen-Yu Tsai
0d3bafac65 pinctrl: sunxi: Fix multi bank interrupt support in gpio_to_irq
When mapping the interrupts, the gpio_to_irq function did not consider
the bank number of the gpio pin in question, only the offset or the
interrupt number in the bank. As a result, requests for interrupts in
the later banks get mapped to the first bank.

This issue was discovered while enabling mmc on the new sun8i platform.
The tablet I have uses a pin/interrupt from the second bank to do mmc
card detection. Tested on this very device with register inspection and
actual mmc card insertion/removal.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:25 +02:00
Hans de Goede
d61e23e525 pinctrl: sunxi: Define enable / disable irq callbacks
Some drivers use disable_irq / enable_irq and do the work
clearing the source in another thread instead of using a threaded
interrupt handler.

The irqchip used not having irq_disable and irq_enable
callbacks in this case, will lead to unnecessary spurious
interrupts:

On a disable_irq in a chip without a handler for this, the irq
core will remember the disable, but not actually call into the
irqchip. With a level triggered interrupt (where the source has
not been cleared) this will lead to an immediate retrigger, at
which point the irq-core will mask the irq. So having an
irq_disable callback in the irqchip will save us the interrupt
firing a 2nd time for nothing.

Drivers using disable / enable_irq like this, will call
enable_irq when they finally have cleared the interrupt source,
without an enable_irq callback, this will turn into an unmask,
at which point the irq will trigger immediately because when it
was originally acked the level was still high, so the ack was
a nop.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:24 +02:00
Hans de Goede
f4c51c103b pinctrl: sunxi: Properly handle level triggered gpio interrupts
For level triggered gpio interrupts we need to use handle_fasteoi_irq,
like we do with the irq-sunxi-nmi driver. This is necessary to give threaded
interrupt handlers a chance to actuall clear the source of the interrupt
(which may involve sleeping waiting for i2c / spi / mmc transfers), before
acknowledging the interrupt.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:24 +02:00
Hans de Goede
fea6d8efd0 pinctrl: sunxi: Move setting of mux to irq type
With level triggered interrupt mask / unmask will get called for each
interrupt, doing the somewhat expensive mux setting on each unmask thus is
not a good idea. Instead add a request_resources callback and do it there.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:24 +02:00
Chen-Yu Tsai
578c0a8721 pinctrl: sunxi: Add IRQCHIP_SKIP_SET_WAKE flag for pinctrl irq chip
The sunxi pinctrl irq chip driver does not support wakeup at the
moment. Adding IRQCHIP_SKIP_SET_WAKE lets the irqs work with drivers
using wakeup.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11 14:08:23 +02:00
Maxime Ripard
aebdc8abc9 pinctrl: sunxi: Implement multiple interrupt banks support
The A23 and A31 support multiple interrupt banks. Support it by adding a linear
domain covering all the banks. It's trickier than it should because there's an
interrupt per bank, so we have multiple interrupts using the same domain.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:35:12 +02:00
Maxime Ripard
645ec71454 pinctrl: sunxi: Remove irq_mask_ack and use irq_ack instead
If irq_mask_ack is not defined, mask_ack_irq will call irq_mask and then
irq_ack. In order to avoid code duplication, between irq_mask_ack and irq_mask,
just declare irq_ack.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:35:11 +02:00
Sachin Kamat
bd07894e21 pinctrl: sunxi: Fix potential null pointer dereference
kzalloc can fail. Add a null check to avoid null pointer
dereference error while accessing the pointer later.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:34:56 +02:00
Chen-Yu Tsai
d54e9a28ca pinctrl: sunxi: create irq/pin mapping during init
The irq/pin mapping is used to lookup the pin to mux to the irq
function when the irq is enabled. It is created when gpio_to_irq
is called. Creating the mapping during init allows us to map the
interrupts directly from the device tree.

Originally the IRQ to pin mapping was created when gpio_to_irq
was called with a GPIO handle. The mapping in turn is used to mux
the pin into EINT mode.

If the mapping is created during gpio_to_irq, we can't use the
interrupts directly, i.e. through the DT with "interrupts = <&pio A 4>".

Instead we'd have to use "gpios = <&pio A B>", then pass the gpio
through to gpio_to_irq.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 16:11:30 +02:00
Chen-Yu Tsai
b4575c6998 pinctrl: sunxi: fix pin numbers passed to register offset helpers
The pin numbers passed to sunxi_*_reg helpers to get the correct
registers should be the pin offset for the PIO block, not the
absolute number we use that is based on the alphanumeric labels
Allwinner uses.

This patch subtracts .pin_base from the pin number passed to these
functions, so the driver accesses the correct registers.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 11:26:01 +02:00
Maxime Ripard
ba6764d57d pinctrl: sunxi: Fix multiple registration issue
When the support for the PRCM muxer on the A31 has been added, the global
static pinctl_desc definition has been left as is. Unfortunately, this
structure is used to register the pinctrl device, and prior to this
registration, we set the name and pins field.

Since this structure is shared across instances, that means that the latest
registered pinctrl device wins in setting the name, pins and pins numbers,
which is not really a good thing.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:36:27 +02:00
Maxime Ripard
dc9691066f pinctrl: sunxi: Move the reset handling functions out of the core
The way that reset is handled right now is that it is made optional for every
pinctrl driver, while actually, it isn't used at all for the main pin
controllers so far, and while it's mandatory for the A31's secondary pin
controller.

Move the reset functions out of the core and in the driver, where they can be
made mandatory.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 19:57:18 -05:00
Maxime Ripard
2519859418 pinctrl: sunxi: Move Allwinner A20 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be.

This is the final step toward retiring pinctrl-sunxi-pins.h that used to define
all the pins for all the Allwinner SoCs in a single header, that would have in
turn result in having these structures in the final binary as many times as the
header was included.

We can finally remove that header, and remove all the driver part of the
pinctrl-sunxi core.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:04:49 -07:00
Maxime Ripard
16c675f989 pinctrl: sunxi: Move Allwinner A31 special pins driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:31 -07:00
Maxime Ripard
1c996176e7 pinctrl: sunxi: Move Allwinner A31 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:30 -07:00
Maxime Ripard
342cefb212 pinctrl: sunxi: Move Allwinner A13 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:29 -07:00
Maxime Ripard
0a127c1c39 pinctrl: sunxi: Move Allwinner A10s pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:29 -07:00
Maxime Ripard
f2821b1ca3 pinctrl: sunxi: Move Allwinner A10 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:28 -07:00
Maxime Ripard
2284ba6b7d pinctrl: sunxi: Libraryse the driver
This will allow to have multiple drivers using the same core code, and
eventually, retire pinctrl-sunxi-pins.h

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:24 -07:00
Maxime Ripard
4409cafc1a pinctrl: sunxi: Switch to devm_ioremap_resource
The previous code was calling of_iomap, which doesn't do any resource
management, and doesn't call request_mem_region either. Use
devm_ioremap_resource that do both.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:44 -07:00
Maxime Ripard
5f9107774f pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directory
This will allow to create numerous files without crippling the main pinctrl
directory.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:43 -07:00