Commit Graph

9 Commits

Author SHA1 Message Date
Thomas Gleixner
52e6676ef5 treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE (part 1)
Based on the normalized pattern:

    this program is free software you can redistribute it and/or modify it
    under the terms of the gnu general public license as published by the
    free software foundation version 2  this program is distributed as is
    without any warranty of any kind whether express or implied without
    even the implied warranty of merchantability or fitness for a
    particular purpose see the gnu general public license for more details

extracted by the scancode license scanner the SPDX license identifier

    GPL-2.0-only

has been chosen to replace the boilerplate/reference.

Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-06-10 14:51:35 +02:00
Tom Rix
7c55e8efd2 clk: cleanup comments
For spdx
Space instead of tab before spdx tag

Removed repeated works
the, to, two

Replacements
much much to a much
'to to' to 'to do'
aready to already
Comunications to Communications
freqency to frequency

Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20220222195153.3817625-1-trix@redhat.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-11 18:22:15 -08:00
Lori Hikichi
becf123772 clk: iproc: Allow iproc pll to runtime calculate vco parameters
Add the ability for the iproc pll to calculate the pll parameters at
runtime instead of only using predefined tables. This ability allows
the clock users to select from the full range of vco frequencies.
The old method of table based programming is retained so that existing
users will retain expected behavior. The flag IPROC_CLK_PLL_CALC_PARAM
will need to be set to enable the new runtime calculation method.
Currently, this is only being enabled for the audio pll.

This feature also revealed a problem with the driver using the
round_rate api.  The round_rate api does not allow for frequencies larger
than 2^31 to be returned.  Those large frequencies are interpreted as an
error code. Therefore, we are moving to the determine_rate api which
solves this problem.

Signed-off-by: Simran Rai <ssimran@broadcom.com>
Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-28 14:53:33 -08:00
Ray Jui
df416e565d clk: iproc: Remove __init from header
Remove __init macro from all function prototypes in clk-iproc.h

Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:31:40 -08:00
Simran Rai
bcd8be1398 clk: iproc: Add support for Cygnus audio clocks
This patch adds support for Broadcom Cygnus audio PLL and leaf
clocks

Signed-off-by: Simran Rai <ssimran@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:31:38 -08:00
Jon Mason
40c8bec3f2 clk: iproc: Separate status and control variables
Some PLLs have separate registers for Status and Control.  The means the
pll_base needs to be split into 2 new variables, so that those PLLs can
specify device tree registers for those independently.  Also, add a new
driver flag to identify this presence of the split, and let the driver
know that additional registers need to be used.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21 17:03:41 -07:00
Jon Mason
f713c6bf32 clk: iproc: Split off dig_filter
The PLL loop filter/gain can be located in a separate register on some
SoCs.  Split these off into a separate variable, so that an offset can
be added if necessary.  Also, make the necessary modifications to the
Cygnus and NSP drivers for this change.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21 17:02:57 -07:00
Jon Mason
01b6722fdf clk: iproc: Add PWRCTRL support
Some iProc SoC clocks use a different way to control clock power, via
the PWRDWN bit in the PLL control register.  Since the PLL control
register is used to access the PWRDWN bit, there is no need for the
pwr_base when this is being used.  A new flag, IPROC_CLK_EMBED_PWRCTRL,
has been added to identify this usage.  We can use the AON interface to
write the values to enable/disable PWRDOWN.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
[sboyd@codeaurora.org: Remove useless parentheses]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-21 16:53:15 -07:00
Ray Jui
5fe225c105 clk: iproc: add initial common clock support
This adds basic and generic support for various iProc PLLs and clocks
including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks.

SoCs under the iProc architecture can define their specific register
offsets and clock parameters for their PLL and clock controllers. These
parameters can be passed as arugments into the generic iProc PLL and
clock setup functions

Derived from code originally provided by Jonathan Richardson
<jonathar@broadcom.com>

Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-06-18 12:36:38 -07:00