Add group configuration for uarts that are cut down
variants, the standard being full, i.e. all signals,
flow control, i.e. rx/tx and cts/rts, and rx/tx only.
This allows us to be more precise in which pins we're
actually using.
Unfortunately the existing naming scheme leaves things
to be desired, e.g. uart3grp0 means RX/TX and CTS/RTS,
yet uart0grp0 means all pins.
Since the exising suffixes have different meaning for
different uarts, and the fact that we cannot change
the name of existing groups, makes it hard to use a
descriptive name for the newly added groups.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add missing pin group uart5nocts (all pins except cts), which has been
supported by the artpec6 pinctrl driver since its initial submission.
Fixes: 00df0582ea ("pinctrl: Add pincontrol driver for ARTPEC-6 SoC")
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the bindings for the pinmux functions in the
ARTPEC-6 SoC, including bias and drive strength.
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
