This updates bindings for MT7629 pinctrl driver.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Sean Wang <sean.wang@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We already had an earlier conclusion that all new i.MX Socs will keep
using the legacy i.MX Pinctrl bindings instead of generic pin config.
However, MX7ULP generic pin config binding support has already been in
tree before that time. Per SoC maintainers' suggestions, in order to
get a better consistency for all i.MX devices, we'd like to go back to
imx legacy binding for MX7ULP as well.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-gpio@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Broadcom SoC pins are controlled using CRU ("Clock and Reset Unit" or
"Central Resource Unit") registers. There are more CRU registers and
functions so CRU should be represented as a separated block in DT.
Moreover CRU is a sub-block of DMU ("Device Management Unit") so that
one should also get its own node.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add support for the new RZ/N1D (R9A06G032) and RZ/N1S (R9A06G033)
SoCs,
- Add INTC-EX pin groups on R-Car E3.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCW7dQmQAKCRCKwlD9ZEnx
cB04AQCj1PoCEotqH9TGaGeVXal35LUMP279vz3HoJweY0DF2AD/QKd/jC2mHz/c
EypfJAvBvckw9AsdfNSacrCIdMNg7gE=
=gtgr
-----END PGP SIGNATURE-----
Merge tag 'sh-pfc-for-v4.20-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.20 (take three)
- Add support for the new RZ/N1D (R9A06G032) and RZ/N1S (R9A06G033)
SoCs,
- Add INTC-EX pin groups on R-Car E3.
Northstar has mux controller just like Northstar Plus and Northstar2.
It's a bit different though (different registers & pins) so it requires
its own binding.
It's needed to allow other block bindings specify required mux setup.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the binding for the TLMM pinctrl block found in the SDM660 platform.
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Renesas RZ/N1 device family PINCTRL node description.
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
- Add MSIOF pin groups on R-Car E3 and D3,
- Add support for the new RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs,
- Add I2C4, DU0, QSPI0, SDHI2, and USB pin groups on RZ/G1C,
- Convert to SPDX license identifiers,
- Small cleanups.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCW63oXAAKCRCKwlD9ZEnx
cEZ3AP4zgrTOnA9iDjgqMPtkaHcIX4b2R8fykZeRBs0J5u9R3QD/Y4JqDXF/AbVB
fAX+GuCf1oMOflFlde7Dpp1nDYIaAg8=
=0a9P
-----END PGP SIGNATURE-----
Merge tag 'sh-pfc-for-v4.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.20 (take two)
- Add MSIOF pin groups on R-Car E3 and D3,
- Add support for the new RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs,
- Add I2C4, DU0, QSPI0, SDHI2, and USB pin groups on RZ/G1C,
- Convert to SPDX license identifiers,
- Small cleanups.
Add the binding for the TLMM pinctrl block found in the QCS404 platform.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for the PMS405 GPIO support to the Qualcomm PMIC GPIO
binding.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Document PFC support for the R8A774C0 SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Document PFC support for the RZ/G1N (R8A7744) SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
- Add SATA and audio pin groups on R-Car M3-N,
- Add EtherAVB pin groups on RZ/G1C,
- Add PWM and display (DU) pin groups on R-Car E3,
- Add support for the new RZ/G2M (r8a774a1) SoC.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCW4k8kAAKCRCKwlD9ZEnx
cKAlAQCI8mw30q/VqEe6Y1aYFMeX6pyBun4viDUdDF4c4KKvzQEAlrWXDgIAkp/5
rPm+hMilDFyTdT5jL4ler0VDbGIo6wI=
=B0/X
-----END PGP SIGNATURE-----
Merge tag 'sh-pfc-for-v4.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.20
- Add SATA and audio pin groups on R-Car M3-N,
- Add EtherAVB pin groups on RZ/G1C,
- Add PWM and display (DU) pin groups on R-Car E3,
- Add support for the new RZ/G2M (r8a774a1) SoC.
The pinctrl-ingenic driver now supports the JZ4725B SoC.
Furthermore, the gpio-ingenic driver was dropped and the pinctrl-ingenic
driver is now responsible for providing the GPIO functionality.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Document PFC support for the R8A774A1 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
- Add Cirrus Logic Madera Codec (CS47L35, CS47L85 and CS47L90/91) driver
- Add ChromeOS EC CEC driver
- Add ROHM BD71837 PMIC driver
- New Device Support
- Add support for Dialog Semi DA9063L PMIC variant to DA9063
- Add support for Intel Ice Lake to Intel-PLSS-PCI
- Add support for X-Powers AXP806 to AXP20x
- New Functionality
- Add support for USB Charging to the ChromeOS Embedded Controller
- Add support for HDMI CEC to the ChromeOS Embedded Controller
- Add support for HDMI CEC to Intel HDMI
- Add support for accessory detection to Madera devices
- Allow individual pins to be configured via DT' wlf,csnaddr-pd
- Provide legacy platform specific EEPROM/Watchdog commands; rave-sp
- Fix-ups
- Trivial renaming/spelling fixes; cros_ec, da9063-*
- Convert to Managed Resources (devm_*); da9063-*, ti_am335x_tscadc
- Transition to helper macros/functions; da9063-*
- Constify; kempld-core
- Improve error path/messages; wm8994-core
- Disable IRQs locally instead of relying on USB subsystem; dln2
- Remove unused code; rave-sp
- New exports; sec-core
- Bug Fixes
- Fix possible false I2C transaction error; arizona-core
- Fix declared memory area size; hi655x-pmic
- Fix checksum type; rave-sp
- Fix incorrect default serial port configuration: rave-sp
- Fix incorrect coherent DMA mask for sub-devices; sm501
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEdrbJNaO+IJqU8IdIUa+KL4f8d2EFAlt6fm8ACgkQUa+KL4f8
d2H8qA/8CLIKKEyc3CiQIF4LqmOPn+P20gSlnNdDFGHV+ZpVryL6qKItDy76nbQS
+GrPCmhADDn7N224ENlv4TYsB1txr7iZvyNr6W7F0fbdTLq5Fl2+6WIB3NnopPPK
MGhzR2jikfuYGwEG+BG3efvTnrjoi+NPbNPHDdoegOiy/Q1R8PhjMKh10xWo3pgG
0TeZVg61ztfewAiebieMixNz+ehzFKK959Lsa7neV2ZsstBbM8B44UpXmLF5JLYe
SR1ai5etSPBLxEeTXxlE+oG+fnDWk9Eyile7z1Nwg4et9OiXdyqAXBoA+BNDj2N2
N8vHuU79pSra+XGbka/7Kyz8sXjb4u92mJlc1wDcsCF+hX+wGEmwkEUb0S4YEtOH
1POi4YuIq0WF1oLSgCla/Pui0OQPIZaT31XhInYLV7rAX+MPgH0cUuLDsmzcg4ut
C6RvoSzWiGA2JVqlALExSDtAkWUoZLjYkqnPYmZwGs25xsGUqJmiw1E73HI0OWr/
EJuKQbeq/bOmRPqbbwO7z7peZJHOt6j344VCXBdP/sB7d/lR1sEGpxC03MIogHrA
BuiPyfDXTF1NB/+ZPBFbSG2Xhcg51yL4ddRa1sMntP6J4Ht1dW7TOpLI21Yu3eRp
jzKnA9DRa/LPUvoR1y+C2LxDeBcT5qFMg4mZedOgio/C0vCXvus=
=4Yj4
-----END PGP SIGNATURE-----
Merge tag 'mfd-next-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"New Drivers:
- Add Cirrus Logic Madera Codec (CS47L35, CS47L85 and CS47L90/91) driver
- Add ChromeOS EC CEC driver
- Add ROHM BD71837 PMIC driver
New Device Support:
- Add support for Dialog Semi DA9063L PMIC variant to DA9063
- Add support for Intel Ice Lake to Intel-PLSS-PCI
- Add support for X-Powers AXP806 to AXP20x
New Functionality:
- Add support for USB Charging to the ChromeOS Embedded Controller
- Add support for HDMI CEC to the ChromeOS Embedded Controller
- Add support for HDMI CEC to Intel HDMI
- Add support for accessory detection to Madera devices
- Allow individual pins to be configured via DT' wlf,csnaddr-pd
- Provide legacy platform specific EEPROM/Watchdog commands; rave-sp
Fix-upsL
- Trivial renaming/spelling fixes; cros_ec, da9063-*
- Convert to Managed Resources (devm_*); da9063-*, ti_am335x_tscadc
- Transition to helper macros/functions; da9063-*
- Constify; kempld-core
- Improve error path/messages; wm8994-core
- Disable IRQs locally instead of relying on USB subsystem; dln2
- Remove unused code; rave-sp
- New exports; sec-core
Bug Fixes:
- Fix possible false I2C transaction error; arizona-core
- Fix declared memory area size; hi655x-pmic
- Fix checksum type; rave-sp
- Fix incorrect default serial port configuration: rave-sp
- Fix incorrect coherent DMA mask for sub-devices; sm501"
* tag 'mfd-next-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (60 commits)
mfd: madera: Add register definitions for accessory detect
mfd: sm501: Set coherent_dma_mask when creating subdevices
mfd: bd71837: Devicetree bindings for ROHM BD71837 PMIC
mfd: bd71837: Core driver for ROHM BD71837 PMIC
media: platform: cros-ec-cec: Fix dependency on MFD_CROS_EC
mfd: sec-core: Export OF module alias table
mfd: as3722: Disable auto-power-on when AC OK
mfd: axp20x: Support AXP806 in I2C mode
mfd: axp20x: Add self-working mode support for AXP806
dt-bindings: mfd: axp20x: Add "self-working" mode for AXP806
mfd: wm8994: Allow to configure CS/ADDR Pulldown from dts
mfd: wm8994: Allow to configure Speaker Mode Pullup from dts
mfd: rave-sp: Emulate CMD_GET_STATUS on device that don't support it
mfd: rave-sp: Add legacy watchdog ping command translation
mfd: rave-sp: Add legacy EEPROM access command translation
mfd: rave-sp: Initialize flow control and parity of the port
mfd: rave-sp: Fix incorrectly specified checksum type
mfd: rave-sp: Remove unused defines
mfd: hi655x: Fix regmap area declared size for hi655x
mfd: ti_am335x_tscadc: Fix struct clk memory leak
...
Here are all of the driver core and related patches for 4.19-rc1.
Nothing huge here, just a number of small cleanups and the ability to
now stop the deferred probing after init happens.
All of these have been in linux-next for a while with only a merge issue
reported. That merge issue is in fs/sysfs/group.c and Stephen has
posted the diff of what it should be to resolve this. I'll follow up
with that diff to this pull request.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-----BEGIN PGP SIGNATURE-----
iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCW3g86Q8cZ3JlZ0Brcm9h
aC5jb20ACgkQMUfUDdst+ynyXQCePaZSW8wft4b7nLN8RdZ98ATBru0Ani10lrJa
HQeQJRNbWU1AZ0ym7695
=tOaH
-----END PGP SIGNATURE-----
Merge tag 'driver-core-4.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core
Pull driver core updates from Greg KH:
"Here are all of the driver core and related patches for 4.19-rc1.
Nothing huge here, just a number of small cleanups and the ability to
now stop the deferred probing after init happens.
All of these have been in linux-next for a while with only a merge
issue reported"
* tag 'driver-core-4.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (21 commits)
base: core: Remove WARN_ON from link dependencies check
drivers/base: stop new probing during shutdown
drivers: core: Remove glue dirs from sysfs earlier
driver core: remove unnecessary function extern declare
sysfs.h: fix non-kernel-doc comment
PM / Domains: Stop deferring probe at the end of initcall
iommu: Remove IOMMU_OF_DECLARE
iommu: Stop deferring probe at end of initcalls
pinctrl: Support stopping deferred probe after initcalls
dt-bindings: pinctrl: add a 'pinctrl-use-default' property
driver core: allow stopping deferred probe after init
driver core: add a debugfs entry to show deferred devices
sysfs: Fix internal_create_group() for named group updates
base: fix order of OF initialization
linux/device.h: fix kernel-doc notation warning
Documentation: update firmware loader fallback reference
kobject: Replace strncpy with memcpy
drivers: base: cacheinfo: use OF property_read_u32 instead of get_property,read_number
kernfs: Replace strncpy with memcpy
device: Add #define dev_fmt similar to #define pr_fmt
...
- Remove an obsolete hack for PPC32 longtrail systems
- Make of_io_request_and_map() "name" arg optional
- Add vendor prefixes for bitmain, Asus, and Y Soft
- Remove 'interrupt-parent' from bindings as it is implicit
- New properties for wm8994 audio codec
- Add 'clocks' property support to SRAM binding
- Add binding for ASPEED coprocessor interrupt controller
- Various binding spelling and link fixes
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAltxnZgQHHJvYmhAa2Vy
bmVsLm9yZwAKCRD6+121jbxhw3kvD/4lNU3vfYZMKUUeY5w8Kt/EJiXOcVM0E4rV
xnzg4udgApkfZToYwnjwx42WI8QcCRF7axObodtRkgdxS8fT0nemGO7Mppwxe0Yl
zdYcGX+Y3bcZamjdEFfX2kt9C0ZalY/QnAYhlUWtT+1vXpsStvAOZddyTwP1l3Q+
+oujpS6xjIFtgVFrFclEiKzBuoVBYSznuWZBqfNMCIaGn3VnCdBLoYbx/NEqPsU2
AyPlWN8GquTtZJJMO0/VUGZGOrCnc1ZBADoza/YYPVzkMog1OJEJPxRRx5e5ddbR
HVRzmWiTwDOVq56MKhk+1FELsbBb3h6yKMKZY/jkbNhzm7pu0S1UKdCf1FpPsXcQ
1op6ryTpzfLF4PlKdRACcUH6HqEWoW4UVqiH5F2TWTvBMTb0Nqo3yHVobN0xwHTU
shgboQlSnTOdnOkXLMFCnDxzbpfGjZgJwXZAmrpz/z+ZOEPps70BXKl75tp7qQ35
8hMNZMZu1UWsd/qoIxbzUJMg2jG7KASSYPTPjgAPXieESiKIdJd8A8t/Qxvgq3f7
6SK+azqvQK1c6PtsTxxMp8JemR/Ih32CIwzaxSIaxmUwci+uX4tsyT406e4O8cJW
qCrEbEjy/5hKqbCS3/kP7hXtPdlHJSDgRn7vqjhgLyDyO8xzHXgbyPU1Q3+LEXI4
BpNil+NSXQ==
=AV4E
-----END PGP SIGNATURE-----
Merge tag 'devicetree-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull Devicetree updates from Rob Herring:
- Remove an obsolete hack for PPC32 longtrail systems
- Make of_io_request_and_map() "name" arg optional
- Add vendor prefixes for bitmain, Asus, and Y Soft
- Remove 'interrupt-parent' from bindings as it is implicit
- New properties for wm8994 audio codec
- Add 'clocks' property support to SRAM binding
- Add binding for ASPEED coprocessor interrupt controller
- Various binding spelling and link fixes
* tag 'devicetree-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
Documentation: remove dynamic-resolution-notes reference to non-existent file
dt-bindings: Add Y Soft Corporation vendor prefix
of/fdt: Remove PPC32 longtrail hack in memory scan
dt-bindings: remove 'interrupt-parent' from bindings
pinctrl: tegra: fix spelling in devicetree binding document
usb: dwc3: rockchip: Fix PHY documentation links.
dt-bindings: sound: wm8994: document wlf,csnaddr-pd property
dt-bindings: sound: wm8994: document wlf,spkmode-pu property
dt-bindings: sram: Add 'clocks' as an optional property
dt-bindings: Add vendor prefix for AsusTek Computer Inc.
dt-bindings: misc: ASPEED coprocessor interrupt controller
dt-bindings: gpio: pca953x: Document interrupts, update example
drivers/of: Make of_io_request_and_map() "name" argument optional
dt-bindings: Add bitmain vendor prefix
Documentation: devicetree: tilcdc: fix spelling mistake "suppors" -> "supports"
This patch adds mask parameter to define IRQ mux field.
This field could vary depend of IRQ mux selection register.
This parameter is needed if the mask is different of 0xf.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In case the exti line is not in line with the bank number (that is the case
when there is an hole between two banks, for example GPIOK and then GPIOZ),
use "st,bank-ioport" DT property to get the right exti line.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Immutable Branch which moves the cros_ec_i2c and cros_ec_spi
transport drivers from mfd to platform/chrome. Changes in arm are a simple
rename in defconfigs. Change in input is a rename in help text.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEE6gYDF28Li+nEiKLaHwn1ewov5lgFAltCtRsACgkQHwn1ewov
5lhIQg//fEoZkDIjFsWIDn2WB1brLS2q7Wnv01NJR3/ZxzA29JYQ1lNA3nCM5mVS
Bf1RqPfVwIO6/d+QA5AnxLBRpRYJ7F7NKwvTvrqQ9QpFPNOLk0m7uUNYSsWTOqlA
uoReeFfJ2/UuUavd04KJRPv1ilCjoki2Wyc4lqVFSJSGZZjDWUOASAiOd666h26F
avW4qBUpJm7mmAfOFh76g6c/Jq713fJkqfdRcstRajB13oLjotfRxa/Rhxb+y8aX
RrlNz8PChIjpYTQ7yDwfLU8u5TDg2sEtz8529YaddDNBWkRyC2BIrKrkev+GIiUx
SZiPT7nmvpEOGJoPQodUa5bgE/9db7pPKb7XqUNmYQIS71jtLaOXMNje9uLn2NHo
CJtoVHJXZ9YWyODn1NPvFM28aysis14PWQGWK1HRq5PCfb8TpZ8W0QTaJV18pUBe
vdrmgxPcdnkAn0Tbt92oBiUrsVT3zoSQuLw9FPuy3ne9Oz+TKHa6kKzjcMMkynwb
mFmDhf822mfbUVkjUpNTtLJ0UMsNtd/tphDUmv1OQDRNStZS/MI4+xr23bPZbf/X
blrIjz5fM6uhUbHSKztWnntGAtzbEy75zzyhh2w99JVzJtK4UK+3ET40Kko4KUIx
1ppYa2wOJVVSvd733O8mYGmzQotKuFc5lyNozlB4EUT8ro/zW1Q=
=EhHj
-----END PGP SIGNATURE-----
Merge branches 'ib-mfd-4.19', 'ib-mfd-gpio-pinctrl-4.19', 'ib-mfd-i915-media-platform-4.19' and 'ib-mfd-regulator-4.19', tag 'ib-platform-chrome-mfd-move-cros-ec-transport-for-4.19' into ibs-for-mfd-merged
Immutable branch (mfd, chrome) due for the v4.19 window
Immutable Branch which moves the cros_ec_i2c and cros_ec_spi
transport drivers from mfd to platform/chrome. Changes in arm are a simple
rename in defconfigs. Change in input is a rename in help text.
1. Add handling of external wakeup interrupts mask inside the pin
controller driver.
Existing solution is spread between the driver and machine code. The
machine code writes the mask but its value is taken from pin
controller driver.
This moves everything into pin controller driver allowing later to
remove the cross-subsystem interaction. Also this is a necessary
step for implementing later Suspend to RAM on ARMv8 Exynos5433.
2. Bring necessary suspend/resume callbacks for Exynos542x and
Exynos5260.
3. Document hidden requirement about one external wakeup interrupts
device node.
4. Minor documentation cleanups.
-----BEGIN PGP SIGNATURE-----
iQItBAABCAAXBQJbWJ6WEBxrcnprQGtlcm5lbC5vcmcACgkQwTdm5oaLg9dvJBAA
kgLUDDgkY+lKOQ/dRA7HJf2OTHSPZ3hhXpD8BnaRnqs8HRTWW8xVX+ts/wbXFnw2
s4Q45hYNqqSfH3lzQ67fKokjoQMf2TtmidXaHVfnVlNHa7gcFW0yj1Kc/4qRyRql
xo7FptZXM1bFZ/su3VMbSnBH+2n9gn4RDC5Zk5Vzgr6jC7Pu2kSgM0Q4dpk7sJg/
TwRT+HZV2RDN3APByGWHEZ5gbOtxj6L8+gHsvtgbf8STHVIlAAUS/dDAFAISusEI
SIkewPCZFvT9FWYqFQjuS7JTAVPgXeU+JisZaRyhR2sQFgu5qyvEZzRDV87f4X2b
Zf0dRMrrcScsNcIMerkKki0r1FVxPEaSjgAuK+8x5u+RopAgbmmiFBSt2pYUayVb
7M8rcfqLRgb6V8/Um/aGajirQaAj5DWtZGPbtCGF01uKCPPaEgE5ch2dXPjKeNbw
HSoj2dOKDnPApzWcsVbRpQfo9E9VszT3JZ9CEV64dxWLebYvQDx9f2vZxxkJnuYS
EcnPXY2E+QkwpSavwmqsbJhrHGVO8scveKQSS3TCmMyOJp2feerBlsyWXCjHGpeA
JLdYXPnj23jIQrcAtRu5a3DskjpT3CgsEheaRikds03vT706qEISLpTDHLbfhvGy
6oetWL6Cwzqq2tRpyOdX5Z/DWthRXJmhKyHhmGKI+ec=
=a9XD
-----END PGP SIGNATURE-----
Merge tag 'samsung-pinctrl-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v4.19
1. Add handling of external wakeup interrupts mask inside the pin
controller driver.
Existing solution is spread between the driver and machine code. The
machine code writes the mask but its value is taken from pin
controller driver.
This moves everything into pin controller driver allowing later to
remove the cross-subsystem interaction. Also this is a necessary
step for implementing later Suspend to RAM on ARMv8 Exynos5433.
2. Bring necessary suspend/resume callbacks for Exynos542x and
Exynos5260.
3. Document hidden requirement about one external wakeup interrupts
device node.
4. Minor documentation cleanups.
'interrupt-parent' is often documented as part of define bindings, but
it is really outside the scope of a device binding. It's never required
in a given node as it is often inherited from a parent node. Or it can
be implicit if a parent node is an 'interrupt-controller' node. So
remove it from all the binding files.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
This fixes a spelling mistake.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Rob Herring <robh@kernel.org>
The S5Pv210 external wakeup interrupts differ from Exynos therefore
separate compatible is needed. Duplicate existing flavor specific data
from exynos4210_wkup_irq_chip and add new compatible for S5Pv210.
At this point this new compatible does not bring anything new and works
exactly as existing "samsung,exynos4210-wakeup-eint".
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
ARMv7 hardware (S5Pv210 and Exynos SoCs) provides only 32 external
interrupts which can wakeup device from deep sleep modes. On S5Pv210
these are gph0-gph3. On all ARMv7 Exynos designs these are gpx0-gpx3.
There is only one 32-bit register for controlling the external wakeup
interrupt mask (masking and unmasking waking capability of these
interrupts).
This lead to implementation in pinctrl driver and machine code which was
using static memory for storing the mask value and not caring about
multiple devices of pin controller... because only one pin controller
device will be handling this.
Since each pin controller node in Device Tree maps onto one device, this
corresponds to hidden assumption in parsing the Device Tree: external
wakeup interrupts can be defined only once. Make this assumption an
explicit requirement.
ARMv8 Exynos5433 and Exynos7 bring additional 32 external wakeup
interrupts (up to 64 total, banks gpa0-gpa3 and gpf1-gpf5) and another
32-bit wide register for controlling them. Existing code does not
support it but anyway these additional interrupts will be belonging to
the same pin controller device/node.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <snawrocki@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
This adds the binding for the i.MX8MQ pin controller, in the same
fashion as earlier i.MX SoCs.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for the drive strength configuration. Usually, this value is
expressed in mA. Since the numeric value depends on VDDIOP voltage, a
value we can't retrieve at runtime, the controller uses low, medium and
high to define the drive strength.
The PIO controller accepts two values for the low drive configuration: 0
and 1. Most of the time, we don't care about the drive strength. So we
keep the default value which is 0. The drive strength is advertised
through the sysfs only when it has been explicitly set in the device
tree i.e. if its value is different from 0.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pin setup may be optional in some cases such as the reset default works
or the pin setup is done by the bootloader. In these cases, it is optional
for the OS to support managing the pin controller and pin setup. In order
to support this scenario, add a property 'pinctrl-use-default' to indicate
that the pin configuration is optional.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch adds the gpio-ranges and gpio-reserved-ranges property
definitions to the binding text files supported by the pinctrl-msm
driver framework.
gpio-ranges:
For DT-based platforms the pinctrl-msm framework currently relies
on the deprecated-for-DT gpiochip_add_pin_range() function to add
the range of GPIOs to be handled by the pin controller. Due to
interactions within gpiolib code, this causes the pinctrl-msm
driver to bail out (-517) during boot when a gpio-hog is declared.
This can be fatal and cause the system to not boot or reset
(for a detailed explanation and call-trace, refer to patch:
"pinctrl: msm: fix gpio-hog related boot issues" in this series).
gpio-reserved-ranges:
The binding has been added as a precaution since the TrustZone
firmware (aka QSEE), which is running as the hypervisor, might
have reserved certain, but undisclosed pins. Hence reading or
writing to the registers for those pins will cause an
XPU violation and this subsequently crashes the kernel.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update the binding for two more PMICs supported by the same driver.
While we're here, remove the duplicate pmi8994 lines because that
support got merged twice.
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rename:
pinctrl-binding.txt -> pinctrl-bindings.txt
In order to match the current name of this file.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Acked-by: Jonathan Corbet <corbet@lwn.net>
No core changes this time! Just a calm all-over-the-place
drivers, updates and fixes cycle as it seems.
New drivers/subdrivers:
- Actions Semiconductor S900 driver with more Actions
variants for S700, S500 in the pipe. Also generic GPIO
support on top of the same driver and IRQ support is in
the pipe.
- Renesas r8a77470 PFC support.
- Renesas r8a77990 PFC support.
- Allwinner Sunxi H6 R_PIO support.
- Rockchip PX30 support.
- Meson Meson8m2 support.
- Remove support for the ill-fated Samsung Exynos 5440 SoC.
Improvements:
- Context save/restore support in pinctrl-single.
- External interrupt support for the Mediatek MT7622.
- Qualcomm ACPI HID QCOM8002 supported.
Fixes:
- Fix up suspend/resume support for Exynos 5433.
- Fix Strago DMI fixes on the Intel Cherryview.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJbGOinAAoJEEEQszewGV1zogcQAIaSUz5bwGhP+FmmIiHpJlGH
MxpdIqu5cMg4e4IUA8jjB70xXgA48CLhAv/r6KjUIoF4G5wkDQS3vH+kIesdVbbK
pmF1LvyJ0PfB6sWdUx98gevCtI0ok4lSvIr9fSGQjcZt5U6Ln4hrhs34Hz12+e3K
BLhW+O1k1BbYEiPPpddgKL0F7cbEabx9wS056VjJKKbUxYMVprzaB4m/pbLHKrjW
vgFis/HQyEEC0erdLCRxF4rpzoTYGhE5XaOygZjjjdawU3wa+RyndNAlxhTwSFS4
W7ZJ41QRKM2vedlxUYpZk5hRWxsLF3cAeBfdtJpvavsqJLZutcuhw1vRTo8+WZ0k
X1KdtZmYnxOY+qoyg36uHf+kimcMUAHNKGVSoDxpbUEeJ+nSb7BD9YWfBlRikuq8
R0QDZ8+YxhqEt8np+SJx984Gnh2Rhxw9sWNJpJt609Nlp6aqTvmzuQbJPchHNk95
KNeFU/PZc0jPQLQVnrlHKQ/UM7PnnOYpGzloq+LBZpnHOHZJW1S8iOvJcPfay2eA
x/zZfj8/IaXELa7Bh8kZrI2UIxvxvVtF+zfRMbupVRr8+CqDOz3m/g9G298NWv5+
SBnJJcLZikxgMvOupH3FKfdgQ7tgfJrXzKynasUm33Ex90cst5REFSlLVhzU0CLb
2TtsB46XFugt3czmKsi9
=6On2
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for v4.18.
No core changes this time! Just a calm all-over-the-place drivers,
updates and fixes cycle as it seems.
New drivers/subdrivers:
- Actions Semiconductor S900 driver with more Actions variants for
S700, S500 in the pipe. Also generic GPIO support on top of the
same driver and IRQ support is in the pipe.
- Renesas r8a77470 PFC support.
- Renesas r8a77990 PFC support.
- Allwinner Sunxi H6 R_PIO support.
- Rockchip PX30 support.
- Meson Meson8m2 support.
- Remove support for the ill-fated Samsung Exynos 5440 SoC.
Improvements:
- Context save/restore support in pinctrl-single.
- External interrupt support for the Mediatek MT7622.
- Qualcomm ACPI HID QCOM8002 supported.
Fixes:
- Fix up suspend/resume support for Exynos 5433.
- Fix Strago DMI fixes on the Intel Cherryview"
* tag 'pinctrl-v4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
pinctrl: cherryview: limit Strago DMI workarounds to version 1.0
pinctrl: at91-pio4: add missing of_node_put
pinctrl: armada-37xx: Fix spurious irq management
gpiolib: discourage gpiochip_add_pin[group]_range for DT pinctrls
pinctrl: msm: fix gpio-hog related boot issues
MAINTAINERS: update entry for Mediatek pin controller
pinctrl: mediatek: remove unused fields in struct mtk_eint_hw
pinctrl: mediatek: use generic EINT register maps for each SoC
pinctrl: mediatek: add EINT support to MT7622 SoC
pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fit
dt-bindings: pinctrl: add external interrupt support to MT7622 pinctrl
pinctrl: freescale: Switch to SPDX identifier
pinctrl: samsung: Fix suspend/resume for Exynos5433 GPF1..5 banks
pinctrl: sh-pfc: rcar-gen3: Fix grammar in static pin comments
pinctrl: sh-pfc: r8a77965: Add I2C pin support
pinctrl: sh-pfc: r8a77990: Add EthernetAVB pins, groups and functions
pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7} pins, groups and functions
pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups and functions
pinctrl: sh-pfc: r8a77990: Add bias pinconf support
pinctrl: sh-pfc: Initial R8A77990 PFC support
...
This is the binding description of the pinctrl driver for Cirrus Logic
Madera codecs. The binding uses the generic pinctrl binding so the main
purpose here is to describe the device-specific names for groups and
functions.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Extend the capability of MT7622 pinctrl with adding EINT so that each
GPIO can be used to notify CPU when a signal state is changing on the
line as an external interrupt.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add support for the new R-Car E3 SoC,
- Add I2C pin groups on R-Car M3-N,
- Small fixes and cleanups.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJbBWP7AAoJEEgEtLw/Ve77vLQQAJUvsQkynQ415tVpxFbFi1NT
jXDunV31hShy3qyfXdxF7lDgQtfwCgho7Pyay47AERHzmK0MQFbQvfNi4631hJ50
CvfYS+/tmVQhyZYO5PiXHvQ5JvgpWa1RlstWDaVQP2O311kj635JdoDkIdYzUjZL
/9hW8S/CAhmzrKb3tSlmW652bwX/6FKGXrLF4p49DXx+57yTZ6ORD5GkKGbCmD9Z
cO/tPmjtAWkpdR9MXKInu7pwMSakycrtJdtx1tOx4DJ5L9WCP75LawwcbUVmbuQZ
Pdjdz9hbndNHaCpj9jsSUYIeZ/1K0eqDj/X8Hjr5DxWugDKzl2u45U2BnSkyCFRL
xLqqmhQR4LCCl1sKioxJa+Fv6aUmr9KFpqdlX20EiiPwfTnpVd22ClAfqQ5IGs3w
u7i7fAaaeDf0cFS/I/8+0RZQp5DZgh/z2mTREwIJ7VFTQCqXWpDM1YTBl0W0k4k/
Nl5WveFYaSIqbXgRyYWBjuALrMAZXsYvRax1UZLEVW4nYWl26GOfKA3i30clc8uG
vluvV4glI3tWK/WLBoKYW2gItCDPhj3b72+U8A4pf8yBi4I9tOL+bcq3Ze2v6M66
yGPzJ7kjQMyy4i3dyGuwOwXVy1CsNHRc1Gcm1vwcShNNrhlz7eKq8A+uDHoybPpD
uwcI1s+/Jqfw+7WUufIQ
=xeSy
-----END PGP SIGNATURE-----
Merge tag 'sh-pfc-for-v4.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.18 (take two)
- Add support for the new R-Car E3 SoC,
- Add I2C pin groups on R-Car M3-N,
- Small fixes and cleanups.
This patch adds initial pinctrl driver to support for the R8A77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
There are 4 banks (GPIO0 ~ GPIO3), bank0 is in PD_PMU
subsystem, bank1/bank2/bank3 are in PD_BUS subsystem.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
which controls the PL and PM pin banks.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Meson8m2 SoC is a variant of Meson8 with some updates from Meson8b
(such as the Gigabit capable DesignWare MAC).
It is mostly pin compatible with Meson8, only 10 (existing) CBUS pins
get an additional function (four of these are Ethernet RXD2, RXD3, TXD2
and TXD3 which are required when the board uses an RGMII PHY).
The AOBUS pins seem to be identical on Meson8 and Meson8m2.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
