The compatible should be "renesas,pwm-rcar", and one the the SoC
specific string. So, this patch revises the documentation.
Reported-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
The PWM controller on sun5i SoCs is identical to the one found on sun7i
SoCs. On the A13 package only one of the 2 pins is routed to the outside,
so only advertise one PWM channel there.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Document the device-tree binding of MediaTek display PWM. The PWM has
one channel to control the backlight brightness for display. Both the
MT8173 and MT6595 are supported.
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Add a binding documentation for the Broadcom BCM7038 PWM controller found in
BCM7xxx chips.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Add DT binding documentation for the Berlin PWM controller.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Not much has been happening in PWM land lately, so this contains mostly
minor fixes that didn't seem urgent enough for a late pull-request last
cycle.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJVOOwlAAoJEN0jrNd/PrOhrh4P/RqehL4BADO9PelU58wcudc4
gjyk93HNobhJmTPnvl6/GflYhqtRn/KQL0PoA7aeg+mDJ311d11JpDABBpd4iRmT
djvzhekkVtEXfI0TzFjI/RQ78KjN5Zbs39qNIsFQW9IO2nQgAqiprzPqvttN0ZHG
BMMU6ZCbzDX2TcCDntM59SS2EEoCQ0rPswFkYykiDcslql1IIKlziY6MGw6LFdWO
WKeRA6vKDAMrv2kcZy55kg5ONamAN1VYmJUeEf0tuSOqcPLT8i4xf9oj+TxySWn2
56y/Kw7ZRCmHHRvAnjUyfZKxaXy3Dxl7H3Wk/qz51EYXKwxPQoXpXUHpkNOhHuVY
SVvQ3j6AAe+6Te/pds87STuLRsiFFwVchAvCftF1DIDZyUgxzTJzUz8viJGe7Urk
OSoQWTMINsCRc/sgSHFf9ZtmLATTO+0L98N980bKTAKng2P/pp/ZbhArHwGLsrYD
ofNYj9YCO7ZE0zdM/V0cyW2OCrl8qwSSA2Kt97XN8YVWdJXXFxjMXdSS+llWrZVm
usTk9fB9vJWhmP7ILnFsQ4+v06fwq4+t/ggXPK6l6+GQx91W6WYdo2/x1rq27UnJ
o4zK1K7ClW2K+Xfag/nRXJOPOBPis9V19J/vKi0EbV9QFyUH2VW87hbqVncOP2ue
tv+KHMkKgqqoc8/3GCFK
=X+q2
-----END PGP SIGNATURE-----
Merge tag 'pwm/for-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
Pull pwm changes from Thierry Reding:
"Not much has been happening in PWM land lately, so this contains
mostly minor fixes that didn't seem urgent enough for a late
pull-request last cycle"
* tag 'pwm/for-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
pwm: Remove __init initializer for pwm_add_table()
pwm: samsung: Fix output race on disabling
pwm: mxs: Fix period divider computation
pwm: atmel-hlcdc: Add errata handling for sama5d4
pwm: pca9685: Constify struct regmap_config
pwm: imx-pwm: add explicit compatible strings and required clock properties
This patchset attempts to standardize the naming of dt-bindings
documents based on the Broadcom vendor prefix of brcm.
Although there are no guidelines currently present for how to name
the dt-bindings document the "vendor,binding.txt" style is in use by
some of the other vendors.
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Gregory Fong <gregory.0xf0@gmail.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Rob Herring <robh@kernel.org>
The imx-pwm binding contains language indicating compatible strings to
be used that is not valid for all supported parts e.g. Should be
"fsl,<soc>-pwm". Fix this by enumerating the valid compatible strings
that represent the two versions of this peripheral in use.
The binding is also missing the clocks/clock-names properties so
document these, the two required ipg and per clocks, and add these
properties to the example.
Signed-off-by: Matt Porter <mporter@konsulko.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This contains two new drivers, one for Allwinner SoCs and the other for
Imagination Technologies' Pistachio SoC.
Complementing this are a couple of fixes to the Atmel HLCDC PWM and STi
PWM drivers as well as minor cleanups to the core and the Tegra driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJU5EPtAAoJEN0jrNd/PrOhqRcQAJSxA7/HVzyEOSphpmysTwnh
gu1++iaFw0LTJ/OcoA3i6oesmbZ+W0QhEZEflEEXuQriAT/U0scC9sKcxz3iBWc3
T1+S3V8CF3ZXjo9Tuurihf/QsfrwrMwge4CQUZfdpRjgD3yiiFx9+U6NwBNmtYix
C1BhR9ybHU16LUuYWct3iS1kjwW/eGx/FLYuW46dYHjcYrAlMEXCZWFhKbgZpnl7
AF6Wap2CWBrFLuftsz6kXy/w8MMx8jZXoUpWlCOs1bY2xJTjOGjkzijs6fHTv+dU
+AvjoOAzsDVEsi6QYoVrNh6XvjpG/VQuk0DKQ3/OZBrKtRLFsrDD3uB5+yYg5Liv
/b6/vNNL64qKrM8677PzoprjdgInCnN2EFxass4al6l9bC7IxCHRwutz+dKSfBy7
KUqOghl1cQEPxyXly4NGo4Z4pC/S03xmghfBcgdk6yulpEnV/GXPZzzyrikFqcYQ
TY03BP1nJ1fkGN42kYZYkdefUOBzybEAT2q9Zq3SgVoexkgDNa1vKo4NEHbZmjYt
Kz1QT1cz/en2Cp2snLSMPsidgr9YaXB6Lrl6YlLHEtG04f0Ey3/iJpMm9VAy5dEv
fDgavey1OOM5qzMJv0zaK73gE8xFSqD0sV5tbig6IW1KFoICD2+mfgAnjuB17xEm
RbLSMs2uuBJ3N2oO43HR
=3uQb
-----END PGP SIGNATURE-----
Merge tag 'pwm/for-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
Pull pwm updates from Thierry Reding:
"This contains two new drivers, one for Allwinner SoCs and the other
for Imagination Technologies' Pistachio SoC.
Complementing this are a couple of fixes to the Atmel HLCDC PWM and
STi PWM drivers as well as minor cleanups to the core and the Tegra
driver"
* tag 'pwm/for-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
pwm: tegra: Use NSEC_PER_SEC
pwm: Remove unnecessary check before of_node_put()
pwm: Add device tree binding document for IMG PWM DAC
pwm: Imagination Technologies PWM DAC driver
pwm: sti: Maintain a bitmap of configured devices
pwm: sunxi: document OF bindings
pwm: Add Allwinner SoC support
pwm: atmel-hlcdc: Prevent division by zero
pwm: atmel-hlcdc: Depend on HAVE_CLK
Align compatible strings for several IP blocks present on Tegra chips
with the latest doctrine from the DT maintainers:
http://marc.info/?l=devicetree&m=142255654213019&w=2
The primary objective here is to avoid checkpatch warnings, per:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
DT binding text files have been updated for the following IP blocks:
- PCIe
- SOR
- SoC timers
- AHB "gizmo"
- APB_MISC
- pinmux control
- UART
- PWM
- I2C
- SPI
- RTC
- PMC
- eFuse
- AHCI
- HDA
- XUSB_PADCTRL
- SDHCI
- SOC_THERM
- AHUB
- I2S
- EHCI
- USB PHY
N.B. The nvidia,tegra20-timer compatible string is removed from the
nvidia,tegra30-timer.txt documentation file because it's already
mentioned in the nvidia,tegra20-timer.txt documentation file.
This second version takes into account the following requests from
Rob Herring <robherring2@gmail.com>:
- Per-IP block patches have been combined into a single patch
- Explicit documentation about which compatible strings are actually
matched by the driver has been removed. In its place is implicit
documentation that loosely follows Rob's prescribed format:
"Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where
<chip> is tegra30, tegra132, ..." [...] "You should attempt to
document known values of <chip> if you use it"
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Dylan Reid <dgreid@chromium.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Jingchang Lu <jingchang.lu@freescale.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mikko Perttunen <mperttunen@nvidia.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Peter Hurley <peter@hurleysoftware.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Tejun Heo <tj@kernel.org>
Cc: "Terje Bergström" <tbergstrom@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-pwm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
This is the documentation for the Allwinner SoCs PWM bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
The HLCDC IP available in some Atmel SoCs (i.e. at91sam9x5, at91sam9n12
or sama5d3 families for instance) provides a PWM device.
The DT bindings used for this PWM device is following the default 3 cells
bindings described in Documentation/devicetree/bindings/pwm/pwm.txt.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
The rk3288 has the ability to invert the polarity of the PWM. Let's
enable that ability. Note that this increases pwm_cells to 3 for
rk3288.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Caesar Wang <caesar.wang@rock-chips.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
The same FTM PWM device can have a different endianness on different
SoCs. The device tree provides a property to describing this so that an
operating system device driver can handle all variants of the device.
Refer to the table below for the endianness of the FTM PWM block as
integrated into the existing SoCs:
SoC | FTM-PWM endianness
--------+-------------------
Vybrid | LE
LS1 | BE
LS2 | LE
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Document new compatible for PWM founding on RK3288 SoC
Signed-off-by: Caesar Wang <caesar.wang@rock-chips.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Ajit Pal Singh <ajitpal.singh@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Add the binding description for the Kona PWM controller found on Broadcom's
mobile SoCs.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Add a new driver for the ARM CLPS711X Pulse Width Modulator (PWM) interface.
This CPU contain two 4-bit PWM outputs with constant period, based on CPU
PLL frequency. PWM polarity is determined by hardware by power on reset.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This adds the binding documentation for Freescale FlexTimer Module
(FTM) PWM driver under Documentation/devicetree/bindings/pwm/.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Yuan Yao <yao.yuan@freescale.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
The patches for this release cycle include various enhancements (device
tree support, better compile coverage, ...) for existing drivers. There
is a new driver for Atmel SoCs.
Various drivers as well as the sysfs support received minor fixes and
cleanups.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJS5m3bAAoJEN0jrNd/PrOhukQP/RdjGTUc8McrOt6pU20xKedI
Sg2HfA77ODWb1T8iigO31qOfCzEhtpl15AZ9kpj6sgLP17PQAlMBQWxQO9iHwRIv
GSGCW8RoWq1yvMImBn6LswR6a+aczsbI46z9kMvBGAsl58AETjR82dxH/nuJ6CVw
cTUIaysmnOhDCidPBSQ2JG/TrmAqhM1wmaixv/39LtIt3pFC5XKoj5rQqPlLKVrZ
r87ZvwKdoX9z87L1gDOxybGOhcKJOKU8Qc8MlQjYzIUzwd91V7fsGF+98RB7e1k2
+I/U0YYRFVfLIc2xxHtQZe80khhWTAOEkzvVOS7jgoXI41AlIlT6rOQnRCuMRniv
YfPTMAQDln+npDEZ4xgdB6qUHIUtduNm2sfL6hWox8xG3Z8Wk5b2IlyBx+kwhSwY
MiM6UZjuENi+XjO/Ea+oJtD6CJ+U48g++mrQhB+BY1IzmEmIeMH6Qut5I0grotjm
qgjw+hEoFL9lJ190OXM9Fxu8aoDcGCIWS/UtXTG8q+V/jBmMeBvqj2jscnrMsZXF
3CTpIquKIHe83A8CLdD0AXauE4TJ/8Eh0zY+jEJzBNDgIFkqZJPIVrmwPgMCFz5O
2Vux3WDxIqXDYJ1RjKeNGUFEfnRPa1PUqc2un9512xJkthXQD4EYE9/P+/MOVGXX
UJoi2MMv4Cmkbs+bMTns
=Rq3R
-----END PGP SIGNATURE-----
Merge tag 'pwm/for-3.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
Pull pwm changes from Thierry Reding:
"The patches for this release cycle include various enhancements
(device tree support, better compile coverage, ...) for existing
drivers. There is a new driver for Atmel SoCs.
Various drivers as well as the sysfs support received minor fixes and
cleanups"
* tag 'pwm/for-3.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
pwm: tiecap: Remove duplicate put_sync call
pwm: tiehrpwm: use dev_err() instead of pr_err()
pwm: pxa: remove unnecessary space before tabs
pwm: ep93xx: split module author names
pwm: use seq_puts() instead of seq_printf()
pwm: atmel-pwm: Do not unprepare clock after successful registration
of: Add Atmel PWM controller device tree binding
pwm: atmel-pwm: Add Atmel PWM controller driver
backlight: pwm_bl: Remove error message upon devm_kzalloc() failure
pwm: pca9685: depends on I2C rather than REGMAP_I2C
pwm: renesas-tpu: Enable driver compilation with COMPILE_TEST
pwm: jz4740: Use devm_clk_get()
pwm: jz4740: Pass device to clk_get()
pwm: sysfs: Convert to use ATTRIBUTE_GROUPS macro
pwm: pxa: Add device tree support
This is the branch where we usually queue up cleanup efforts, moving
drivers out of the architecture directory, header file restructuring,
etc. Sometimes they tangle with new development so it's hard to keep it
strictly to cleanups.
Some of the things included in this branch are:
* Atmel SAMA5 conversion to common clock
* Reset framework conversion for tegra platforms
- Some of this depends on tegra clock driver reworks that are shared with Mike
Turquette's clk tree.
* Tegra DMA refactoring, which are shared branches with the DMA tree.
* Removal of some header files on exynos to prepare for multiplatform
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJS4Vf7AAoJEIwa5zzehBx3f9UP/jwMlbfbSZHfNQ/QG0SqZ9RD
zvddyDMHY/qXnzgF3Dax+JR9BDDVy8AlQe713FCoiHJZggWRAbbavkx8gxITDrZQ
6NYaEkkuVxqyM8APl3PwMqYm8UZ8MUf4lCltlOA4jkesY9vue91AFnfyKh2CvHrn
Leg4XT6mFzf/vYDL6RbvTz/Qr253uv3KvYBxkeiRNa0Y7OXRemEXSOfgxh0YGxUl
LZ2IWQFOh/DH4kaeQI8V4G67X3ceHiFyhCnl0CPwfxaZaNBVaxvIFgIUTdetS6Sb
zcXa029tE/Dfsr55vZAv9LUHEipCSOeE5rn2EJWehTWyM7vJ42Eozqgh+zfCjXS7
Ib6g2npsvIluQit/RdITu44h5yZlrQsLgKTGJ8jjXqbT4HQ/746W8b/TP0YLtbw7
N8oqr7k4vsZyF0dAYZQtfQUZeGISz67UbFcdzl9tmYOR7HFuAYkAQYst77zkVJf8
om59BAYYTG5FNjQ4I9AKUfJzxXYveI6AKpXSCCZiahpFM2D1CJIzp9Wi0GwK1HRR
sFVWhS0dajvz63pVVC2tw5Sq4J7onRRNGIXFPoE5fkmlelm0/q0zzGjw3Z0nTqbZ
8zxuwuy2FfPJK11GbUAIhAgn1sCLYyAhl6IE+FsanGeMOSGIMrH0v5/HphAxoCXt
BvqMDogyLoGPce1Gm3pJ
=3CcT
-----END PGP SIGNATURE-----
Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson:
"This is the branch where we usually queue up cleanup efforts, moving
drivers out of the architecture directory, header file restructuring,
etc. Sometimes they tangle with new development so it's hard to keep
it strictly to cleanups.
Some of the things included in this branch are:
* Atmel SAMA5 conversion to common clock
* Reset framework conversion for tegra platforms
- Some of this depends on tegra clock driver reworks that are shared
with Mike Turquette's clk tree.
* Tegra DMA refactoring, which are shared branches with the DMA tree.
* Removal of some header files on exynos to prepare for
multiplatform"
* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits)
ARM: mvebu: move Armada 370/XP specific definitions to armada-370-xp.h
ARM: mvebu: remove prototypes of non-existing functions from common.h
ARM: mvebu: move ARMADA_XP_MAX_CPUS to armada-370-xp.h
serial: sh-sci: Rework baud rate calculation
serial: sh-sci: Compute overrun_bit without using baud rate algo
serial: sh-sci: Remove unused GPIO request code
serial: sh-sci: Move overrun_bit and error_mask fields out of pdata
serial: sh-sci: Support resources passed through platform resources
serial: sh-sci: Don't check IRQ in verify port operation
serial: sh-sci: Set the UPF_FIXED_PORT flag
serial: sh-sci: Remove duplicate interrupt check in verify port op
serial: sh-sci: Simplify baud rate calculation algorithms
serial: sh-sci: Remove baud rate calculation algorithm 5
serial: sh-sci: Sort headers alphabetically
ARM: EXYNOS: Kill exynos_pm_late_initcall()
ARM: EXYNOS: Consolidate selection of PM_GENERIC_DOMAINS for Exynos4
ARM: at91: switch Calao QIL-A9260 board to DT
clk: at91: fix pmc_clk_ids data type attriubte
PM / devfreq: use inclusion <mach/map.h> instead of <plat/map-s5p.h>
ARM: EXYNOS: remove <mach/regs-clock.h> for exynos
...
Bindings for LP3943 MFD, GPIO and PWM controller are added.
Signed-off-by: Milo Kim <milo.kim@ti.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The Atmel PWM controller uses the standard device tree bindings for PWM
controllers.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Update all the Tegra DT bindings to require resets/reset-names properties
where the HW module has reset inputs. Remove any entries from clocks or
clock-names that were only required to identify reset inputs, rather than
referring to real clocks.
This is a DT-ABI-incompatible change. It is the first of two changes
required for me to consider the Tegra DT bindings as stable, the other
being conversion to the common DMA DT bindings.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
Many of the Tegra DT binding documents say nothing about the clocks or
clock-names properties, yet those are present and required in DT files.
This patch simply updates the documentation file to match the implicit
definition of the binding, based on real-world DT content.
All Tegra bindings that mention clocks are updated to have consistent
wording and formatting of the clock-related properties.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
This patch adds device tree support to the PXA's PWM driver. Nothing
needs to be extracted from the device tree node by the PWM device.
Client devices need only specify the period; the per-chip index is
implicitly zero because one device node must be present for each PWM
output in use. This approach is more convenient due to the wide
variability in the number of PWM channels present across the various PXA
variants, and is made possible by the fact that the register sets for
each PWM channel are segregated from each other. An of_xlate() method
is added to parse this single-cell node. The existing ID table is
reused for the match table data.
Tested on a Palm Treo 680 (both platform data and DT cases).
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
patches, both new drivers and fixes to existing. A high percentage of
these are for Samsung platforms like Exynos. Core framework fixes and
some new features like automagical clock re-parenting round out the
patches.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJSLkImAAoJEDqPOy9afJhJOjsP/Ri26AW7XB9pPWJRSU9REBZA
31wxcFo2T+PNir9duwDwjFBFycC3MisaKFlg7D134M+7txbYqm1TRvfu9OEDxpSP
4b/Yl6TarN4dhCN2R+BREO8PnxCBVpspDcsdh6Esuwuet2xUom3UtN8yvSjhPP/u
qGNmXQYXyQy4fom5r+GsDVW+HIhLkaX9b0fYc9EN/bqfgv94PMZAxAxsK9CroAGZ
0m0g9ZXw9iSvVfz+iQEqPINtvpTLHk0FGyimoSR7kvW4o4o47tVtLEWp7VjG6mr5
zvBsycaQq6NgxPu96iUWWhsO9Uj2I7/7JgidXF7r+wvEFs1mcgZtkkirSA/n4zUN
C8a87rvQrZRLr+xXhVuqiVHCgCY8vXoHqkWg6SrZ62ORL8C7uYRpog5SEe2ZzLJX
l5uGAsDM6el+Uc/YviCPoZbeFr3h3CQvvFo8+i2eN0v/Phf30rq4lotBvpQj894G
ngEIMj+D8wshdYSF2dNJ0rLnkLHTgCbiA28L6Cl5TRzRMj3Uaj9aT3cmoLUnimZu
7F7nWU4Iu/vzQKCTQ+eTvwxXJqIlE0JeVbJilqH1f2a68JdXP1LOId+2w/CP8gqQ
i2odj6JHMgBzM9rNs+y0Ir9X/bXIVi6F341c19Nl15srEiLLl8xQIpcPDaI/Kvzs
pefYgF2yS5AZAW3ac90r
=5GfA
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux
Pull clock framework changes from Michael Turquette:
"The common clk framework changes for 3.12 are dominated by clock
driver patches, both new drivers and fixes to existing. A high
percentage of these are for Samsung platforms like Exynos. Core
framework fixes and some new features like automagical clock
re-parenting round out the patches"
* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
clk: only call get_parent if there is one
clk: samsung: exynos5250: Simplify registration of PLL rate tables
clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
clk: samsung: exynos4: Register PLL rate tables for Exynos4210
clk: samsung: exynos4: Reorder registration of mout_vpllsrc
clk: samsung: pll: Add support for rate configuration of PLL46xx
clk: samsung: pll: Use new registration method for PLL46xx
clk: samsung: pll: Add support for rate configuration of PLL45xx
clk: samsung: pll: Use new registration method for PLL45xx
clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
clk: samsung: exynos4: Remove checks for DT node
clk: samsung: exynos4: Remove unused static clkdev aliases
clk: samsung: Modify _get_rate() helper to use __clk_lookup()
clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
clocksource: samsung_pwm_timer: Get clock from device tree
ARM: dts: exynos4: Specify PWM clocks in PWM node
pwm: samsung: Update DT bindings documentation to cover clocks
clk: Move symbol export to proper location
clk: fix new_parent dereference before null check
clk: wm831x: Initialise wm831x pointer on init
...
PWM driver consumes at least one and up to three clocks, which need to be
specified in device tree when used. This patch updates bindings
documentation to add information about clocks.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Specify DT bindings for the TPU PWM controller and add OF support to the
driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
The PWM client cells format is documented in the generic pwm.txt
documentation and duplicated in all PWM driver bindings. Remove
duplicate information and reference pwm.txt instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Define a PWM_POLARITY_INVERTED macro in include/dt-bindings/pwm/pwm.h to
be used by device tree sources.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Add pwm driver for the NXP pca9685 16 channel pwm-led controller.
The driver is really barebones at this stage. E.g. the OE' pin and
therefore the corresponding registers are not supported.
The driver was tested on a HW where this pin is tied to GND.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
[thierry.reding@gmail.com: style and whitespace cleanups]
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
These continue the multiplatform support for exynos, adding support
for building most of the essential drivers (clocksource, clk, irqchip)
when combined with other platforms. As a result, it should become
really easy to add full multiplatform exynos support in 3.11, although
we don't yet enable it for 3.10.
The changes were not included in the earlier multiplatform series
in order to avoid clashes with the other Exynos updates.
This also includes work from Tomasz Figa to fix the pwm clocksource
code on Exynos, which is not strictly required for multiplatform,
but related to the other patches in this set and needed as a bug
fix for at least one board.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAUYgmgWCrR//JCVInAQIp6A//cb87A7biCHo0hd64v7RtX2dIvYTc8ZDh
7O9yH7NuAtbSI7FF7cVQGGK6nCRqmwO2SM/KLFgbt2MF36FLgQKKZhJIDM/qB4jb
3DCHHH814eqExf4MFfZL4Yxl4FaMqxzSwYX8fD28GmpeVxLeHjh0yQCKmPejz5MW
WgkMcBJS3IPqbhhKMcMZmXteLrEzEm43Uj6dxkZP7RbinyuWzHvx3IWWv4gQ6ITz
3jcCvZC5JWBo9MEPH43vlmOd8qsAn0OvkbtbYiy2Tre5VerqOgbEEXU2U0A2zUSj
YTmRvwIGsIylL2EkVsJTkMj8KJ8TAHZjHyNUY8m2UzWuS+9EdZjf6rXeKIdUz9Wa
0dmiWJEOEvejk0RnHEJm7anmKp7a9YHFkFSRnHbLOAXAMkUZWWcVAMZ4UbDK8RtF
RX6R+ga9tR8R7aBLIzqYyfSHaZ7xUpF6nSBOM4GNVNKtViJv3PENWVQrm2GHcQ9w
+4IMUqXO/5IRvuHW93l+oN8tENDTF0cR0+S7t0R6Vuuh7OebRt9TAE421Hrvt+7p
gI5tvhEeV3o1CMmXWod8X1jxY/1OrONG7wX/x07ymiRnXSd+sZ0CPkYyWultKNw8
bCAsnOP2aFpO1RB0XEC5y8FZ5uSfcQ7Ngu2kyAP7mEXV6qbSHgmb+lyxf2G8ftL2
Rn0M7nbLcz4=
=FY7+
-----END PGP SIGNATURE-----
Merge tag 'multiplatform-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull late ARM Exynos multiplatform changes from Arnd Bergmann:
"These continue the multiplatform support for exynos, adding support
for building most of the essential drivers (clocksource, clk, irqchip)
when combined with other platforms. As a result, it should become
really easy to add full multiplatform exynos support in 3.11, although
we don't yet enable it for 3.10.
The changes were not included in the earlier multiplatform series in
order to avoid clashes with the other Exynos updates.
This also includes work from Tomasz Figa to fix the pwm clocksource
code on Exynos, which is not strictly required for multiplatform, but
related to the other patches in this set and needed as a bug fix for
at least one board."
* tag 'multiplatform-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits)
ARM: dts: exynops4210: really add universal_c210 dts
ARM: dts: exynos4210: Add basic dts file for universal_c210 board
ARM: dts: exynos4: Add node for PWM device
ARM: SAMSUNG: Do not register legacy timer interrupts on Exynos
clocksource: samsung_pwm_timer: Work around rounding errors in clockevents core
clocksource: samsung_pwm_timer: Correct programming of clock events
clocksource: samsung_pwm_timer: Use proper clockevents max_delta
clocksource: samsung_pwm_timer: Add support for non-DT platforms
clocksource: samsung_pwm_timer: Drop unused samsung_pwm struct
clocksource: samsung_pwm_timer: Keep all driver data in a structure
clocksource: samsung_pwm_timer: Make PWM spinlock global
clocksource: samsung_pwm_timer: Let platforms select the driver
Documentation: Add device tree bindings for Samsung PWM timers
clocksource: add samsung pwm timer driver
irqchip: exynos: look up irq using irq_find_mapping
irqchip: exynos: pass irq_base from platform
irqchip: exynos: localize irq lookup for ATAGS
irqchip: exynos: allocate combiner_data dynamically
irqchip: exynos: pass max combiner number to combiner_init
ARM: exynos: add missing properties for combiner IRQs
...
This patch adds missing documentation describing Device Tree bindings
for Samsung PWM timers.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Update binding document of pwm-tiehrpwm to reflect the usage of similar
modules in da850 and am3xx SOCs.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Update binding document of pwm-tiecap to reflect the usage of similar
modules in da850 and am3xx SOCs.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Add support to set polarity on PWM devices, allowing for inverted
duty cycles.
Also update the binding document to #pwm-cells = <3> to allow
passing the flags from devicetree.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
This patch adds a PWM driver based on Atmel Timer Counter Block. The
Timer Counter Block is used in Waveform generator mode.
A Timer Counter Block provides up to 6 PWM devices grouped by 2:
* group 0 = PWM 0 and 1
* group 1 = PWM 2 and 3
* group 2 = PMW 4 and 5
PWM devices in a given group must be configured with the same period
value. If a PWM device in a group tries to change the period value and
the other device is already configured with a different value an error
will be returned.
This driver requires device tree support. The Timer Counter Block number
used to create a PWM chip is given by the tc-block field in an
"atmel,tcb-pwm" compatible node.
This patch was tested on kizbox board (at91sam9g20 SoC) with pwm-leds.
Signed-off-by: Boris BREZILLON <linux-arm@overkiz.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
The driver supports the following LED outputs as generic PWM driver:
TWL4030 LEDA and LEDB (PWMA and PWMB)
TWL6030 Charging indicator LED (PWM LED)
On TWL6030 when the PWM requested LED is configured to be controlled by SW.
In this case the user can enable/disable and set the duty period freely.
When the PWM has been freed, the LED driver is put back to HW control.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
The driver supports the following PWM outputs:
TWL4030 PWM0 and PWM1
TWL6030 PWM1 and PWM2
On TWL4030 the PWM signals are muxed. Upon requesting the PWM the driver
will select the correct mux so the PWM can be used. When the PWM has been
freed the original configuration is going to be restored.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
This patch
1. Add support for device-tree binding for EHRWPM driver.
2. Set size of pwm-cells set to 3 to support PWM channel number, PWM
period & polarity configuration from device tree.
3. Add enable/disable clock gating in PWM subsystem common config space.
4. When here set .owner member in platform_driver structure to
THIS_MODULE.
Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
This patch
1. Add support for device-tree binding for ECAP APWM driver.
2. Set size of pwm-cells set to 3 to support PWM channel number, PWM
period & polarity configuration from device tree.
3. Add enable/disable clock gating in PWM subsystem common config space.
4. When here set .owner member in platform_driver structure to
THIS_MODULE.
Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
In some platforms (like am33xx), PWM sub modules (ECAP, EHRPWM, EQEP)
are integrated to PWM subsystem. These PWM submodules has resources
shared and only one register bit-field is provided to control
module/clock enable/disable, makes it difficult to handle common
resources from independent PWMSS submodule drivers.
So the solution here implemented in this patch is, to create driver for
PWMSS and take the role of parent driver for PWM submodules. PWMSS
parent driver enumerates all the child nodes under PWMSS module. Also
symbol "pwmss_submodule_state_change" exported to enable clock gating
for individual PWMSS submodules, and submodule drivers has to enable
clock gating from their drivers.
As this is only supported during DT boot, the parent/child relationship
is created and populated in DT execution flow. The only required change
is inside DTS file, making EHRPWM & ECAP as a child to PWMSS node.
Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Add support for encoding PWM properties in bit encoded form with
of_pwm_xlate_with_flags() function support. Platforms require platform
specific PWM properties has to populate in 3rd cell of the pwm-specifier
and PWM driver should also set .of_xlate support with this function.
Currently PWM property polarity encoded in bit position 0 of the third
cell in pwm-specifier.
Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
