Commit Graph

47 Commits

Author SHA1 Message Date
Andy Shevchenko
fe55d73238 mfd: intel-lpss: Provide an SSP type to the SPI driver
The SPI driver wants to know the exact type of the controller.
Provide this information to it. This is a complementary part to
the previously updated intel-lpss-acpi.c.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20220702211903.9093-1-andriy.shevchenko@linux.intel.com
2022-09-28 16:09:48 +01:00
Andy Shevchenko
37e8ba74d1 mfd: intel-lpss: Add Intel Meteor Lake-P PCI IDs
Add Intel Meteor Lake-P LPSS PCI IDs.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220628223047.34301-1-andriy.shevchenko@linux.intel.com
2022-07-19 10:54:41 +01:00
Gaggery Tsai
eeb0a442da mfd: intel-lpss: Add support for ADL-P i2c6 and i2c7
Added 8086:51d8 and 8086:51d9 to the intel_lpss_pci driver. They are
Intel Alder Lake-P i2c controllers.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220520193537.26090-1-gaggery.tsai@intel.com
2022-05-23 14:08:45 +01:00
Jarkko Nikula
8c70bd5802 mfd: intel-lpss: Add Intel Raptor Lake PCH-S PCI IDs
Add Intel Raptor Lake PCH-S LPSS PCI IDs.

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220211145055.992179-1-jarkko.nikula@linux.intel.com
2022-03-08 09:44:06 +00:00
Hans de Goede
e6b142060b mfd: intel-lpss: Fix I2C4 not being available on the Microsoft Surface Go & Go 2
Many DSDTs for Kaby Lake and Kaby Lake Refresh models contain a
_SB.PCI0.GEXP ACPI Device node describing an I2C attached PCA953x
GPIO expander.

This seems to be something which is copy and pasted from the DSDT
from some reference design since this ACPI Device is present even on
models where no such GPIO expander is used at all, such as on the
Microsoft Surface Go & Go 2.

This ACPI Device is a problem because it contains a SystemMemory
OperationRegion which covers the MMIO for the I2C4 I2C controller. This
causes the MFD cell for the I2C4 controller to not be instantiated due
to a resource conflict, requiring the use of acpi_enforce_resources=lax
to work around this.

I have done an extensive analysis of all the ACPI tables on the
Microsoft Surface Go and the _SB.PCI0.GEXP ACPI Device's methods are
not used by any code in the ACPI tables, neither are any of them
directly called by any Linux kernel code. This is unsurprising since
running i2cdetect on the I2C4 bus shows that there is no GPIO
expander chip present on these devices at all.

This commit adds a PCI subsystem vendor:device table listing PCI devices
where it is known to be safe to ignore resource conflicts with ACPI
declared SystemMemory regions.

This makes the I2C4 bus work out of the box on the Microsoft Surface
Go & Go 2, which is necessary for the cameras on these devices to work.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211203115108.89661-1-hdegoede@redhat.com
2021-12-29 13:17:01 +00:00
Orlando Chamberlain
9651cf2cb1 mfd: intel-lpss-pci: Fix clock speed for 38a8 UART
This device is found in the MacBookPro16,2, and as the MacBookPro16,1 is
from the same generation of MacBooks and has a UART with bxt_uart_info,
it was incorrectly assumed that the MacBookPro16,2's UART would have the
same info.

This led to the wrong clock speed being used, and the Bluetooth
controller exposed by the UART receiving and sending random data, which
was incorrectly assumed to be an issue with the Bluetooth stuff, not an
error with the UART side of things.

Changing the info to spt_uart_info changes the clock speed and makes it
send and receive data correctly.

Fixes: ddb1ada416 ("mfd: intel-lpss: Add support for MacBookPro16,2 ICL-N UART")
Signed-off-by: Orlando Chamberlain <redecorating@protonmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211124091846.11114-1-redecorating@protonmail.com
2021-11-29 13:17:00 +00:00
Ed Schaller
8b2051a1de mfd: intel-lpss: Add Intel Lakefield PCH PCI IDs
Add new IDs of the Intel Lakefield chip to the list of supported
devices.

Signed-off-by: Ed Schaller <schallee@darkmist.net>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211123180114.GA4747@darkmist.net
2021-11-29 13:16:59 +00:00
Orlando Chamberlain
ddb1ada416 mfd: intel-lpss: Add support for MacBookPro16,2 ICL-N UART
Added 8086:38a8 to the intel_lpss_pci driver. It is an Intel Ice Lake
PCH-N UART controler present on the MacBookPro16,2.

Signed-off-by: Orlando Chamberlain <redecorating@protonmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211002111449.12674-1-redecorating@protonmail.com
2021-11-05 14:40:06 +00:00
Andy Shevchenko
9fb3cad025 mfd: intel-lpss: Add Intel Alder Lake-M PCI IDs
Add Intel Alder Lake-M LPSS PCI IDs.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-06-02 10:49:58 +01:00
Heikki Krogerus
03152e35dd mfd: intel-lpss: Switch to use the software nodes
Software node was always created for the device if it was
supplied with additional device properties, so those nodes
might as well be constant.

Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-04-14 16:06:11 +01:00
Andy Shevchenko
9677e6f78f mfd: intel-lpss: Constify device property structures
There is no point to have non-constant device properties in this driver.
Thus, constify them for good.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-04-14 16:06:09 +01:00
Jarkko Nikula
c7b79a7528 mfd: intel-lpss: Add Intel Alder Lake PCH-S PCI IDs
Add Intel Alder Lake LPSS PCI IDs.

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-02-08 13:54:27 +00:00
Andy Shevchenko
f7b6732178 mfd: intel-lpss: Add Intel Alder Lake PCH-P PCI IDs
Add Intel Alder Lake LPSS PCI IDs.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-02-08 13:54:16 +00:00
Andy Shevchenko
5f039fa742 mfd: intel-lpss: Add device IDs for UART ports for Lakefield
Add PCI IDs for Lakefield to the list of supported UARTs.

Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com>
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-09-30 16:25:06 +01:00
Andy Shevchenko
bb7fcad48d mfd: intel-lpss: Add Intel Tiger Lake PCH-H PCI IDs
Intel Tiger Lake PCH-H has the same LPSS than Intel Broxton.
Add the new IDs to the list of supported devices.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-06-30 08:07:59 +01:00
Andy Shevchenko
3ea2e4eab6 mfd: intel-lpss: Add Intel Emmitsburg PCH PCI IDs
Intel Emmitsburg PCH has the same LPSS than Intel Ice Lake.
Add the new IDs to the list of supported devices.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-06-18 11:23:15 +01:00
Andy Shevchenko
9a875245f0 mfd: intel-lpss: Update LPSS UART #2 PCI ID for Jasper Lake
It appears that preliminary documentation has a typo in the ID list,
i.e. LPSS UART #2 had been advertised wrongly.

Fix the driver according to the EDS v0.9.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-05-26 10:51:20 +01:00
Jarkko Nikula
d2923aa453 mfd: intel-lpss: Fix Intel Elkhart Lake LPSS I2C input clock
Intel Elkhart Lake LPSS I2C has 100 MHz input clock instead of 133 MHz
that was our preliminary information. This will result slower I2C bus
clock when driver calculates its timing parameters in case ACPI tables
don't provide them.

Slower I2C bus clock is allowed but let's fix this to match with
reality.

While at it, keep the same default I2C device properties as Intel
Broxton since it is not known do they need any update.

Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-03-30 07:35:28 +01:00
Andy Shevchenko
4e213b45d2 mfd: intel-lpss: Add Intel Comet Lake PCH-V PCI IDs
Intel Comet Lake PCH-V has the same LPSS than Intel Kaby Lake.
Add the new IDs to the list of supported devices.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-03-30 07:35:28 +01:00
Andy Shevchenko
57b89dd220 mfd: intel-lpss: Add Intel Jasper Lake PCI IDs
Intel Jasper Lake has the same LPSS than Intel Ice Lake.
Add the new IDs to the list of supported devices.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-01-24 07:33:57 +00:00
Andy Shevchenko
dd047dce3a mfd: intel-lpss: Add Intel Comet Lake PCH-H PCI IDs
Intel Comet Lake PCH-H has the same LPSS than Intel Cannon Lake.
Add the new IDs to the list of supported devices.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-11-11 08:45:19 +00:00
Jarkko Nikula
3f31bc67e4 mfd: intel-lpss: Add default I2C device properties for Gemini Lake
It turned out Intel Gemini Lake doesn't use the same I2C timing
parameters as Broxton.

I got confirmation from the Windows team that Gemini Lake systems should
use updated timing parameters that differ from those used in Broxton
based systems.

Fixes: f80e78aa11 ("mfd: intel-lpss: Add Intel Gemini Lake PCI IDs")
Tested-by: Chris Chiu <chiu@endlessm.com>
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-11-11 08:45:01 +00:00
Andy Shevchenko
ec65b56046 mfd: intel-lpss: Add Intel Tiger Lake PCI IDs
Intel Tiger Lake has the same LPSS than Intel Broxton.
Add the new IDs to the list of supported devices.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-08-12 11:29:04 +01:00
Kai-Heng Feng
76380a607b mfd: intel-lpss: Remove D3cold delay
Goodix touchpad may drop its first couple input events when
i2c-designware-platdrv and intel-lpss it connects to took too long to
runtime resume from runtime suspended state.

This issue happens becuase the touchpad has a rather small buffer to
store up to 13 input events, so if the host doesn't read those events in
time (i.e. runtime resume takes too long), events are dropped from the
touchpad's buffer.

The bottleneck is D3cold delay it waits when transitioning from D3cold
to D0, hence remove the delay to make the resume faster. I've tested
some systems with intel-lpss and haven't seen any regression.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=202683
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-08-12 11:28:03 +01:00
Linus Torvalds
8de262531f - Core Frameworks
- Set 'struct device' fwnode when registering a new device
 
  - New Drivers
    - Add support for ROHM BD70528 PMIC
 
  - New Device Support
    - Add support for LP87561 4-Phase Regulator to TI LP87565 PMIC
    - Add support for RK809 and RK817 to Rockchip RK808
    - Add support for Lid Angle to ChromeOS core
    - Add support for CS47L15 CODEC to Madera core
    - Add support for CS47L92 CODEC to Madera core
    - Add support for ChromeOS (legacy) Accelerometers in ChromeOS core
    - Add support for Add Intel Elkhart Lake PCH to Intel LPSS
 
  - New Functionality
    - Provide regulator supply information when registering; madera-core
    - Additional Device Tree support; lp87565, madera, cros-ec, rohm,bd71837-pmic
    - Allow over-riding power button press via Device Tree; rohm-bd718x7
    - Differentiate between running processors; cros_ec_dev
 
  - Fix-ups
    - Big header file update; cros_ec_commands.h
    - Split header per-subsystem; rohm-bd718x7
    - Remove superfluous code; menelaus, cs5535-mfd, cs47lXX-tables
    - Trivial; sorting, coding style; intel-lpss-pci
    - Only remove Power Off functionality if set locally; rk808
    - Make use for Power Off Prepare(); rk808
    - Fix spelling mistake in header guards; stmfx
    - Properly free IDA resources
    - SPDX fixups; cs47lXX-tables, madera
    - Error path fixups; hi655x-pmic
 
  - Bug Fixes
    - Add missing break in case() statement
    - Repair undefined behaviour when not initialising variables; arizona-core, madera-core
    - Fix reference to Device Tree documentation; madera
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Merge tag 'mfd-next-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "Core Frameworks:
   - Set 'struct device' fwnode when registering a new device

  New Drivers:
   - Add support for ROHM BD70528 PMIC

  New Device Support:
   - Add support for LP87561 4-Phase Regulator to TI LP87565 PMIC
   - Add support for RK809 and RK817 to Rockchip RK808
   - Add support for Lid Angle to ChromeOS core
   - Add support for CS47L15 CODEC to Madera core
   - Add support for CS47L92 CODEC to Madera core
   - Add support for ChromeOS (legacy) Accelerometers in ChromeOS core
   - Add support for Add Intel Elkhart Lake PCH to Intel LPSS

  New Functionality:
   - Provide regulator supply information when registering; madera-core
   - Additional Device Tree support; lp87565, madera, cros-ec, rohm,bd71837-pmic
   - Allow over-riding power button press via Device Tree; rohm-bd718x7
   - Differentiate between running processors; cros_ec_dev

  Fix-ups:
   - Big header file update; cros_ec_commands.h
   - Split header per-subsystem; rohm-bd718x7
   - Remove superfluous code; menelaus, cs5535-mfd, cs47lXX-tables
   - Trivial; sorting, coding style; intel-lpss-pci
   - Only remove Power Off functionality if set locally; rk808
   - Make use for Power Off Prepare(); rk808
   - Fix spelling mistake in header guards; stmfx
   - Properly free IDA resources
   - SPDX fixups; cs47lXX-tables, madera
   - Error path fixups; hi655x-pmic

  Bug Fixes:
   - Add missing break in case() statement
   - Repair undefined behaviour when not initialising variables; arizona-core, madera-core
   - Fix reference to Device Tree documentation; madera"

* tag 'mfd-next-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (45 commits)
  mfd: hi655x-pmic: Fix missing return value check for devm_regmap_init_mmio_clk
  mfd: madera: Fixup SPDX headers
  mfd: madera: Remove some unused registers and fix some defaults
  mfd: intel-lpss: Release IDA resources
  mfd: intel-lpss: Add Intel Elkhart Lake PCH PCI IDs
  mfd: cs5535-mfd: Remove ifdef OLPC noise
  mfd: stmfx: Fix macro definition spelling
  dt-bindings: mfd: Add link to ROHM BD71847 Datasheet
  MAINAINERS: Swap words in INTEL PMIC MULTIFUNCTION DEVICE DRIVERS
  mfd: cros_ec_dev: Register cros_ec_accel_legacy driver as a subdevice
  mfd: rk808: Prepare rk805 for poweroff
  mfd: rk808: Check pm_power_off pointer
  mfd: cros_ec: differentiate SCP from EC by feature bit
  dt-bindings: Add binding for cros-ec-rpmsg
  mfd: madera: Add Madera core support for CS47L92
  mfd: madera: Add Madera core support for CS47L15
  mfd: madera: Update DT bindings to add additional CODECs
  mfd: madera: Add supply mapping for MICVDD
  mfd: madera: Fix potential uninitialised use of variable
  mfd: madera: Fix bad reference to pinctrl.txt file
  ...
2019-07-15 20:18:40 -07:00
Andy Shevchenko
01e4ecee03 mfd: intel-lpss: Add Intel Elkhart Lake PCH PCI IDs
Intel Elkhart Lake has the same LPSS than Intel Broxton.
Add the new IDs to the list of supported devices.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-07-02 12:11:31 +01:00
Andy Shevchenko
f88314c1e9 mfd: intel-lpss: Keep device tables sorted by ID
Easier to find and maintain if the device tables sorted by ID.
Do it here for intel-lpss MFD driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-07-02 12:11:31 +01:00
Thomas Gleixner
d2912cb15b treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-19 17:09:55 +02:00
Andy Shevchenko
dd6629073a mfd: intel-lpss: Add Intel Comet Lake PCI IDs
Intel Comet Lake has the same LPSS than Intel Cannon Lake.
Add the new IDs to the list of supported devices.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Tested-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-05-14 08:13:27 +01:00
Andy Shevchenko
16b7a09bb6 mfd: intel-lpss: Move linux/pm.h to the local header
We now using a common macro for PM operations in Intel LPSS driver,
and, since that macro relies on the definition and macro from linux/pm.h
header file, it's logical to include it directly in intel-lpss.h.
Otherwise it's a bit fragile and requires a proper ordering
of header inclusion in C files.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-02-18 09:06:52 +00:00
Mika Westerberg
a13c93b3a5 mfd: intel-lpss: Add Ice Lake PCI IDs
Intel Ice Lake has the same LPSS than Intel Cannon Lake. Add the new IDs
to the list of supported devices.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2018-07-27 08:13:24 +01:00
Jarkko Nikula
4e93a65857 mfd: intel-lpss: Fix Intel Cannon Lake LPSS I2C input clock
Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C
than Sunrisepoint which uses 120 MHz. Preliminary information was that
both share the same clock rate but actual silicon implements elevated
rate for better support for 3.4 MHz high-speed I2C.

This incorrect input clock rate results too high I2C bus clock in case
ACPI doesn't provide tuned I2C timing parameters since I2C host
controller driver calculates them from input clock rate.

Fix this by using the correct rate. We still share the same 230 ns SDA
hold time value than Sunrisepoint.

Cc: stable@vger.kernel.org
Fixes: b418bbff36 ("mfd: intel-lpss: Add Intel Cannonlake PCI IDs")
Reported-by: Jian-Hong Pan <jian-hong@endlessm.com>
Reported-by: Chris Chiu <chiu@endlessm.com>
Reported-by: Daniel Drake <drake@endlessm.com>
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: Jian-Hong Pan <jian-hong@endlessm.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2018-06-04 08:44:17 +01:00
Florian R. Hölzlwimmer
e4b91470bd mfd: intel-lpss: Add missing PCI ID for Intel Sunrise Point LPSS devices
This patch adds a missing PCI ID of the Intel Sunrise Point chipset to the Intel LPSS driver.
It fixes a bug causing the touchpad of the Lenovo Yoga 720-15 not to be recognized.
See also bug 1700657 on bugs.launchpad.net.

Many thanks to CoolStar, who found this solution!

Reported-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: Mike Schwartz <mykesx@gmail.com>
Tested-by: Björn Dahlgren <bjodah@gmail.com>
Signed-off-by: Florian R. Hölzlwimmer <git.ich@frhoelzlwimmer.de>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-09-05 08:46:01 +01:00
Andy Shevchenko
b418bbff36 mfd: intel-lpss: Add Intel Cannonlake PCI IDs
Intel Cannonlake PCH has the same LPSS than Intel Kabylake. Add the new IDs
to the list of supported devices.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-07-06 08:29:11 +01:00
Andy Shevchenko
f80e78aa11 mfd: intel-lpss: Add Intel Gemini Lake PCI IDs
Intel Gemini Lake is essentially Broxton with different PCI IDs. Add these
new PCI IDs to the list of supported devices.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-02-13 09:29:42 +00:00
Linus Torvalds
ac5a28b0d3 - New Device Support
- Add support for Ricoh RC5T619 PMIC to rn5t618
    - Add support for PM8821 PMIC to qcom-pm8xxx
 
 - New Functionality
    - Add support for GPIO to lpc_ich
    - Add support for GPADC to sun4i
    - Add ability for rk808 to shutdown
 
  - Fix-ups
    - Simplify/strip unnecessary code; tps65218, palmas, tps65217
    - Device Tree binding updates; tps65218, altera-a10sr
    - Provide/export device ID info; tps65218, axp20x-i2c, hi655x-pmic, fsl-imx25-tsadc, intel_soc_pmic_bxtwc
    - Use MFD API instead of of_platform_populate(); tps65218
    - Generalise name-space; pm8xxx
    - Supply/edit regmap configuration; axp20x, cs47l24-tables, axp20x
    - Enable compile testing; max77620,  max77686, exynos-lpass, abx500-core
    - Coding style issues; wm8994-core, wm5102-tables
    - Supply endian support; syscon
    - Remove module support; ab3100-core, ab8500-debugfs, ab8500-gpadc, abx500-core
 
 - Bug Fixes
    - Fix ordering issues; wm8994
    - Fix dependencies (build-time/run-time); exynos_lpass, sun4i-gpadc
    - Fix compiler warnings; sun4i-gpadc
    - Fix leaks; mfd-core
    - Fix page fault during module unload; tps65217
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Merge tag 'mfd-for-linus-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "New Device Support
   - Add support for Ricoh RC5T619 PMIC to rn5t618
   - Add support for PM8821 PMIC to qcom-pm8xxx

  New Functionality:
   - Add support for GPIO to lpc_ich
   - Add support for GPADC to sun4i
   - Add ability for rk808 to shutdown

  Fix-ups:
   - Simplify/strip unnecessary code; tps65218, palmas, tps65217
   - Device Tree binding updates; tps65218, altera-a10sr
   - Provide/export device ID info; tps65218, axp20x-i2c, hi655x-pmic,
     fsl-imx25-tsadc, intel_soc_pmic_bxtwc
   - Use MFD API instead of of_platform_populate(); tps65218
   - Generalise name-space; pm8xxx
   - Supply/edit regmap configuration; axp20x, cs47l24-tables, axp20x
   - Enable compile testing; max77620, max77686, exynos-lpass,
     abx500-core
   - Coding style issues; wm8994-core, wm5102-tables
   - Supply endian support; syscon
   - Remove module support; ab3100-core, ab8500-debugfs, ab8500-gpadc,
     abx500-core

  Bug Fixes:
   - Fix ordering issues; wm8994
   - Fix dependencies (build-time/run-time); exynos_lpass, sun4i-gpadc
   - Fix compiler warnings; sun4i-gpadc
   - Fix leaks; mfd-core
   - Fix page fault during module unload; tps65217"

* tag 'mfd-for-linus-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (49 commits)
  mfd: tps65217: Support an interrupt pin as the system wakeup
  mfd: tps65217: Make an interrupt handler simpler
  mfd: tps65217: Update register interrupt mask bits instead of writing operation
  mfd: tps65217: Specify the IRQ name
  mfd: tps65217: Fix page fault on unloading modules
  mfd: palmas: Remove redundant check in palmas_power_off
  mfd: arizona: Disable IRQs during driver remove
  mfd: pm8xxx: add support to pm8821
  mfd: intel-lpss: Try to enable Memory-Write-Invalidate
  mfd: rn5t618: Add Ricoh RC5T619 PMIC support
  mfd: axp20x: Add address extension registers for AXP806 regmap
  mfd: intel_soc_pmic_bxtwc: Fix a typo in MODULE_DEVICE_TABLE()
  mfd: core: Fix device reference leak in mfd_clone_cell
  mfd: bcm590xx: Simplify a test
  mfd: sun4i-gpadc: Select regmap-irq
  mfd: abx500-core: drop unused MODULE_ tags from non-modular code
  mfd: ab8500: make sysctrl explicitly non-modular
  mfd: ab8500-gpadc: Make it explicitly non-modular
  mfd: ab8500-debugfs: Make it explicitly non-modular
  mfd: ab8500-core: Make it explicitly non-modular
  ...
2016-12-19 08:16:26 -08:00
Andy Shevchenko
85a9419a25 mfd: intel-lpss: Try to enable Memory-Write-Invalidate
Enable MWI mechanism if PCI bus master supports it.

It might be potential benefit in some cases. Documentation [1] says that
standard Memory Write might supply more current data than in the CPU modified
cache line and "trashing a line in the cache may trash some data that is more
current that in the memory line". This allows to avoid potential retries and
other performance degradation issues on the bus.

[1] PCI System Architecture, 4th edition, ISBN: 0-201-30974-2, pp.117-119.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-11-29 08:21:36 +00:00
Jarkko Nikula
2c8c34167c mfd: lpss: Fix Intel Kaby Lake PCH-H properties
There are a few issues on Intel Kaby Lake PCH-H properties added by
commit a6a576b78e09 ("mfd: lpss: Add Intel Kaby Lake PCH-H PCI IDs"):

- Input clock of I2C controller on Intel Kaby Lake PCH-H is 120 MHz not
  133 MHz. This was probably copy-paste error from Intel Broxton I2C
  properties.
- There is no default I2C SDA hold time specified which is used when
  ACPI doesn't provide it. I got information from Windows driver team
  that Kaby Lake PCH-H can use the same configuration than Intel
  Sunrisepoint PCH.
- Common HS-UART properties are not used.

Fix these by reusing the Sunrisepoint properties on Kaby Lake PCH-H.

Fixes: a6a576b78e09 ("mfd: lpss: Add Intel Kaby Lake PCH-H PCI IDs")
Reported-by: Xiang A Wang <xiang.a.wang@intel.com>
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-11-16 09:50:18 +00:00
Jarkko Nikula
c50cdd62dd mfd: intel-lpss: Add default I2C device properties for Apollo Lake
Default I2C device properties for Intel Broxton, especially SDA hold time
may not be enough on Intel Apollo Lake. These properties are used in case
we don't get timing parameters from ACPI.

The default SDA hold time for Broxton may fail with arbitration lost errors
on Apollo Lake:

  i2c_designware i2c_designware.1: i2c_dw_handle_tx_abort: lost arbitration

Fix this by using different default device properties on Apollo Lake than
Broxton.

Reported-by: Paul Liu <paul.liu@canonical.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=156181
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04 15:48:04 +01:00
Mika Westerberg
77fc5ff64f mfd: lpss: Add Intel Kaby Lake PCH-H PCI IDs
Intel Kaby Lake PCH-H has the same LPSS than Intel Sunrisepoint. Add the new
IDs to the list of supported devices.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-10-04 15:48:02 +01:00
Heikki Krogerus
f4d0526603 device property: don't bother the drivers with struct property_set
Since device_add_property_set() now always takes a copy of
the property_set, and also since the fwnode type is always
hard coded to be FWNODE_PDATA, there is no need for the
drivers to deliver the entire struct property_set. The
function can just create the instance of it on its own and
bind the properties from the drivers to it on the spot.

This renames device_add_property_set() to
device_add_properties(). The function now takes struct
property_entry as its parameter instead of struct
property_set.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2016-04-09 03:10:50 +02:00
Mika Westerberg
0343b2f4e4 mfd: intel-lpss: Pass I2C configuration via properties on BXT
I2C host controller need to be configured properly in order to meet I2C
timings specified in the I2C protocol specification. Some Intel Broxton
based machines do not have this information in the ACPI namespace (or the
boot firmware does not support ACPI at all) so we use build-in device
properties instead.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-03-16 08:50:42 +00:00
Huiquan Zhong
023269cc98 mfd: lpss: Add PCI IDs for Intel Broxton B-Step platform
Add PCI IDs for Intel Broxton B-Step platform, which have same
LPSS devices with A-Step.

Signed-off-by: Huiquan Zhong <huiquan.zhong@intel.com>
Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
cked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-03-09 12:58:53 +07:00
Andy Shevchenko
ec14c5395d mfd: intel-lpss: Pass HSUART configuration via properties
The HS-UART host controller driver needs to know certain properties like
width of the register set if it cannot get that information from ACPI or
DT. In order to support non-ACPI systems we pass this information to the
driver via device properties.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2015-12-07 02:29:24 +01:00
Mika Westerberg
028af5941d mfd: intel-lpss: Pass SDA hold time to I2C host controller driver
Intel Skylake the LPSS I2C pad circuit has internal delays that require
programming non-zero SDA hold time for the I2C host controller. If this is
not done communication to slave devices may fail with arbitration lost
errors like the one seen below taken from Lenovo Yoga 900:

  i2c_hid i2c-SYNA2B29:00: Fetching the HID descriptor
  i2c_hid i2c-SYNA2B29:00: __i2c_hid_command: cmd=20 00
  i2c_designware i2c_designware.1: i2c_dw_handle_tx_abort: lost arbitration

To fix this we follow what the Windows driver is doing and pass the default
SDA hold time of 230 ns to all Intel Skylake host controllers. This still
allows the platform to override these values by passing special ACPI
methods SSCN and FMCN.

Reported-by: Kevin Fenzi <kevin@scrye.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2015-12-07 02:29:24 +01:00
Andy Shevchenko
ff0a04a699 mfd: lpss: Add Intel Broxton PCI IDs
Intel Broxton has the same LPSS block than Intel Sunrisepoint so add
Broxton PCI IDs to the list.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-10-30 18:57:34 +00:00
Andy Shevchenko
4b45efe852 mfd: Add support for Intel Sunrisepoint LPSS devices
The new coming Intel platforms such as Skylake will contain Sunrisepoint PCH.
The main difference to the previous platforms is that the LPSS devices are
compound devices where usually main (SPI, HSUART, or I2C) and DMA IPs are
present.

This patch brings the driver for such devices found on Sunrisepoint PCH.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-07-28 09:56:47 +01:00