SST 39VF160x and 39VF320x chips use vendorname id 0x0701 and alternative
unlock addresses. Add support for them in cfi_probe.c.
Signed-off-by: Guillaume LECERF <glecerf@gmail.com>
Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Make the addresses used to enter Auto Select Mode variable to leave place
for handling chips using non-standard addresses.
Signed-off-by: Guillaume LECERF <glecerf@gmail.com>
Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Move the code to enter Auto Select Mode down to be able to use cfi->cfiq
members to add support for chips using alternative sequence / unlock
addresses.
Signed-off-by: Guillaume LECERF <glecerf@gmail.com>
Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Ensure that the flash device is in a quiescent state before rebooting.
The implementation is closely modeled after the cfi_cmdset_0001 reboot
notifier, commit 963a6fb0a0 .
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The use of a memcpy() during a spinlock operation will cause very long
thread context switch delays if the flash chip bandwidth is low and the
data to be copied large, because a spinlock will disable preemption.
For example: A flash with 6,5 MB/s bandwidth will cause under ubifs,
which request sometimes 128 KiB (the flash erase size), a preemption delay of
20 milliseconds. High priority threads will not be served during this
time, regardless whether this threads access the flash or not. This behavior
breaks real time.
The patch changes all the use of spin_lock operations for xxxx->mutex
into mutex operations, which is exact what the name says and means.
I have checked the code of the drivers and there is no use of atomic
pathes like interrupt or timers. The mtdoops facility will also not be used
by this drivers. So it is dave to replace the spin_lock against mutex.
There is no performance regression since the mutex is normally not
acquired.
Changelog:
06.03.2010 First release
26.03.2010 Fix mutex[1] issue and tested it for compile failure
Signed-off-by: Stefani Seibold <stefani@seibold.net>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Move MANUFACTURER_MACRONIX and MANUFACTURER_SST definitions to the
include/linux/mtd/cfi.h header file and rename them to CFI_MFR_MACRONIX and
CFI_MFR_SST.
All references in drivers/mtd/chips/cfi_cmdset_0002.c are updated to reflect
this.
Signed-off-by: Guillaume LECERF <glecerf@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
In cfi_intelext_setup and cfi_amdstd_setup, mtd is never NULL.
Remove unnecessary checks.
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
In particular, several occurances of funny versions of 'success',
'unknown', 'therefore', 'acknowledge', 'argument', 'achieve', 'address',
'beginning', 'desirable', 'separate' and 'necessary' are fixed.
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Cc: Joe Perches <joe@perches.com>
Cc: Junio C Hamano <gitster@pobox.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* git://git.infradead.org/mtd-2.6: (90 commits)
jffs2: Fix long-standing bug with symlink garbage collection.
mtd: OneNAND: Fix test of unsigned in onenand_otp_walk()
mtd: cfi_cmdset_0002, fix lock imbalance
Revert "mtd: move mxcnd_remove to .exit.text"
mtd: m25p80: add support for Macronix MX25L4005A
kmsg_dump: fix build for CONFIG_PRINTK=n
mtd: nandsim: add support for 4KiB pages
mtd: mtdoops: refactor as a kmsg_dumper
mtd: mtdoops: make record size configurable
mtd: mtdoops: limit the maximum mtd partition size
mtd: mtdoops: keep track of used/unused pages in an array
mtd: mtdoops: several minor cleanups
core: Add kernel message dumper to call on oopses and panics
mtd: add ARM pismo support
mtd: pxa3xx_nand: Fix PIO data transfer
mtd: nand: fix multi-chip suspend problem
mtd: add support for switching old SST chips into QRY mode
mtd: fix M29W800D dev_id and uaddr
mtd: don't use PF_MEMALLOC
mtd: Add bad block table overrides to Davinci NAND driver
...
Fixed up conflicts (mostly trivial) in
drivers/mtd/devices/m25p80.c
drivers/mtd/maps/pcmciamtd.c
drivers/mtd/nand/pxa3xx_nand.c
kernel/printk.c
Stanse found a double unlock in get_chip. get_chip is called with
chip->mutex held and caller is responsible for unlocking it too.
Do not unlock the lock in get_chip on a fail path. This would mean
a double unlock.
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
SST 39VF160x/39VF320x and some old SST chips need a special command
sequence to enter CFI QueRY mode [1].
This patch adds the relevant sequence to cfi_qry_mode_on().
Tested with 39VF3201.
Signed-off-by: Guillaume LECERF <glecerf@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This one sits in my tree for more than two years...
Using device code found on page 12 (http://www.btdesigner.com/pdfs/M29W800D.pdf)
and unlock address from page 15 MTD subsytem happily detects ST M29W800DB
in 16-bit mode. I do believe original author used only 8-bit mode and thus
didn't hit this bug.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Erase-suspend for writing is required to avoid blocking applications
that wish to write some data (to a NOR block other than the one being
erased). Particularly, it solves some huge delays that an application
(which writes to a UBIFS) will experience if UBI attaches to empty NOR
flash. In this case the UBI background thread will erase a lot of blocks
and the application can be blocked for minutes because of the "MTD/CFI
chip lock".
This feature has been disabled for years. Maybe this was because the old
code turned it on for erase-suspend read-only chips also
(cfip->EraseSuspend & 0x1). This is wrong and corrected now.
This patch was tweaked by Norbert van Bolhuis.
Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch moves the MANUFACTURER_ST and MANUFACTURER_INTEL to the
include/linux/mtd/cfi.h header file and renames them to CFI_MFR_ST and
CFI_MFR_INTEL. CFI_MFR_ST was already present there.
All references in drivers/mtd/chips/cfi_cmdset_0001.c are updated to reflect
this.
Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch sets the MTD_POWERUP_LOCK flag for AT49BV640D and AT49BV640DT
devices, since the devices are locked when powered up and needs to be unlocked
before interfaced.
Quote datasheet; "At power-up and reset, all sectors have their Softlock
protection mode enabled.".
Tested on AVR32 hardware platform with an AT49BV640D flash device.
Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The M29W128G Numonyx flash devices are intolerant to any 0xFF command:
in the Cfi_util.c the function cfi_qry_mode_off() (that resets the device
after the autoselect mode) must have a 0xF0 command after the 0xFF command.
This fix solves also the cause of the fixup_M29W128G_write_buffer() fix,
that can be removed now.
The following patch applies to 2.6.30 kernel.
Signed-off-by: Massimo Cirillo <maxcir@gmail.com>
Acked-by: Alexey Korolev <akorolev@infradead.org>
Cc: stable@kernel.org
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
linux v2.6.31-rc6 can not detect NEC uPD29F064115.
uPD29F064115 is a 16 bit device.
datasheet:
http://www.cn.necel.com/memory/cn/download/M16062EJ2V0DS00.pdf
This applies the same fix as used for SST chips in commit
ca6f12c67e ("jedec_probe: Fix SST 16-bit
chip detection").
Signed-off-by: Hiroshi Ito <ito@mlb.co.jp>
Cc: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Due to problems at cam.org, my nico@cam.org email address is no longer
valid. FRom now on, nico@fluxnic.net should be used instead.
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This chip reports CFI 1.3, but the CFI PRI is like CFI 1.1. Add a quirk
to pass probe on this chip.
This patch depends on "MTD: CFI 1.0 and CFI 1.1"
Signed-off-by: Daniel Ribeiro <drwyrm@gmail.com>
Acked-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Prevent NUMONYX M29W128G memories from using write buffer,
because it doesn't work properly.
Signed-off-by: Darius Augulis <augulis.darius@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Present backing device capabilities for MTD character device files to allow
NOMMU mmap to do direct mapping where possible.
Signed-off-by: David Howells <dhowells@redhat.com>
Tested-by: Bernd Schmidt <bernd.schmidt@analog.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
If the inval_cache_and_wait_for_operation() is re-entered by write operation when erase
operation is in progress, the chip->erase_suspended will be cleared, this cause the erase
timeo is not reset and will result time out error for erase.
Signed-off-by: Graff Yang <graff.yang@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Which means if inftl or similar are loaded with it (which is a dumb thing
to do admittedly) it may oops.
Closes#8108
[dwmw2: change error to -EROFS to match write-protected flash]
Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The NOR Flash memory K8P2815UQB from Samsung uses the major version
number '0'. Add a quirk to cope with it.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
MTD internal API presently uses 32-bit values to represent
device size. This patch updates them to 64-bits but leaves
the external API unchanged. Extending the external API
is a separate issue for several reasons. First, no one
needs it at the moment. Secondly, whether the implementation
is done with IOCTLs, sysfs or both is still debated. Thirdly
external API changes require the internal API to be accepted
first.
Note that although the MTD API will be able to support 64-bit
device sizes, existing drivers do not and are not required
to do so, although NAND base has been updated.
In general, changing from 32-bit to 64-bit values cause little
or no changes to the majority of the code with the following
exceptions:
- printk message formats
- division and modulus of 64-bit values
- NAND base support
- 32-bit local variables used by mtdpart and mtdconcat
- naughtily assuming one structure maps to another
in MEMERASE ioctl
Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
For "unlock" cycles to 16bit devices in 8bit compatibility mode we need
to use the byte addresses 0xaaa and 0x555. These effectively match
the word address 0x555 and 0x2aa, except the latter has its low bit set.
Most chips don't care about the value of the 'A-1' pin in x8 mode,
but some -- like the ST M29W320D -- do. So we need to be careful to
set it where appropriate.
cfi_send_gen_cmd is only ever passed addresses where the low byte
is 0x00, 0x55 or 0xaa. Of those, only addresses ending 0xaa are
affected by this patch, by masking in the extra low bit when the device
is known to be in compatibility mode.
[dwmw2: Do it only when (cmd_ofs & 0xff) == 0xaa]
v4: Fix stupid typo in cfi_build_cmd_addr that failed to compile
I'm writing this patch way to late at night.
v3: Bring all of the work back into cfi_build_cmd_addr
including calling of map_bankwidth(map) and cfi_interleave(cfi)
So every caller doesn't need to.
v2: Only modified the address if we our device_type is larger than our
bus width.
Cc: stable@kernel.org
Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The CFI information read from AT49BV6416 lists the erase regions in the
wrong order, causing problems when trying to erase or update the first
or last 64KiB block.
Work around this by inverting the "top boot" flag, which will
effectively reverse the order of the erase regions.
This chip is obsolete, but it's used in some existing designs.
Signed-off-by: Håvard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch adds TopBottom detection for most Macronix chips with CFI V1.0.
The main purpose of this patch is to add detection of the MX29LV400C B
used on the LaCie Ethernet Disk mini V2 NAS.
It detects the following parts correctly:-
MX28F640C3B T
MX29LV002C B
MX29LV002NC B
MX29LV004C T
MX29LV400C T/B
MX29LV800C T/B
MX29LV160C T/B
MX29SL800C T/B
MX29SL802C T/B
It detects the following uniform part as bottom but it should work
correctly:-
MX29LV040C
For T parts it causes the erase block table to be reversed correctly.
For other parts it avoids the bogus "Assuming top" message.
It does not detect the following correctly:-
MX28F640C3B B
MX29LV002C T
MX29LV002NC T
MX29LV004C B
MX29SL400C T/B
MX29SL402C T/B
If desired I could supply a more complicated patch to handle these as
well.
Only the MX29LV400C B has been physically tested; others were checked
against their data sheets.
Signed-off-by: Christopher Moore <moore@free.fr>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The patch fixes CFI issue with multipartitional devices leading to the
set of errors or even deadlock. The problem is CFI FL_SYNCING state race
with flash operations (e.g. erase suspend). It is reproduced by running
intensive writes on one JFFS2 partition and simultaneously performing
mount/unmount cycle on another partition of the same chip.
Signed-off-by: Alexander Belyakov <abelyako@googlemail.com>
Acked-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
They need to be exported, so let's give them less generic-sounding names
while we're at it.
Original export patch, along with the suggestion about the nomenclature,
from Stephen Rothwell.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Timeouts are currently given by the typical operation time times 8.
It works in the general well-behaved case but not when an erase block is
failing. For erase operations, it seems that a failing erase block will
keep the device state machine in erasing state until the vendor
specified maximum timeout period has passed. By this time the driver
would have long since timed out, left erasing state and attempted
further operations which all fail. This patch implements timeouts using
values from the CFI Query structure when available.
The patch also sets a longer timeout for locking operations. The current
value used for locking/unlocking given by 1000000/HZ microseconds is too
short for devices like J3 and J5 Strataflash which have a typical clear
lock-bits time of 0.5 seconds.
Signed-off-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
There are some CFI chips which require non standard procedures to get
into QRY mode. The possible way to support them would be trying
different modes till QRY will be read. This patch introduce two new
functions qry_mode_on qry_mode_off. qry_mode_on tries different commands
in order switch chip into QRY mode.
So if we have one more "odd" chip - we just could add several lines to
qry_mode_on. Also using these functions remove unnecessary code
duplicaton in porbe procedure.
Currently there are two "odd" cases
1. Some old intel chips which require 0xFF before 0x98
2. ST M29DW chip which requires 0x98 to be sent at 0x555 (according to
CFI should be 0x55)
This patch is partialy based on the patch from Uwe
(see "[PATCH 2/4] [RFC][MTD] cfi_probe: remove Intel chip workaround"
thread )
Signed-off-by: Alexey Korolev <akorolev@infradead.org>
Signed-off-by: Alexander Belyakov <abelyako@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This long overdue trivial change to the MTD_CFI_AMDSTD kconfig menu
description is intended to help clarify that this option also supports
Spansion flash devices.
Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The kernel.h macro DIV_ROUND_UP performs the computation (((n) + (d) - 1) /
(d)) but is perhaps more readable.
Signed-off-by: Julia Lawall <julia@diku.dk>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Now that we can tell when we have one of the newer DataFlash chips,
optionally expose the 128 bytes of OTP memory they provide. Tested
on at45db642 revision B and D chips.
Switch mtdchar over to a generic HAVE_MTD_OTP flag instead of adding
another #ifdef for each type of chip whose driver has OTP support.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Cc: Bryan Wu <cooloney@kernel.org>
Cc: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The device id for Am29DL800BB in jedec_probe.c is wrong.
Reference: http://www.spansion.com/datasheets/21519c4.pdf
I discovered this while working with u-boot.
The u-boot folks mentioned Linux as an upstream reference, thought I'd
post a heads-up here too.
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The unlock_addr rework in kernel 2.6.25 breaks 16-bit SST chips. SST
39LF160 and SST 39VF1601 are both 16-bit only chip (do not have BYTE#
pin) and new uaddr value is not correct for them. Add
MTD_UADDR_0xAAAA_0x5555 for those chips. Tested with SST 39VF1601
chip.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Existing CFI driver has problems with excessive writes during erase.
If CFI driver does many writes during one erase cycle we may face the
messages with -ETIMEO error on erase operation. It may cause the
following data corruption and kernel panics.
The reason of the issue is related to specifics of suspend operation:
if we write to flash during erase, suspend operation will cost some time
to erase procedure (for P30 it could be significant). In current version of
cfi driver the problem of many suspends is partially workarounded by adding
some time reserv to any operation (8xerase_time) but if we have many writes
during one erase the problem appears.
This patch detects the suspend and resets timer if suspend occured. It
has been well verified on different chips. No problems were found.
Could you please include the patch as it is simple and fixes bad issue.
Signed-off-by: Alexey Korolev <akorolev@infradead.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Use pr_debug(...) instead of printk(KERN_DEBUG ...) so that the message
is only printed when debugging is enabled.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Tested-by: John stoffel <john@stoffel.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
