From Linus Walleij:
Ux500 core patches for the v3.14 series:
- Enable PRINTK_TIME
- Enable suspend with WFI
* tag 'ux500-core-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: Enable system suspend with WFI support
ARM: ux500: turn on PRINTK_TIME in u8500_defconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
From Christian Daudt, various defconfig udpates to bcm mobile.
* tag 'bcm-for-3.14-soc' of git://github.com/broadcom/bcm11351:
rename ARCH_BCM to ARCH_BCM_MOBILE (clocksource)
ARM: bcm_defconfig: Unset CONFIG_CRYPTO_ANSI_CPRNG
ARM: bcm_defconfig: Do not expect appended DTB
ARM: bcm_defconfig: CONFIG_OABI_COMPAT default off
Signed-off-by: Olof Johansson <olof@lixom.net>
When building for CONFIG_SUSPEND, add the platform suspend callbacks
to enable system suspend for ux500.
At this initial step, only WFI state is supported, which is reached
for both PM_SUSPEND_MEM and PM_SUSPEND_STANDBY.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
I recently noticed slow booting of a board, and without printk timestamps it's
harder to tell just where the delays are coming from. Enable it.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add the initial i.MX50 SoC support
- Support device tree boot for i.MX35
- Move imx5 clock driver to use macros for clock ID
- Some random updates and non-critical fixes on clock drivers
- A few defconfig updates and minor cleanups
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJSwiPBAAoJEFBXWFqHsHzO3/AIALlP6m/7taIQW5wO4o4aqdwk
GsN7IdsfWH/biG9VyxgpIoJKUqaOJckGA0eyLSeEG7p78xlf0n7cVPUNwzz9z1Vc
zxLSaVNznVOa4fTIsbMK9U+gUP931hjXskxD3tH98MUFqlM0JLQYoofr/lXG7Esf
N2p8B9aUND3WSxDa+d+CsW0B3FBj1piOQDMDgrdc3p7kjcAJs31KaKfUa06o7gzM
a81OaD9Vk0ONf44wh1LGlg0hDRsatQOa4tUTimeV14CnESKqsKxT4qAJ6pZLdfOt
KyRqSk4f4mkpimv4bGdhXTIsIko1CD9wg7G9fsSaolh3OEP0yyNf1savR1fmwCI=
=Hhbl
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-3.14' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo:
i.MX SoC changes for 3.14:
- Add the initial i.MX50 SoC support
- Support device tree boot for i.MX35
- Move imx5 clock driver to use macros for clock ID
- Some random updates and non-critical fixes on clock drivers
- A few defconfig updates and minor cleanups
* tag 'imx-soc-3.14' of git://git.linaro.org/people/shawnguo/linux-2.6: (37 commits)
ARM: imx: improve the comment of CCM lpm SW workaround
ARM: imx: improve status check of clock gate
ARM: imx: add necessary interface for pfd
ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100
ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support
ARM: imx: Add cpu frequency scaling support
ARM i.MX35: Add devicetree support.
ARM: imx: update imx_v6_v7_defconfig
ARM: imx6sl: Add missing spba clock to clock tree
ARM: imx6sl: Add missing pll4_audio_div to the clock tree
ARM: imx6: Derive spdif clock from pll3_pfd3_454m
ARM: imx: use __initconst for const init definition
ARM i.MX5: fix obvious typo in ldb_di0_gate clk definition
ARM i.MX5: set CAN peripheral clock to 24 MHz parent
ARM: imx: pllv1: Fix PLL calculation for i.MX27
ARM i.MX5: fix "shift" value for lp_apm_sel on i.MX50 and i.MX53
ARM: imx: imx53: Add SATA PHY clock
ARM: imx_v6_v7_defconfig: Enable STMPE touchscreen
ARM: imx: rename IMX6SL_CLK_CLK_END to IMX6SL_CLK_END
ARM: imx: select PINCTRL at sub-architecure level
...
Signed-off-by: Olof Johansson <olof@lixom.net>
* Global
- Don't set plat_sci_port scbrr_algo_id field
- Declare SCIF register base and IRQ as resources
- Don't define SCIF platform data in an array
- Use macros to declare SCIF devices
* r7s72100 SoC (RZ/A1H)
- Add i2c clocks
* r8a7778 (R-Car M1)
- Add sound SCU clock support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJSuYCjAAoJENfPZGlqN0++5uEQAICvtZMbC5Q04G22ePlzTTk1
/AHZTLRifgo8nNvGi0vky5tt3fuLBmNTixNFF1qCT7gTy9J+CzNz0OmSbg7sWY3h
km8IrTVWfY7lCMQ7UxbHW/3KjEOLG371B2edVunTb9JYHrrCte0q+4I4A7xmV1HA
mwoF+tziXXK5xCo6P0iAL7bAV04AE/r1fUD/zuH8CSm8xS8FJ2z7ZD1EIxcMNMbb
Xl7J2NkP1ntlazrElupuYxY+zDImI1mc0FIBtkV+ft4C2REKCs1q9fGC0xq+hN10
EkO0WYqezphcwSHXiHqApcjBwKHZoI6W+VmISl197FsY5zbtqLwpD+8mHeqd+WuG
qqK67m6BrcXTmM5pdsxy7QF81FdETX1e14zVkRaNBxw08kkFYbndFJz4ffNPIWUq
9N3q7Do8vZCnksM9XxQ95mpLIvfM8itlf4FDGr0O0ACEu+uQfUczXykSJVx5sGqu
0SV8ESCb3LRpRCGbwEIUgMDHM36aESqaIOWbmK6QHoTYWlg9Ka88dB2s2We71yuS
+PRZ7CpIsWMe7zb30TuiBPokYloHneiIVRf4RJWeGsyCgkN0DfkxorHK9UB7Adzy
jmkaqp5ebQ8CQplIVgldCcJngi2PmbUWeJcKlSNfg8aVpl8BRW8/Xv9RFuL8x/Cc
3jmFoXD12pJavs8T9dgi
=7k3L
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Third Round of Renesas ARM Based SoC Updates for v3.14
* Global
- Don't set plat_sci_port scbrr_algo_id field
- Declare SCIF register base and IRQ as resources
- Don't define SCIF platform data in an array
- Use macros to declare SCIF devices
* r7s72100 SoC (RZ/A1H)
- Add i2c clocks
* r8a7778 (R-Car M1)
- Add sound SCU clock support
* tag 'renesas-soc3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits)
arm: shmobile: r7s72100: add i2c clocks
ARM: shmobile: r8a7791: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7779: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7790: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7740: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a73a4: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7778: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r7s72100: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: sh73a0: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7790: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7791: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7778: Declare SCIF register base and IRQ as resources
ARM: shmobile: sh7372: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7779: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7740: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a73a4: Declare SCIF register base and IRQ as resources
ARM: shmobile: r7s72100: Declare SCIF register base and IRQ as resources
ARM: shmobile: sh73a0: Declare SCIF register base and IRQ as resources
ARM: shmobile: sh7372: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7790: Don't define SCIF platform data in an array
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This doesn't need to be a def_bool y. Instead we can have every
DT supported platform select ARCH_MSM_DT and we achieve the same
thing with less chance of conflicts.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add support for the Snapdragon 800 MSM8974 SoC, used on the Dragonboard
and others. Board support added in separate patch.
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
[olof: split off SoC support in separate patch]
Signed-off-by: Olof Johansson <olof@lixom.net>
Fix the following warning when !CONFIG_MMC:
arch/arm/mach-msm/board-trout.c: In function 'trout_init':
arch/arm/mach-msm/board-trout.c:67:6: warning: unused variable 'rc' [-Wunused-variable]
int rc;
^
Also, while we're here, rework explicit printk(KERN_CRIT..) to use
pr_crit.
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Improve the comment of SW workaround for CCM lpm issue using
hardware errata description to avoid confusion.
ERR007265: CCM: When improper low-power sequence is used, the SoC
enters low power mode before the ARM core executes WFI.
Software workaround:
1) Software should trigger IRQ #32 (IOMUX) to be always pending
by setting IOMUX_GPR1_GINT.
2) Software should then unmask IRQ #32 in GPC before setting CCM
Low-Power mode.
3) Software should mask IRQ #32 right after CCM Low-Power mode is
set (set bits 0-1 of CCM_CLPCR).
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
For ccm clock gate, both 2b'11 and 2b'01 should be treated
as clock enabled, see below description in CCM, whenver CPU
trys to check clock gate's status, system will be in run mode.
2b'00: clock is off during all modes;
2b'01: clock is on in run mode, but off in wait and stop mode;
2b'10: Not applicable;
2b'11: clock is on during all modes, except stop mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Common clk framework will disable unused clks in late init only if
they are enabled by default and no one is using it, so we need to
add is_enabled callback for clk framework to get clks' status.
PFD clocks are enabled by hardware reset, so we need to add
interface for common clk framework to disable those unused ones for
saving power.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
PFUZE100 regulator is commonly found on mx6 based designs.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Let MX35 and MX50 device tree support be built by default.
Generated by doing:
- Selected CONFIG_MACH_IMX35_DT and CONFIG_SOC_IMX50 via 'make menuconfig'
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v6_v7_defconfig
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Update the IMX v6/v7 defconfig for the SolidRun HummingBoard:
- Add AT803X ethernet phy
- Add consumer IR devices
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We are missing spba clock in imx6sl's clock tree, thus add it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
SPDIF can derive a TX clock for playback from one of its clock sources --
spdif root clock to match its supporting sample rates. So this patch set
the spdif root clock's parent to pll3_pfd3_454m since the pll3_pfd3_454m
can approximately meet its sample rate requirement.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
0-DAY kernel build testing backend reports the following.
scripts/checkpatch.pl 0001-ARM-imx-add-support-code-for-IMX50-based-machines.patch
# many are suggestions rather than must-fix
ERROR: Use of const init definition must use __initconst
#80: arch/arm/mach-imx/mach-imx50.c:26:
+static const char *imx50_dt_board_compat[] __initdata = {
While at it, fix the error globally for IMX platform.
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
ldb_di0_gate is registerd with the clk index of IMX5_CLK_LDB_DI1_GATE,
thus the DI0 interface will be turned off inadvertently during boot.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
lp_apm clock, which has a rate of 24 MHz.
In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
has a rate of 66.666 MHz which produces quite large bit rate errors.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
is a just sign bit. This patch makes different calculation for i.MX27.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
According to the i.MX50 Rev. 1 and i.MX53 Rev. 2.1 datasheet the lp_apm_sel is
bit 10 in the CCM_CCSR register not bit 9. On the i.MX51 it's bit 9.
This patch fixes this issue.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add SATA PHY clock which are derived from the USB PHY1 clock. Note that this
patch derives the SATA PHY clock from USB PHY1 clock gate so that the SATA
driver can ungate both the SATA PHY clock and USB PHY1 clock for the SATA to
work correctly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Linux-IDE <linux-ide@vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Instead of selecting PINCTRL on individual SoC, let's select it at IMX
sub-architecure level.
While at it, it also adds the missing PINCTRL_IMX50 selection for
SOC_IMX50.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
ARM clock is sourcing from pll1_sw, and pll1_sw can be either from
pll1_sys or step, so we should enable arm clock during clock
initialization instead of pll1_sys, otherwise, arm clock's usecount
would be incorrect and PLL1 will never be disabled even it is not
used.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use clock defines in order to make devicetrees more
human readable.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This branch contains various miscellaneous changes to code in the
mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict
with anything else.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSr3IGAAoJEMzrak5tbycxVVUP/09VfeFYOidIm6mgbWSMlL4l
DEPzrGBOvyO60og4LIbDIgwDzkcEsxIF9erlrVTz1Fvh2p0P0sQycIKjvyhvNXeh
Ft9TQ1kDHjoJcfHI9f8tapkmwhOG+6vy2gDrTPmyxjnLpiE5ccM18CCr5CMK+y2v
Ojzmf2paPBFyI84gcdWuwF4Ze2YmwdHmG7TksG/PZrpicizSxe+d9wNVDBMkJnP6
QFicMU6DEFZVwwDkFx4qPYrFDJPk8dqcAmNl+F+9jGEqTmxA+7M8eOF/SQa62lwa
OJrVugD8YigT5NjRW/9btOVY/jUHbg0Ekj5DXd7Q9rO5KNUrFDRSia5XiWmms/S8
QNJezmjNgA83OQDefuAkpsKydf1XGoyIQ9EjDUb4i807PRwTO4En+1pD0EpEWSet
0c1mfDvU5uC6L9A5VvR0pzyGz2U2EhNhkUz03WAqtWYdrR68vIZHNZVIvHOLuwWF
fDkS26KxziOmKM1ePdL7wemuNOod8ACeyzXMa2dhR68l6LH1X1pnMaoxvk2AjETk
SMat9tsxY827+TtQlAQ+4bdR3qXqYsQLD7VWOPO0V3fs5T08jVZrpJ9pHDRYW88K
dGHmIW4sHXKXP4Qw9rDGWSkWZeOVJYr72U6uH9vbg8hK6Wi2eAMxZ27ngFiqahSK
PIhnAfsdM2/FX+C+vu58
=Oztt
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc
From Stephen Warren:
ARM: tegra: SoC-specific core code changes
This branch contains various miscellaneous changes to code in the
mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict
with anything else.
* tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC
ARM: tegra: use section-sized static mappings for LPAE too
ARM: tegra: don't hard-code DEBUG_LL baud rate
ARM: tegra: fix DEBUG_LL combined with LPAE
ARM: tegra: switch FUSE clock on before usage
Signed-off-by: Olof Johansson <olof@lixom.net>
This branch includes all the changes to Tegra's powergate driver for 3.14.
These are separate out, since the Tegra DRM changes for 3.14 rely on the
new APIs introduced here.
A few cleanups and fixes are included, plus additions of Tegra124 SoC
support, and a new API for manipulating Tegra's IO rail deep power down
states.
This branch is based on tag tegra-for-3.14-dmas-resets-rework, in order
to avoid conflicts with the addition of common reset controller support
to the powergate driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSr3G5AAoJEMzrak5tbycxHaEP/2YP1KIUTINzF9JlTaFWLd38
dlqCOdDjcIow6QvaI0H2xdD7OhWqbiK2gAKz10PH0TYVr5AJZKyC7uxAw1gvV5bI
2hgP9ZBVQY8qfveZuyQhL9jCwAg52TfG2LBO4Iw3wng9tO00uo8knjoHURmiewuY
fLY8CQxYydwK8MmqabPI/L0gQhSlswyDByaeB0ixHJncSVT8KHmbSX8kx7FnYsI6
/r/D7IQtMyx52XJRbInN83UIdONKP9vkPAXmptKBU2SGwdXOzqPqfxFuNRKN85Gq
a4wlJUQAfBAndiemaZIH5O7gmmUht1lB0L9JWDFw9nBr6EHDVOpgRgi/OgVFaFE+
Qer3LdrpEvyXsRe3AjeQgta8716KaRMW3IbaqkdS0F+HwyFGL9/nGRttu9JLHSCR
oo7FVscaE7tC2d/LGNqI0y4pprgbrjROT70hWoNDF8oS5qDsI3rxEjB0FXyzE2by
Bd702Sc9heh60Hnov/vZy9WFcWETEKVEF5hgIL3lrjA6pMKdH7fEylOD+bxVAmE2
t5wePXc7OSdciaLN/D1GhtCD+R58u+idHadKnU9uRYB1wmeIAeJMi9D/ZnpKftX4
M5Ts7t8k1jxZlRXXgiara3SwJ6tIOlc5vEvhQWEeInzL0yishFDy2mmq1lMaV0mJ
cFgQUdhufycI0Yprfwjt
=jJOV
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.14-powergate' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc
From Stephen Warren:
ARM: tegra: powergate driver changes
This branch includes all the changes to Tegra's powergate driver for 3.14.
These are separate out, since the Tegra DRM changes for 3.14 rely on the
new APIs introduced here.
A few cleanups and fixes are included, plus additions of Tegra124 SoC
support, and a new API for manipulating Tegra's IO rail deep power down
states.
This branch is based on tag tegra-for-3.14-dmas-resets-rework, in order
to avoid conflicts with the addition of common reset controller support
to the powergate driver.
* tag 'tegra-for-3.14-powergate' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Add IO rail support
ARM: tegra: Special-case the 3D clamps on Tegra124
ARM: tegra: Add Tegra124 powergate support
ARM: tegra: Export tegra_powergate_remove_clamping()
ARM: tegra: Export tegra_powergate_power_off()
ARM: tegra: Rename cpu0 powergate to crail
ARM: tegra: Fix some whitespace oddities
Signed-off-by: Olof Johansson <olof@lixom.net>
Bringing in the tegra dma/reset rework as a base for new SoC branches.
* tegra/dma-reset-rework: (81 commits)
spi: tegra: checking for ERR_PTR instead of NULL
ASoC: tegra: update module reset list for Tegra124
clk: tegra: remove bogus PCIE_XCLK
clk: tegra: remove legacy reset APIs
ARM: tegra: remove legacy DMA entries from DT
ARM: tegra: remove legacy clock entries from DT
USB: EHCI: tegra: use reset framework
Input: tegra-kbc - use reset framework
serial: tegra: convert to standard DMA DT bindings
serial: tegra: use reset framework
spi: tegra: convert to standard DMA DT bindings
spi: tegra: use reset framework
staging: nvec: use reset framework
i2c: tegra: use reset framework
ASoC: tegra: convert to standard DMA DT bindings
ASoC: tegra: allocate AHUB FIFO during probe() not startup()
ASoC: tegra: call pm_runtime APIs around register accesses
ASoC: tegra: use reset framework
dma: tegra: register as an OF DMA controller
dma: tegra: use reset framework
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Tested with RIIC2 on a genmai board. Others untested but hopefully
trivial enough to be added.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
