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3 Commits

Author SHA1 Message Date
Ben Skeggs
52eba8dd5e drm/nva3/clk: better pll calculation when no fractional fb div available 
The core/mem/shader clocks don't support the fractional feedback divider,
causing our calculated clocks to be off by quite a lot in some cases.  To
solve this we will switch to a search-based algorithm when fN is NULL.

For my NVA8 at PL3, this actually generates identical cooefficients to
the binary driver.  Hopefully that's a good sign, and that does not
break VPLL calculation for someone..

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2011-05-16 10:50:59 +10:00
Ben Skeggs
2a56a0b913 drm/nva3: fix overflow in fixed point math used for pll calculation 
And a slight tweak which gets us closer to VBIOS-calculated numbers.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2010-11-18 14:38:34 +10:00
Ben Skeggs
e9ebb68b86 drm/nv50: support fractional feedback divider on newer chips 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
 2010-05-19 16:21:59 +10:00