Commit Graph

2 Commits

Author SHA1 Message Date
Rob Herring
479a41748f media: dt-bindings: coda: Add missing 'additionalProperties'
'additionalProperties' is now required by the meta-schema. Add it for
coda. As a result, 'interrupts', 'interrupt-names' and 'power-domains'
need to be reworked to be defined at the top level.

Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: linux-media@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20201117200752.4004368-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
2020-12-18 15:15:20 -06:00
Philipp Zabel
d7dc892dd4 media: dt-bindings: convert CODA VPU bindings to yaml
Convert to YAML and add generic IP core compatibles "cnm,codadx6",
"cnm,codahx4", "cnm,coda7541", and "cnm,coda960" in addition to the SoC
specific compatibles. The new generic compatibles are already used in
the SoC device trees and replace the free form comments. For example:

- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
  (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27

turns into:

properties:
  compatible:
    oneOf:
      - items:
          - const: fsl,imx27-vpu
          - const: cnm,codadx6

This allows to properly specify the secondary JPEG unit interrupt that
is only present on cnm,coda960.

Also add the missing "fsl,imx6dl-vpu", "cnm,coda960" compatible.
The AXI bus connection to the internal SRAM is different between i.MX6Q
and i.MX6DL, which requires the driver to load a different firmware
depending on the SoC.

Further, specify the power-domain property for i.MX6 and change the
clock order from "ahb", "per" to "per", "ahb". This order is currently
used in all SoC device trees.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-11-16 10:31:13 +01:00