Commit Graph

9708 Commits

Author SHA1 Message Date
Shengzhou Liu
478a4829d8 powerpc/85xx: Update corenet64_smp_defconfig
Enable USB, MMC, SATA, LBC, MTD, NAND, SPI, PCIe, EDAC, VFAT, NFS, etc.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11 07:45:50 -05:00
Shengzhou Liu
9d23298734 powerpc/85xx: Update corenet32_smp_defconfig
- Enable NAND support
 - Enable CONFIG_PCI_MSI and CONFIG_MMC_SDHCI_OF

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11 07:45:43 -05:00
Xu Jiucheng
3ef4106573 powerpc/85xx: Rename P1021RDB-PC device trees to be consistent
The board is really P1021RDB-PC, so rename from p1021rdb.* to p1021rdb-pc.*

Signed-off-by: Xu Jiucheng <Jiucheng.Xu@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11 07:45:42 -05:00
Shaohui Xie
c5f02bb422 powerpc/watchdog: move booke watchdog param related code to setup-common.c
Currently, BOOKE watchdog code for checking "wdt" and "wdt_period" is
in setup_32.c, it cannot be used in 64-bit, so move it to a common place
setup-common.c, which will be shared by 32-bit and 64-bit.

Also, replace the simple_strtoul with kstrtol.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-11 07:44:03 -05:00
Zhicheng Fan
b5dc298687 powerpc/85xx: Add ucc uart support for p1025rdb
Add device tree nodes to enable ucc uart support on P1025RDB.

Signed-off-by: Zhicheng Fan <B32736@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:56:45 -05:00
Shawn Guo
6d4ae2ddfe powerpc: select PPC_CLOCK unconditionally for FSL_SOC
Freescale PowerPC SoCs share a number of IP blocks with Freescale
ARM/IMX SoCs, FlexCAN, SSI, FEC, eSDHC, USB, etc.  There are some
effort consolidating those drivers to make them work for both
architectures.

One outstanding difference between two architectures is ARM/IMX will
turn off module clocks during platform initialization for power saving
and expects drivers manage clocks using clk API, while PowerPC
mostly does not do that, and thus does not always build in clk API.

Listing all those driver Kconfig options in "select PPC_CLOCK if" seems
not scalable for long term maintenance, and could easily introduce
Kconfig recursive dependency.  This patch chooses to select PPC_CLOCK
unconditionally for FSL_SOC to always build clk API for PowerPC in.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:08:58 -05:00
Kokoris, Ioannis
e65650e6c3 powerpc/qe: set IReady in QE Microcode Upload
QE Microcode Initialization using qe_upload_microcode() does not work on
P1021 if the IRAM-Ready register is not set after the microcode upload. Add
a definition for the "I-RAM Ready" register and sets it upon microcode
upload completion.

Signed-off-by: Ioannis Kokkoris <ioannis.kokoris@siemens-enterprise.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:08:58 -05:00
Jia Hongtao
1f0e90ad7a powerpc/85xx: MPC8572DS - Update the MSI interrupts into 4-cell format
With 2-cell format interrupts of MSI PCIe ethernet card can not work.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:08:35 -05:00
Jia Hongtao
a2ec009b75 powerpc/85xx: MPC8572DS - Fix eTSEC is not available on core1 of AMP boot
The issue log on core1 is:
root@mpc8572ds:~# ifconfig eth0 10.192.208.244
net eth0: could not attach to PHY
SIOCSIFFLAGS: No such device

To attach PHY node mdio@24520 should not be disabled in dts of core1.
Because all PHYs are controlled through this node as follows:

mdio@24520 {
	phy0: ethernet-phy@0 {
		interrupts = <10 1 0 0>;
		reg = <0x0>;
	};
	phy1: ethernet-phy@1 {
		interrupts = <10 1 0 0>;
		reg = <0x1>;
	};
	phy2: ethernet-phy@2 {
		interrupts = <10 1 0 0>;
		reg = <0x2>;
	};
	phy3: ethernet-phy@3 {
		interrupts = <10 1 0 0>;
		reg = <0x3>;
	};

	tbi0: tbi-phy@11 {
		reg = <0x11>;
		device_type = "tbi-phy";
	};
};

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:49 -05:00
Varun Sethi
5a271fe784 powerpc/mpic: Use the MPIC_LARGE_VECTORS flag for FSL MPIC.
We should use the MPIC_LARG_VECTORS flag while intializing the MPIC.
This prevents us from eating in to hardware vector number space (MSIs)
while setting up internal sources.

Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:22 -05:00
Liu Yu
2dc3d4cc68 powerpc/e500: make load_up_spe a normal fuction
So that we can call it when improving SPE switch like book3e did for fp
switch.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:22 -05:00
Prabhakar Kushwaha
d729b900e5 powerpc/85xx: Add BSC9131 RDB Support
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The
BSC9131 is integrated SoC that targets Femto base station market. It
combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.

The BSC9131 SoC includes the following function and features:
    . Power Architecture subsystem including a e500 processor with 256-Kbyte
    shared L2 cache
    . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
    . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
      Processing (MAPLE-B2F)
    . A multi-standard baseband algorithm accelerator for Channel
      Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE
      UP/DL Channel processing, and CRC algorithms
    . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
      Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix
      Inversion operations
    . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit
      with ECC, up to 400-MHz clock/800 MHz data rate
    . Dedicated security engine featuring trusted boot
    . DMA controller
    . OCNDMA with four bidirectional channels
    . Interfaces
    . Two triple-speed Gigabit Ethernet controllers featuring network
      acceleration including IEEE 1588. v2 hardware support and
      virtualization (eTSEC)
    . eTSEC 1 supports RGMII/RMII
    . eTSEC 2 supports RGMII
    . High-speed USB 2.0 host and device controller with ULPI interface
    . Enhanced secure digital (SD/MMC) host controller (eSDHC)
    . Antenna interface controller (AIC), supporting three industry standard
      JESD207/three custom ADI RF interfaces (two dual port and one single
      port) and three MAXIM's MaxPHY serial interfaces
    . ADI lanes support both full duplex FDD support and half duplex TDD
      support
    . Universal Subscriber Identity Module (USIM) interface that facilitates
      communication to SIM cards or Eurochip pre-paid phone cards
    . TDM with one TDM port
    . Two DUART, four eSPI, and two I2C controllers
    . Integrated Flash memory controller (IFC)
    . TDM with 256 channels
    . GPIO
    . Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

 BSC9131RDB Overview
 ----------------------
    BSC9131 SoC
    1Gbyte DDR3 (on board DDR)
    128Mbyte 2K page size NAND Flash
    256 Kbit M24256 I2C EEPROM
    128 Mbit SPI Flash memory
    USB-ULPI
    eTSEC1: Connected to RGMII PHY
    eTSEC2: Connected to RGMII PHY
    DUART interface: supports one UARTs up to 115200 bps for console display

 Linux runs on e500v2 core and access some DSP peripherals like AIC

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:22 -05:00
Timur Tabi
ab2aba4743 Revert "powerpc/p3060qds: Add support for P3060QDS board"
This reverts commit 96cc017c5b.

The P3060 was cancelled before it went into production, so there's no point
in supporting it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:22 -05:00
Timur Tabi
6bd825f029 powerpc/85xx: use the BRx registers to enable indirect mode on the P1022DS
In order to enable the DIU video controller on the P1022DS, the FPGA needs
to be switched to "indirect mode", where the localbus is disabled and
the FPGA is accessed via writes to localbus chip select signals CS0 and CS1.

To obtain the address of CS0 and CS1, the platform driver uses an "indirect
pixis mode" device tree node.  This node assumes that the localbus 'ranges'
property is sorted in chip-select order.  That is, reg value 0 maps to
CS0, reg value 1 maps to CS1, etc.  This is how the 'ranges' property is
supposed to be arranged.

Unfortunately, the 'ranges' property is often mis-arranged, and not just on
the P1022DS.  Linux normally does not care, since it does not program the
localbus.  But the indirect-mode code on the P1022DS does care.

The "proper" fix is to have U-Boot fix the 'ranges' property, but this would
be too cumbersome.  The names and 'reg' properties of all the localbus
devices would also need to be updated, and determining which localbus device
maps to which chip select is board-specific.

Instead, we determine the CS0/CS1 base addresses the same way that U-boot
does -- by reading the BRx registers directly and mapping them to physical
addresses.  This code is simpler and more reliable, and it does not require
a U-boot or device tree change.

Since the indirect pixis device tree node is no longer needed, the node is
deleted from the DTS.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:21 -05:00
Shaohui Xie
aeccf8983e powerpc/p2041rdb: add NAND node in device tree
NAND on p2041 uses CS1 as chip select.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:21 -05:00
Paul Gortmaker
b048b4e17c powerpc: remove Wind River SBC8560 support
This reference board dates back to 2004, and is largely a legacy
EOL product.  The MPC8560 is a pre e500v2 CPU.  The SBC8548 is
a more modern, better e500v2 target for people to use as a
reference board with today's kernels, should they require one.

Removing support for it will also allow us to remove some
sbc8560 specific quirk handling in 8250 UART code, and some
MTD mapping support.

Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:21 -05:00
Tang Yuantian
572546b334 powerpc/85xx: Add P1024rdb dts support
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:21 -05:00
Tang Yuantian
063e94bbe5 powerpc/85xx: Add P1024rdb board support
The p1024rdb has the similar feature as the p1020rdb. Therefore, p1024rdb use
the same platform file as the p1/p2 rdb board.
Overview of P2020RDB platform
	- DDR3 1G
	- NOR flash 16M
	- 3 Ethernet interfaces
	- NAND Flash 32M
	- SPI EEPROM 16M
	- SD/MMC
	- 2 USB ports
	- 4 TDM ports

Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:21 -05:00
Gustavo Zacarias
babb5e8d47 powerpc/p1010rdb: add EEPROMs to device tree
Add EEPROM to the P1010RDB device tree.
The 24c01 acts as a memory SPD so it shouldn't be overwritten without
care.
The 24c256 is a general purpose memory.

Signed-off-by: Gustavo Zacarias <gustavo@zacarias.com.ar>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:20 -05:00
Sebastian Andrzej Siewior
4b2e185d23 Revert "powerpc/85xx: p2020rdb - move the NAND address."
This reverts commit 0c00f65653.
The initial commit was my fault. There are two boards out there:
P2020RDB and P2020RDB-PC. I wasn't aware of that and assumed that I have
a RDB board in front of me while I the RDB-PC. This patch makes it work
for the RDB-PC variant and breaks it for the RDB. Now there is a device
tree file available for the RDB-PC which was not there earlier. So with
this revert, everything gets back to normal :)

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:20 -05:00
Holger Brunck
5d1d67e361 powerpc/82xx: add SPI support for mgcoge
Add spi support for mgcoge into the platform code and the dts
file. Additionaly SPIDEV is switched on in the defconfig and the
updates for the newer kernel version are committed. The SPI
interface is used to drive the Maxim DS3106 clock chip.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:20 -05:00
Holger Brunck
7ee0bf5336 powerpc/83xx: update defconfig for kmeter1
Switch on UBIFS, HOTPLUG and TIPC and update the config to
the latest kernel version.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:20 -05:00
Christian Herzig
4bfc1dd9d6 powerpc/83xx: fix RGMII AC values workaround for km83xx
Fix RGMII workaround code in km83xx.c for MPC8360E and MPC8358E that it
correctly identifes all affected SoC chip models and applies the
workarounds appropriate for 2.0 and 2.1 revisions as per Freescale
MPC8360ECE Errata document Rev.5(9/2011) item QE_ENET10.

Signed-off-by: Christian Herzig <christian.herzig@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:20 -05:00
Holger Brunck
f7854e72a3 powerpc/83xx: use for_each_node_by_name for km83xx.c
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:20 -05:00
Jerry Huang
4a35243319 powerpc/p1022ds: Add RTC support
Add the RTC support into the p1022ds device tree

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:19 -05:00
Shengzhou Liu
5a9e0d2e7a powerpc/85xx: Enable MTD/NOR/NAND options by default in defconfig
Enable MTD/NOR/NAND options by default in mpc85xx_defconfig and
mpc85xx_smp_defconfig to support NOR, NAND flash.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:19 -05:00
Kim Phillips
a6fceddd7b powerpc/fsl: Distribute interrupts on all CPUs by default
At least for crypto/IPSec, doing so provides users with a better
performance experience out of the box.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:19 -05:00
Matias Garcia
dea0ed4a64 powerpc/fsl/pci: Fix when quirk_fsl_pcie_header is freed up
Change quirk_fsl_pcie_header from __init to __devinit to ensure if we
have a runtime access (like via an FPGA being loaded after boot on the
PCIe link) that we dont access randomly freed memory.

Signed-off-by: Matias Garcia <mgarcia@rossvideo.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10 07:07:19 -05:00
Michael Ellerman
db9112173b powerpc: Turn on BPF_JIT in ppc64_defconfig
Matt added BPF_JIT support in commit 0ca87f05, but currently none of our
defconfigs build it. Turn that sucker on.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:19:02 +10:00
Anton Blanchard
d6b9a81b2a powerpc: IOMMU fault injection
Add the ability to inject IOMMU faults. We enable this per device
via a fail_iommu sysfs property, similar to fault injection on other
subsystems.

An example:

...
0003:01:00.1 Ethernet controller: Emulex Corporation OneConnect 10Gb NIC (be3) (rev 02)

To inject one error to this device:

echo 1 > /sys/bus/pci/devices/0003:01:00.1/fail_iommu
echo 1 > /sys/kernel/debug/fail_iommu/probability
echo 1 > /sys/kernel/debug/fail_iommu/times

As feared, the first failure injected on the be3 results in an
unrecoverable error, taking down both functions of the card
permanently:

be2net 0003:01:00.1: Unrecoverable error in the card

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:59 +10:00
Anton Blanchard
a980349725 powerpc: Call dma_debug_add_bus for PCI and VIO buses
The DMA API debug code has hooks to verify all DMA entries have been
freed at time of hot unplug. We need to call dma_debug_add_bus for
this to work.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:57 +10:00
Anton Blanchard
44b372d8a0 powerpc/vio: Separate vio bus probe and device probe
Similar to PCI, separate the bus probe from device probe. This allows
us to attach bus notifiers for DMA debug and IOMMU fault injection
before devices have been probed.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:54 +10:00
Anton Blanchard
62761d1f68 powerpc/vio: Remove dma not supported warnings
During boot we see a number of these warnings:

vio 30000000: Warning: IOMMU dma not supported: mask 0xffffffffffffffff, table unavailable

The reason for this is that we set IOMMU properties for all VIO
devices even if they are not DMA capable.

Only set DMA ops, table and mask for devices with a DMA window.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:51 +10:00
Michael Neuling
9c41ef086e powerpc/pseries: Fix whitespace in eeh
Signed-off-by: Michael Neuling <mikey@neuling.org>
Acked-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:49 +10:00
Anton Blanchard
6da7094810 powerpc/perf: Use perf_instruction_pointer in callchains
We use SIAR or regs->nip for the instruction pointer depending on
the PMU configuration, but we always use regs->nip in the callchain.

Use perf_instruction_pointer so the backtrace is consistent.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:46 +10:00
Anton Blanchard
5c093efa6f powerpc/perf: Always use pt_regs for userspace samples
At the moment we always use the SIAR if the PMU supports continuous
sampling. Unfortunately the SIAR and the PMU exception are not
synchronised for non marked events so we can end up with callchains
that dont make sense.

The following patch checks the HV and PR bits for samples coming from
userspace and always uses pt_regs for them. Userspace will never have
interrupts off so there is no real advantage to using the SIAR for
non marked events in userspace.

I had experimented with a patch that did a similar thing for kernel
samples but we lost a significant amount of information. I was
unable to profile any of our early exception code for example.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:43 +10:00
Anton Blanchard
75382aa72f powerpc/perf: Move code to select SIAR or pt_regs into perf_read_regs
The logic to choose whether to use the SIAR or get the information
out of pt_regs is going to get more complicated, so do it once in
perf_read_regs.

We overload regs->result which is gross but we are already doing it
with regs->dsisr.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:41 +10:00
Anton Blanchard
68b30bb9f0 powerpc/perf: Create mmcra_sihv/mmcra_sipv helpers
We want to access the MMCRA_SIHV and MMCRA_SIPR bits elsewhere so
create mmcra_sihv and mmcra_sipr which hide the differences between
the old and new layout of the bits.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:38 +10:00
Michael Neuling
962cffbd8a powerpc: Enforce usage of RA 0-R31 where possible
Some macros use RA where when RA=R0 the values is 0, so make this
the enforced mnemonic in the macro.

Idea suggested by Andreas Schwab.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:35 +10:00
Michael Neuling
f4c015795c powerpc: Add defines for RA 0-R31
R0 is special since it'll be 0.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:33 +10:00
Michael Neuling
0b7673c35e powerpc: Enforce usage of R0-R31 where possible
Enforce the use of R0-R31 in macros where possible now we have all the
fixes in.

R0-R31 macros are removed here so that can't be used anymore.  They
should not be defined anywhere.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:30 +10:00
Michael Neuling
0972def44f powerpc: Introduce new __REG_R macros
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:27 +10:00
Michael Neuling
cdaade7129 powerpc: Start using ___PPC_RA/B/S/T where necessary
Now have ___PPC_RA/B/S/T we can use it in some places.  These are
places where we can't use the existing defines which will soon enforce
R0-R31 usage.

The macros being changed here are being used in inline asm, which
can't convert to enforce the R0-R31 usage.

bpf_jit uses a mix of both generated and non-generated with the same
code, so just convert all these to use the ___PPC_R versions which
won't enforce R usage later.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:25 +10:00
Michael Neuling
55a5db1846 powerpc: Introduce new ___PPC_RA/B/S/T macros
These are currently the same as __PPC_RA/B/S/T but we'll wrap them
soon.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:22 +10:00
Michael Neuling
178f2ae092 powerpc: Fix VSX macros so register names aren't wrapped
We need to do this so we can enforce the name of a and b in called
macros PPC_RA/B later.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:19 +10:00
Michael Neuling
e55174e911 powerpc: Fixes for instructions not using correct register naming
These macros are using integers where they could be using logical
names since they take registers.

We are going to enforce this soon, so fix these up now.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:16 +10:00
Michael Neuling
03a22bfcfd powerpc: Change LOAD_REG_ADDR to use real register names
LOAD_REG_ADDR define is just a wrapper around real instructions so we
can just use real register names here (ie. lower case).

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:14 +10:00
Michael Neuling
86e32fdce7 powerpc: Change mtcrf to use real register names
mtocrf define is just a wrapper around the real instructions so we can
just use real register names here (ie. lower case).

Also remove braces in macro so this is possible.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:11 +10:00
Benjamin Herrenschmidt
b38c77d82e powerpc: Move and fix MTMSR_EERI definition
Move this duplicated definition to ppc_asm.h and remove the
braces which prevent the use of %rN register names

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:08 +10:00
Michael Neuling
d72be892c8 powerpc: Merge VCPU_GPR
Merge the defines of VCPU_GPR from different places.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-07-10 19:18:06 +10:00