includes:
- addition of sound subsystem related clocks for Exynos5410 SoC
(EPLL, PDMA) and support for "samsung,exynos5410-audss-clock"
compatible in the clk-exynos-audss driver,
- addition of DRAM controller related clocks for exynos5420,
- MAINTAINERS update adding Chanwoo Choi as the Samsung SoC
clock drivers co-maintainer.
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Merge tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull samsung clk driver updates from Sylwester Nawrocki:
In addition to a few clean up and code consolidation patches this
includes:
- addition of sound subsystem related clocks for Exynos5410 SoC
(EPLL, PDMA) and support for "samsung,exynos5410-audss-clock"
compatible in the clk-exynos-audss driver,
- addition of DRAM controller related clocks for exynos5420,
- MAINTAINERS update adding Chanwoo Choi as the Samsung SoC
clock drivers co-maintainer.
* tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: Add support for EPLL on exynos5410
clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanup
clk: samsung: clk-exynos-audss: Add exynos5410 compatible
clk: samsung: clk-exynos-audss: controller variant handling rework
clk: samsung: Use common registration function for pll2550x
clk: samsung: exynos5410: Expose the peripheral DMA gate clocks
clk: samsung: exynos5420: Add clocks for CMU_CDREX domain
clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify code
clk: samsung: exynos5260: Move struct samsung_cmu_info to init section
MAINTAINERS: Add myself as Samsung SoC clock drivers co-maintainer
clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks
clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)
There is no such significant differences in pll2550x PLL type
to justify a separate registration function. This patch adapts
exynos5440 driver to use the common function and removes
samsung_clk_register_pll2550x().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
The PDMA{0,1} and EPLL clock IDs are added separately in this
patch so the patch can be merged to the arm-soc tree as dependency.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
This patch adds missing clock IDs for CMU_CDREX (DRAM Express Controller)
which generates clocks for DRAM and NoC (Network on Chip) busses.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
control. While reading that clock is done the normal way from the
registers, setting it always requires some sort of special handling
to let the system survive this addition.
As the commit message explains, there are currently 3 handling-types
known. General SRAM-based code on rk3288 and before (which is waiting
essentially for the PIE support that is currently being worked on),
SCPI-based clk setting on the rk3368 through a coprocessor, which we
might support once the support for legacy scpi-variants has matured
and now on the rk3399 (and probably later) using a dcf controller that
is controlled from the arm-trusted-firmware and gets accessed through
firmware calls from the kernel. This is the variant we currently
support, but the clock type is made to support the other variants in
the future as well.
Apart from that slightly bigger chunk, we have a mix of PLL rates,
clock-ids and flags mainly for the rk3399.
And interestingly an iomap fix for the legacy gate driver, where I
hopefully could deter the submitter from actually using that in any
new works.
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Merge tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
The biggest addition is probably the special clock-type for ddr clock
control. While reading that clock is done the normal way from the
registers, setting it always requires some sort of special handling
to let the system survive this addition.
As the commit message explains, there are currently 3 handling-types
known. General SRAM-based code on rk3288 and before (which is waiting
essentially for the PIE support that is currently being worked on),
SCPI-based clk setting on the rk3368 through a coprocessor, which we
might support once the support for legacy scpi-variants has matured
and now on the rk3399 (and probably later) using a dcf controller that
is controlled from the arm-trusted-firmware and gets accessed through
firmware calls from the kernel. This is the variant we currently
support, but the clock type is made to support the other variants in
the future as well.
Apart from that slightly bigger chunk, we have a mix of PLL rates,
clock-ids and flags mainly for the rk3399.
And interestingly an iomap fix for the legacy gate driver, where I
hopefully could deter the submitter from actually using that in any
new works.
* tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: use the dclk_vop_frac clock ids on rk3399
clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers
clk: rockchip: add 2016M to big cpu clk rate table on rk3399
clk: rockchip: add rk3399 ddr clock support
clk: rockchip: add dclk_vop_frac ids for rk3399 vop
clk: rockchip: add new clock-type for the ddrclk
soc: rockchip: add header for ddr rate SIP interface
clk: rockchip: add SCLK_DDRC id for rk3399 ddrc
clk: rockchip: handle of_iomap failures in legacy clock driver
clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical
clk: rockchip: use general clock flag when registering pll
clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399
clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI
Export the dclk_vop_frac out, so we can set the dclk_vop as the
child of dclk_vop_frac, and then we can start to take use of
the fractional dividers.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Only expose future CLKID constants if necessary. This patch
removes CLK_NR_CLKS from the DT bindings but leaves all previously
defined CLKIDs there to keep backward compatibility.
Signed-off-by: Alexander Müller <serveralex@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-5-git-send-email-serveralex@gmail.com
Add BIMC gdsc data found in MMCC part of msm8996 family of devices.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add documentations and dt-bindings headers for the AO clock and reset
controller.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Dt-binding file about reset controller is used to provide
kinds of definition, which is referenced by dts file and
IC-specified reset controller driver code.
Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Tested-by: John Crispin <blogic@openwrt.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk-qcom-9615:
dt-bindings: clock: Update bindings for MDM9615 GCC and LCC
clk: mdm9615: Add support for MDM9615 Clock Controllers
dt-bindings: Add MDM9615 DT bindings include files for GCC and LCC
Add the SD/eMMC gate clocks and expose them for use by DT.
While at it, also explose FCLK_DIV2 since this is one of the input
clocks to the mux internal to each of the SD/eMMC blocks.
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Maxim has used the same clock IP on multiple PMICs like MAX77686,
MAX77802, MAX77620. Only differences are the number of clocks
from these PMICs like MAX77686 has 3 clocks output, MAX776802 have
two clock output and MAX77620 has one clock output.
Add clock binding details and DT example for the MAX77620.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Device tree contents continue to be the largest branches we submit. This
time around, some of the contents worth pointing out is:
- New SoC platforms:
- Freescale i.MX 7Solo
- Broadcom BCM23550
- Cirrus Logic EP7209 and EP7211 (clps711x platforms)_
- Hisilicon HI3519
- Renesas R8A7792
Some of the other delta that is sticking out, line-count wise:
- Exynos moves of IP blocks under an SoC bus, which causes a large delta due
to indentation changes
- A new Tegra K1 board: Apalis
- A bunch of small updates to many Allwinner platforms; new hardware support,
some cleanup, etc.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"Device tree contents continue to be the largest branches we submit.
This time around, some of the contents worth pointing out is:
New SoC platforms:
- Freescale i.MX 7Solo
- Broadcom BCM23550
- Cirrus Logic EP7209 and EP7211 (clps711x platforms)_
- Hisilicon HI3519
- Renesas R8A7792
Some of the other delta that is sticking out, line-count wise:
- Exynos moves of IP blocks under an SoC bus, which causes a large
delta due to indentation changes
- a new Tegra K1 board: Apalis
- a bunch of small updates to many Allwinner platforms; new hardware
support, some cleanup, etc"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits)
ARM: dts: sun8i: Add dts file for inet86dz board
ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet
ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts
ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04
ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply
ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi
ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts
ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts
ARM: dts: sun5i: reference-design-tablet: Remove mention of q8
ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc
ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi
ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts
ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi
ARM: dts: at91: Don't build unnecessary dtbs
ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions
ARM: dts: at91: at91sam9g25ek: fix isi endpoint node
ARM: dts: at91: move isi definition to at91sam9g25ek
ARM: dts: at91: fix i2c-gpio node name
ARM: dts: at91: vinco: fix regulator name
ARM: dts: at91: ariag25 : fix onewire node
...
Driver updates for ARM SoCs.
A slew of changes this release cycle. The reset driver tree, that we merge
through arm-soc for historical reasons, is also sizable this time around.
Among the changes:
- clps711x: Treewide changes to compatible strings, merged here for simplicity.
- Qualcomm: SCM firmware driver cleanups, move to platform driver
- ux500: Major cleanups, removal of old mach-specific infrastructure.
- Atmel external bus memory driver
- Move of brcmstb platform to the rest of bcm
- PMC driver updates for tegra, various fixes and improvements
- Samsung platform driver updates to support 64-bit Exynos platforms
- Reset controller cleanups moving to devm_reset_controller_register() APIs
- Reset controller driver for Amlogic Meson
- Reset controller driver for Hisilicon hi6220
- ARM SCPI power domain support
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Driver updates for ARM SoCs.
A slew of changes this release cycle. The reset driver tree, that we
merge through arm-soc for historical reasons, is also sizable this
time around.
Among the changes:
- clps711x: Treewide changes to compatible strings, merged here for simplicity.
- Qualcomm: SCM firmware driver cleanups, move to platform driver
- ux500: Major cleanups, removal of old mach-specific infrastructure.
- Atmel external bus memory driver
- Move of brcmstb platform to the rest of bcm
- PMC driver updates for tegra, various fixes and improvements
- Samsung platform driver updates to support 64-bit Exynos platforms
- Reset controller cleanups moving to devm_reset_controller_register() APIs
- Reset controller driver for Amlogic Meson
- Reset controller driver for Hisilicon hi6220
- ARM SCPI power domain support"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (100 commits)
ARM: ux500: consolidate base platform files
ARM: ux500: move soc_id driver to drivers/soc
ARM: ux500: call ux500_setup_id later
ARM: ux500: consolidate soc_device code in id.c
ARM: ux500: remove cpu_is_u* helpers
ARM: ux500: use CLK_OF_DECLARE()
ARM: ux500: move l2x0 init to .init_irq
mfd: db8500 stop passing around platform data
ASoC: ab8500-codec: remove platform data based probe
ARM: ux500: move ab8500_regulator_plat_data into driver
ARM: ux500: remove unused regulator data
soc: raspberrypi-power: add CONFIG_OF dependency
firmware: scpi: add CONFIG_OF dependency
video: clps711x-fb: Changing the compatibility string to match with the smallest supported chip
input: clps711x-keypad: Changing the compatibility string to match with the smallest supported chip
pwm: clps711x: Changing the compatibility string to match with the smallest supported chip
serial: clps711x: Changing the compatibility string to match with the smallest supported chip
irqchip: clps711x: Changing the compatibility string to match with the smallest supported chip
clocksource: clps711x: Changing the compatibility string to match with the smallest supported chip
clk: clps711x: Changing the compatibility string to match with the smallest supported chip
...
In the updates:
* Big endian support and preparation for defered probing for the
Exynos IOMMU driver
* Simplifications in iommu-group id handling
* Support for Mediatek generation one IOMMU hardware
* Conversion of the AMD IOMMU driver to use the generic IOVA
allocator. This driver now also benefits from the recent
scalability improvements in the IOVA code.
* Preparations to use generic DMA mapping code in the Rockchip
IOMMU driver
* Device tree adaption and conversion to use generic page-table
code for the MSM IOMMU driver
* An iova_to_phys optimization in the ARM-SMMU driver to greatly
improve page-table teardown performance with VFIO
* Various other small fixes and conversions
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Merge tag 'iommu-updates-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel:
- big-endian support and preparation for defered probing for the Exynos
IOMMU driver
- simplifications in iommu-group id handling
- support for Mediatek generation one IOMMU hardware
- conversion of the AMD IOMMU driver to use the generic IOVA allocator.
This driver now also benefits from the recent scalability
improvements in the IOVA code.
- preparations to use generic DMA mapping code in the Rockchip IOMMU
driver
- device tree adaption and conversion to use generic page-table code
for the MSM IOMMU driver
- an iova_to_phys optimization in the ARM-SMMU driver to greatly
improve page-table teardown performance with VFIO
- various other small fixes and conversions
* tag 'iommu-updates-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (59 commits)
iommu/amd: Initialize dma-ops domains with 3-level page-table
iommu/amd: Update Alias-DTE in update_device_table()
iommu/vt-d: Return error code in domain_context_mapping_one()
iommu/amd: Use container_of to get dma_ops_domain
iommu/amd: Flush iova queue before releasing dma_ops_domain
iommu/amd: Handle IOMMU_DOMAIN_DMA in ops->domain_free call-back
iommu/amd: Use dev_data->domain in get_domain()
iommu/amd: Optimize map_sg and unmap_sg
iommu/amd: Introduce dir2prot() helper
iommu/amd: Implement timeout to flush unmap queues
iommu/amd: Implement flush queue
iommu/amd: Allow NULL pointer parameter for domain_flush_complete()
iommu/amd: Set up data structures for flush queue
iommu/amd: Remove align-parameter from __map_single()
iommu/amd: Remove other remains of old address allocator
iommu/amd: Make use of the generic IOVA allocator
iommu/amd: Remove special mapping code for dma_ops path
iommu/amd: Pass gfp-flags to iommu_map_page()
iommu/amd: Implement apply_dm_region call-back
iommu/amd: Create a list of reserved iova addresses
...
drivers, along with a pretty standard number of new drivers. The core
recieved a small number of updates as well.
Core changes of note:
* Removed CLK_IS_ROOT flag
New clk provider drivers:
* Renesas r8a7796 Clock Pulse Generator / Module Standby and Software
Reset
* Allwinner sun8i H3 Clock Controller Unit
* AmLogic meson8b clock controller (rewritten)
* AmLogic gxbb clock controller
* Support for some new ICs was added by simple changes to static data
tables for chips sharing the same family
Driver updates of note:
* the Allwinner sunxi clock driver infrastucture was rewritten to
comform to the state of the art at drivers/clk/sunxi-ng. The old
implementation is still supported for backwards compatibility with the
DT ABI
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Merge tag 'clk-for-linus-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Michael Turquette:
"The bulk of the changes are updates and fixes to existing clk provider
drivers, along with a pretty standard number of new drivers. The core
recieved a small number of updates as well.
Core changes of note:
- removed CLK_IS_ROOT flag
New clk provider drivers:
- Renesas r8a7796 clock pulse generator / module standby and
software reset
- Allwinner sun8i H3 clock controller unit
- AmLogic meson8b clock controller (rewritten)
- AmLogic gxbb clock controller
- support for some new ICs was added by simple changes to static
data tables for chips sharing the same family
Driver updates of note:
- the Allwinner sunxi clock driver infrastucture was rewritten to
comform to the state of the art at drivers/clk/sunxi-ng. The old
implementation is still supported for backwards compatibility with
the DT ABI"
* tag 'clk-for-linus-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits)
clk: Makefile: re-sort and clean up
Revert "clk: gxbb: expose CLKID_MMC_PCLK"
clk: samsung: Allow modular build of the Audio Subsystem CLKCON driver
clk: samsung: make clk-s5pv210-audss explicitly non-modular
clk: exynos5433: remove CLK_IGNORE_UNUSED flag from SPI clocks
clk: oxnas: Add hardware dependencies
clk: imx7d: do not set parent of ethernet time/ref clocks
ARM: dt: sun8i: switch the H3 to the new CCU driver
clk: sunxi-ng: h3: Fix Kconfig symbol typo
clk: sunxi-ng: h3: Fix audio clock divider offset
clk: sunxi-ng: Add H3 clocks
clk: sunxi-ng: Add N-K-M-P factor clock
clk: sunxi-ng: Add N-K-M Factor clock
clk: sunxi-ng: Add N-M-factor clock support
clk: sunxi-ng: Add N-K-factor clock support
clk: sunxi-ng: Add M-P factor clock support
clk: sunxi-ng: Add divider
clk: sunxi-ng: Add phase clock support
clk: sunxi-ng: Add mux clock support
clk: sunxi-ng: Add gate clock support
...
New drivers:
- New driver for Oxnas pin control and GPIO. This ARM-based chipset
is used in a few storage (NAS) type devices.
- New driver for the MAX77620/MAX20024 pin controller portions.
- New driver for the Intel Merrifield pin controller.
New subdrivers:
- New subdriver for the Qualcomm MDM9615
- New subdriver for the STM32F746 MCU
- New subdriver for the Broadcom NSP SoC.
Cleanups:
- Demodularization of bool compiled-in drivers.
Apart from this there is just regular incremental improvements to
a lot of drivers, especially Uniphier and PFC.
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Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.8 kernel cycle.
Nothing stands out as especially exiting: new drivers, new subdrivers,
lots of cleanups and incremental features.
Business as usual.
New drivers:
- New driver for Oxnas pin control and GPIO. This ARM-based chipset
is used in a few storage (NAS) type devices.
- New driver for the MAX77620/MAX20024 pin controller portions.
- New driver for the Intel Merrifield pin controller.
New subdrivers:
- New subdriver for the Qualcomm MDM9615
- New subdriver for the STM32F746 MCU
- New subdriver for the Broadcom NSP SoC.
Cleanups:
- Demodularization of bool compiled-in drivers.
Apart from this there is just regular incremental improvements to a
lot of drivers, especially Uniphier and PFC"
* tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits)
pinctrl: fix pincontrol definition for marvell
pinctrl: xway: fix typo
Revert "pinctrl: amd: make it explicitly non-modular"
pinctrl: iproc: Add NSP and Stingray GPIO support
pinctrl: Update iProc GPIO DT bindings
pinctrl: bcm: add OF dependencies
pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe()
pinctrl: Add STM32F746 MCU support
pinctrl: intel: Protect set wake flow by spin lock
pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe()
pinctrl: uniphier: add Ethernet pin-mux settings
sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code
pinctrl: ns2: fix return value check in ns2_pinmux_probe()
pinctrl: qcom: update DT bindings with ebi2 groups
pinctrl: qcom: establish proper EBI2 pin groups
pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro
Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
includes: dt-bindings: Add STM32F746 pinctrl DT bindings
pinctrl: sunxi: fix nand0 function name for sun8i
pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11
...
This reverts commit e16fb2e635.
Updated documentation from the chip vendor reveals that this clock is
not required for correct operation of the MMC controller. As such, do
not expose it to DT.
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Simon Horman told me that R8A7792 has ADSP clock based on an incorrect
table in the most recent R-Car gen2 manual. But when I received that manual
I discovered that this is false: R8A7792 is the only Gen 2 SoC that doesn't
have ADSP at all. Accordingly remove the ADSP clock from DT for the
r8a7792.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Merge "STi late updates for v4.8" from Patrice Chotard:
- Add STi DT critical clocks declaration
- Remove SPI hack wich has dependecy with critical clocks
These 2 STi DT patches and SPI hack MUST be applied after patches
contained into Stephen Boyd's branch clk-next/clk-st-critical.
This to ensure not to break SPI.
* tag 'sti-late-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
spi: st-ssc4: Remove 'no clocking' hack
ARM: sti: stih410-clocks: Identify critical clocks
ARM: sti: stih407-family: Supply defines for CLOCKGEN A0
clk: st: clkgen-pll: Detect critical clocks
clk: st: clkgen-fsyn: Detect critical clocks
clk: st: clk-flexgen: Detect critical clocks
Merging this in avoids a build error that was missed earlier:
In file included from ../arch/arm/boot/dts/meson8b-mxq.dts:48:0:
../arch/arm/boot/dts/meson8b.dtsi:49:53: fatal error: dt-bindings/reset/amlogic,meson8b-reset.h: No such file or directory
* reset/for-4.8-2:
dt-bindings: reset: Add bindings for the Meson SoC Reset Controller
reset: Add support for the Amlogic Meson SoC Reset Controller
reset: Return -ENOTSUPP when not configured
reset: oxnas: Use devm register API and get rid of platform remove
reset: fix Kconfig menu to include reset drivers in sub-menu
reset: zynq: use devm_reset_controller_register()
reset: socfpga: use devm_reset_controller_register()
reset: sunxi: use devm_reset_controller_register()
reset: pistachio: use devm_reset_controller_register()
reset: ath79: use devm_reset_controller_register()
reset: add devm_reset_controller_register API
There are 2 LMI clocks generated by CLOCKGEN A0. We wish to control
them individually and need to use these indexes to do so.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The MMC_PCLK is needed for the SD/eMMC driver, expose to DT (and comment
out in clk driver)
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160707033837.20029-1-khilman@baylibre.com
- change request API to be more explicit about the difference between
exclusive and shared resets (the former guarantee the reset line is
asserted immediately when reset_control_assert is called, the latter
are refcounted and do not guarantee this).
- add Hisilicon hi6220 media subsystem reset controller support
- add TI SYSCON based reset controller support
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Merge tag 'reset-for-4.8-3' of git://git.pengutronix.de/git/pza/linux into next/drivers
Merge "Reset controller changes for v4.8, part 3" from Philipp Zabel:
- change request API to be more explicit about the difference between
exclusive and shared resets (the former guarantee the reset line is
asserted immediately when reset_control_assert is called, the latter
are refcounted and do not guarantee this).
- add Hisilicon hi6220 media subsystem reset controller support
- add TI SYSCON based reset controller support
* tag 'reset-for-4.8-3' of git://git.pengutronix.de/git/pza/linux:
reset: add TI SYSCON based reset driver
Documentation: dt: reset: Add TI syscon reset binding
reset: hisilicon: Add hi6220 media subsystem reset support
reset: hisilicon: Change to syscon register access
arm64: dts: hi6220: Add media subsystem reset dts
reset: hisilicon: Add media reset controller binding
reset: TRIVIAL: Add line break at same place for similar APIs
reset: Supply *_shared variant calls when using *_optional APIs
reset: Supply *_shared variant calls when using of_* API
reset: Ensure drivers are explicit when requesting reset lines
reset: Reorder inline reset_control_get*() wrappers
as well as i2s and ethernet support on rk3228/rk3229 devices
and a dts file for the rk3229 eval board.
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Merge tag 'v4.8-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Audio support and spi-flash on rk3288-veyron Chromedevices
as well as i2s and ethernet support on rk3228/rk3229 devices
and a dts file for the rk3229 eval board.
* tag 'v4.8-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add support rk3229 evb board
ARM: dts: rockchip: add GMAC nodes for RK322x SoCs
ARM: dts: rockchip: add i2s nodes for RK322x SoCs
ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi
clk: rockchip: add clock-ids for rk3228 MAC clocks
clk: rockchip: add clock-ids for rk3228 audio clocks
ARM: dts: rockchip: rename i2s model for Veyron devices
ARM: dts: rockchip: move rk3288 io-domain nodes to the grf
ARM: dts: rockchip: Enable analog audio on rk3288-veyron chromebooks
ARM: dts: rockchip: Add shared file for audio on rk3288-veyron boards
ARM: dts: rockchip: add SPI flash node for rk3288-veyron
Signed-off-by: Olof Johansson <olof@lixom.net>
* Use APMU on R-Car Gen2 and provide SMP for r8a7793 SoC
* Update console parameters to uniformly use chosen/stdout-path,
serial0, not provide kernel unnecessary command line parameters
* Add DU pins to silk board
* Add support for blanche/r8a7792
* Name pfc subnodes after device name
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Merge tag 'renesas-dt2-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Second Round of Renesas ARM Based SoC DT Updates for v4.8
* Use APMU on R-Car Gen2 and provide SMP for r8a7793 SoC
* Update console parameters to uniformly use chosen/stdout-path,
serial0, not provide kernel unnecessary command line parameters
* Add DU pins to silk board
* Add support for blanche/r8a7792
* Name pfc subnodes after device name
* tag 'renesas-dt2-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (41 commits)
ARM: dts: r8a7792: add SMP support
ARM: dts: r8a7793: Add APMU node and second CPU core
ARM: dts: r8a7791: Add APMU node
ARM: dts: r8a7790: Add APMU nodes
devicetree: bindings: Renesas APMU and SMP Enable method
ARM: dts: kzm9g: Update console parameters
ARM: dts: kzm9d: Update console parameters
ARM: dts: marzen: Add serial port config to chosen/stdout-path
ARM: dts: genmai: Update console parameters
ARM: dts: armadillo800eva: Update console parameters
ARM: dts: r8a7792: add JPU support
ARM: dts: r8a7792: add JPU clocks
ARM: dts: silk: add DU pins
ARM: dts: blanche: add Ethernet support
ARM: dts: blanche: initial device tree
ARM: dts: blanche: document Blanche board
ARM: dts: r8a7792: add IRQC support
ARM: dts: r8a7792: add [H]SCIF support
ARM: dts: r8a7792: add SYS-DMAC support
ARM: dts: r8a7792: initial SoC device tree
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch add the support to select the peripheral clock (PERIPH)
as a parent clock source using the "assigned-clock-parents"
parameter in the device tree.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1464982475-24738-1-git-send-email-slemieux.tyco@gmail.com
rk3228 clockids and a small fix for the not yet used spdif to
displayport clock on the rk3399.
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Merge tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
Placeholder for the rk3399 watchdog pclk, some newly exported
rk3228 clockids and a small fix for the not yet used spdif to
displayport clock on the rk3399.
* tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
clk: rockchip: export rk3228 MAC clocks
clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk
clk: rockchip: export rk3228 audio clocks
clk: rockchip: include rk3228 downstream muxes into fractional dividers
clk: rockchip: fix incorrect rk3228 clock registers
clk: rockchip: add clock-ids for rk3228 MAC clocks
clk: rockchip: add clock-ids for rk3228 audio clocks
clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
Fixes and enhancements mostly for Tegra210 clocks that allow DSI and
HDMI to work on Tegra X1. There's also a refactoring, including fixes,
the USB PLL.
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Merge tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
Pull tegra clk driver updates from Thierry Reding:
Fixes and enhancements mostly for Tegra210 clocks that allow DSI and
HDMI to work on Tegra X1. There's also a refactoring, including fixes,
the USB PLL.
* tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: Initialize UTMI PLL when enabling PLLU
clk: tegra: Micro-optimize Tegra210 clock setup
clk: tegra: Make sor_safe the parent of dpaux and dpaux1
clk: tegra: Mark timer clock as critical
clk: tegra: Enable sor1 and sor1_src on Tegra210
clk: tegra: Squash sor1 safe/brick/src into a single mux
clk: tegra: Disable spread spectrum on pll_d2
clk: tegra: Fixup post dividers on Tegra210
