This change adds support for the sh7372 A4R power domain.
The sh7372 A4R hardware power domain contains the
SH CPU Core and a set of I/O devices including
multimedia accelerators and I2C controllers.
One special case about A4R is the INTCS interrupt
controller that needs to be saved and restored to
keep working as expected. Also the LCDC hardware
blocks are in a different hardware power domain
but have their IRQs routed only through INTCS. So
as long as LCDCs are active we cannot power down
INTCS because that would risk losing interrupts.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This change adds support for the sh7372 A3SP power domain.
The sh7372 A3SP hardware power domain contains a
wide range of I/O devices. The list of I/O devices
include SCIF serial ports, DMA Engine hardware,
SD and MMC controller hardware, USB controllers
and I2C master controllers.
This patch adds the A3SP low level code which
powers the hardware power domain on and off. It
also ties in platform devices to the pm domain
support code.
It is worth noting that the serial console is
hooked up to SCIFA0 on most sh7372 boards, and
the SCIFA0 port is included in the A3SP hardware
power domain. For this reason we cannot output
debug messages from the low level power control
code in the case of A3SP.
QoS support is needed in drivers before we can
enable the A3SP power control on the fly.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Merge commit e8b364b88c
(PM / Clocks: Do not acquire a mutex under a spinlock) fixing
a regression in drivers/base/power/clock_ops.c.
Conflicts:
drivers/base/power/clock_ops.c
Instead of coding the undocumented dependencies between power domains
A3RV and A4LC on SH7372 directly into the low-level power up/down
routines, make A3RV be a subdomain of A4LC, which will cause the
same dependecies to hold.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Magnus Damm <damm@opensource.se>
Switch the sh7372 CPU support to use CMT2 instead
of CMT1 for system timer.
CMT1 is located in the A3SP power domain while CMT2
is located in the always-on power domain C5.
This improves our PM situation - with CMT2 as timer
we can power down A3SP and still access the timer.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add support for the sh7372 D4 power domain. This power domain
contains the Coresight-ETM hardware block.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Add support for the sh7372 A4MP power domain
and hook up the FSI/SPU2 device.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Add support for the sh7372 A3SG power domain. This domain contains
the SGX hardware block, but there is no open source driver available.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Add support for the sh7372 A3RI power domain. This domain contains
the ISP hardware block, but there is no driver available.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Add support for the sh7372 A3RV power domain and hook
up the VPU device.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
The AP4EVB board is also using a sh7372 SoC, so tie in
A4LC support on that board as well.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Export the following sh7372 multimedia hardware blocks
using UIO: VPU, VEU[0-3], JPU and SPU2[0-1]
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add DMA slave IDs and slave definitions for MMCIF on sh7372.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds support for the two first channels of
the TMU0 timer block on sh7372. One channel is used
for clock event, the other for clock source.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Move SH-Mobile ARM systems over from the legacy
"clk" member of struct sh_timer_config to using
the device name and clkdev for clock matching.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch introduces sh7372_late_devices which
should include all regular processor specific
platform devices.
Early platform devices for console and timers
should be put on the sh7372_early_devices list,
all other devices should be on sh7372_late_devices.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Use evt2irq() for DMAC resources on sh7372.
This makes the code easier to read and also
allows adjusting the INTC base offset without
breaking platform data.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
SH7372 can use DMA with the SCI serial driver. Add required slave IDs and slave
descriptors.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds DMA support for the sh7372 sh-mobile ARM core, using the shdma
dmaengine driver, and uses DMA for the SDHI SD-card controller on this SoC.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The current SH7372 setup code registers 7 SCIF ports, which is wrong.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch updates the irq numbers on sh7372/AP4EVB
to make use of evt2irq() and intcs_evt2irq().
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch is V2 of clock framework tables/code for sh7372.
MSTP are included for KEYSC, SCIF, IIC, USB, SDHI and UIO.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh7372 chip has 2 INTC.
Then, I2C0 is connected to INTCS, and I2C1 is connected to INTCA.
Both of these has no GPIO settings.
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds preliminary support for the SH7372 (SH-Mobile AP4) CPU and
the AP4EVB reference board.
Only timer, serial console and NOR flash are supported at this point.
Support for the interrupt controller, pinmux support, clock framework
and runtime pm will be submitted as feature patches on top of this.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
