Commit Graph

1033 Commits

Author SHA1 Message Date
Shaohua Li
311089d3d3 drm/i915: use msleep for intel_wait_for_vblank
20ms delay is quite big and the routine isn't called in atomic context.
better use msleep to let other tasks run. This can reduce cpu time used
by Xorg, so potentially boost boot.

Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-30 09:39:57 -08:00
Shaohua Li
1991bdfaf5 drm/i915: handle failure path correctly for lvds
In failure path, make sure encoder is cleaned up, otherwise there
is a kernel oops.

Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-25 13:45:55 -08:00
Zhenyu Wang
1b3c7a47f9 drm/i915: Fix LVDS stability issue on Ironlake
In disable sequence, all output ports on PCH have to be disabled
before PCH transcoder, but LVDS port was left always enabled. This
one fixes that by disable LVDS port properly during pipe disable
process, and resolved stability issue seen on Ironlake. Also move
panel fitting disable time just after pipe disable to align with
the spec.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-25 13:09:35 -08:00
Zhao Yakui
4215866059 drm/i915: Restore the DPLL calculation logic for 9xx platform
The DPLL calculation logic for 9xx platform is changed in:
commit 652c393a33
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Mon Aug 17 13:31:43 2009 -0700

    drm/i915: add dynamic clock frequency control

Maybe we will get the different M/N/P combination with that by using the
previous dpll calculation logic.

So restore the DPLL calculation logic for 9xx platform.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-25 13:03:12 -08:00
Zhao Yakui
d1fcea6a52 drm/i915: Check whether the LVDS downclock is found in VBT
Enumerate the LVDS panel timing info entry list in VBT to check whether
the LVDS downclock is found. If found, the downclock is also used to switch
dynamically between low and high frequency for LVDS.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-25 13:02:33 -08:00
Zhao Yakui
18f9ed12f8 drm/i915: Enable LVDS downclock feature through EDID.
If more than one mode with the same resolution defined in EDID has different
refresh rate, it is thought that the downclock is found for LVDS.
We will program the different FPx0/1 register so that we can select dynamically
between the low and high frequency.

On the g4x platform we will use the CxSR feature to switch the different
refresh rate if the LVDS downclock feature is supported.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-25 12:46:41 -08:00
Eric Anholt
c8e0f93a38 drm/i915: Replace a calloc followed by copying data over it with malloc.
Execbufs involve quite a bit of payload, to the extent that cache misses
show up in the profiles here, and a suspicion that some of those cachelines
may get evicted and then reloaded in the subsequent copy.

This is still abstracted like drm_calloc_large since we want to check for
size overflow, and because we want to choose between kmalloc and vmalloc
on the fly.  cairo's interface for malloc-with-calloc's-args was used as
the model.

Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-25 06:36:21 -08:00
Eric Anholt
5b8f0be0dc Merge remote branch 'airlied/drm-next' into drm-intel-next 2009-11-05 15:04:06 -08:00
Daniel Vetter
43bcd61fae drm/i915: fix get_core_clock_speed for G33 class desktop chips
Somehow the case for G33 got dropped while porting from ums code.
This made a 400MHz chip into a 133MHz one which resulted in the
unnecessary enabling of double wide pipe mode which in turn
screwed up the overlay code.

Nothing else (than the overlay code) seems to be affected.

This fixes fdo.org bug #24835

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:57:39 -08:00
Zhenyu Wang
c650156af3 drm/i915: Add display hotplug event on Ironlake
Enable display hotplug irqs from Ibex Peak (PCH).

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:49:37 -08:00
Zhao Yakui
01c66889c1 drm/i915: Add ACPI OpRegion support for Ironlake
Add the support of ACPI opregion on Ironlake so that the backlight
brightness can be adjusted by using ACPI interface
   >/sys/class/backlight/acpi_video0/brightness

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Tested-by: Zhao Yakui <yakui.zhao@intel.com>
[zhenyuw: cleanups, fix typo for checking GSE irq and convert to
current irq handling logic.]
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:49:13 -08:00
Jesse Barnes
1dc7546d1a drm/i915: enable self-refresh on 965
Need to calculate the SR watermark and enable it.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:14 -08:00
Kristian Høgsberg
a4f45cf178 drm/i915: Support 30 bit depth modes
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:13 -08:00
Chris Wilson
f3cd474bb2 drm/i915: debugfs interface to manually reset the GPU
Create a /debug/dri/%d/i915_wedged file to display the current wedged
status, and to enable setting that value. On an i965, this will also
trigger a GPU reset.

Useful in order to attempt to recover from some error conditions that
are not currently caught by the automatic hang detection code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:13 -08:00
Chris Wilson
aed5f1dc26 drm/i915: Use a single thread workqueue
Our work is serialised so allocating per-cpu workqueues is overkill and
a waste of resources.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:12 -08:00
Zhao Yakui
d0c3b04ae9 drm/i915: Replace DRM_DEBUG with DRM_DEBUG_KMS in DVO output code.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:12 -08:00
Eric Anholt
3e0f27ed75 drm/i915: Enable the SDVO debug code, which is now under DEBUG_KMS.
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:11 -08:00
Zhao Yakui
28c97730c3 drm/i915: Replace DRM_DEBUG with DRM_DEBUG_KMS
Replace the DRM_DEBUG with DRM_DEBUG_KMS in output device code.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:11 -08:00
Zhao Yakui
44d98a6142 drm/i915: Replace DRM_DEBUG with DRM_DEBUG_DRIVER
Replace the DRM_DEBUG with DRM_DEBUG_DRIVER in generic i915 driver.
Then the debug info can be obtained by adding the boot option of
"drm.debug=0x02".

At the same time the debug info in increase/decrease clock is also
printed by using DRM_DEBUG_DRIVER instead of DRM_DEBUG_KMS.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:10 -08:00
Daniel Vetter
5c5a4359fe drm/i915: overlay: kill one more unnecessary uninterruptible sleep
I've simply overlooked one case in the conversion to interruptible
sleeps. Rectify this.

Also delete a leftover debug printk.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:10 -08:00
Daniel Vetter
1df4b35b61 drm/i915: kill i915_lp_ring_sync
It's not needed anymore.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:09 -08:00
Daniel Vetter
03f77ea597 drm/i915: implement interruptible sleeps in the overlay code
At least for the common case of userspace ioctls. When doing a
modeset operation, the wait is still uninterruptible. But considering
that failing to turn off the overlay when switching off the crtc it's
running on hangs the chip, it doesn't complicate matters _very_
much. There's just an unkillable X in addition to a black screen.
BUG() about it and explain in the code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:09 -08:00
Daniel Vetter
5a5a0c64a9 drm/i915: implement fastpath for overlay flip waiting
As long as the gpu can keep up, neither the cpu (waiting for gpu)
nore the gpu (waiting for vblank to do an overlay flip) stalls.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:09 -08:00
Daniel Vetter
240a2d12df drm/i915: fully switch off overlay when not in use
Now that the cache flushing of the memory based overlay regs works,
we can safely switch off the overlay. Beforehand it was only disabled
(like in userspace).

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:08 -08:00
Daniel Vetter
02e792fbaa drm/i915: implement drmmode overlay support v4
This implements intel overlay support for kms via a device-specific
ioctl. Thomas Hellstrom brought up the idea of a general ioctl (on
dri-devel). We've reached the conclusion that such an infrastructure
only makes sense when multiple kms overlay implementations exists,
which atm don't (and it doesn't look like this is gonna change).

Open issues:
- Runs in sync with the gpu, i.e. unnecessary waiting. I've decided
  to wait on this because the hw tends to hang when changing something
  in this area. I left some dummy functions as infrastructure.
- polyphase filtering uses a static table.
- uses uninterruptible sleeps. Unfortunately the alternatives may
  unnecessarily wedged the hw if/when we timeout too early (and
  userspace only overloaded the batch buffers with stuff worth a few
  secs of gpu time).

Changes since v1:
- fix off-by-one misconception on my side. This fixes fullscreen
  playback.
Changes since v2:
- add underrun detection as spec'ed for i965.
- flush caches properly, fixing visual corruptions.
Changes since v4:
- fix up cache flushing of overlay memory regs.
- killed require_pipe_a logic - it hangs the chip.

Tested-By: diego.abelenda@gmail.com (on a 865G)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[anholt: Resolved against the MADVISE ioctl going in before this one]
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:08 -08:00
Daniel Vetter
f0f8a9cece drm/i915: kill superflous IS_I855 macro
It is identical to I85X. Use that one instead.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[anholt: fix conflicts against the display function pointer stuff]
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:07 -08:00
Daniel Vetter
48764bf43f drm/i915: add i915_lp_ring_sync helper
This just waits until the hw passed the current ring position with
cmd execution. This slightly changes the existing i915_wait_request
function to make uninterruptible waiting possible - no point in
returning to userspace while mucking around with the overlay, that
piece of hw is just too fragile.

Also replace a magic 0 with the symbolic constant (and kill the then
superflous comment) while I was looking at the code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:07 -08:00
Daniel Vetter
7a9c906094 drm: make drm_mode_object_find typesafe
I've wasted half a day hunting a bug that could easily be spotted by
gcc. Prevent this from reoccurring.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:06 -08:00
Jesse Barnes
97f5ab6651 drm/i915: add render standby support
Render standy allows the GPU to power down the render unit when idle.
In order for this to work, it needs a page of graphics memory to save
state.  This patch allocates that page and enables the feature on
supported chipsets.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:06 -08:00
Zhenyu Wang
d8a2d0e00c drm/i915: HDMI hardware workaround for Ironlake
This brings some hardware workaround for HDMI port on PCH (Ibex Peak),
which fixes unstable issues like during rotation.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:03:28 -08:00
Zhenyu Wang
4bfe6b6876 drm/i915: Fix and cleanup DPLL calculation for Ironlake
When the ideal error range can't be reached, this will safely use
a most closed one. Clean up some dumb codes in DPLL function too.

This fixes DPLL clock issue against one monitor at 1680x1050@60hz.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:00:32 -08:00
Chris Wilson
ba86bf8bfc drm/i915: Avoid potential sleep whilst holding spinlock
Miles Lane reported the following error:
2 locks held by cat/4179:
  #0:  (&p->lock){+.+.+.}, at: [<c10a3884>] seq_read+0x25/0x315
  #1:  (&dev_priv->mm.active_list_lock){+.+...}, at: [<c119a854>]
i915_batchbuffer_info+0x2b/0x124
Pid: 4179, comm: cat Not tainted 2.6.32-rc5-git1 #2
Call Trace:
  [<c104874f>] ? __debug_show_held_locks+0x1e/0x20
  [<c1023fb0>] __might_sleep+0xf0/0xf7
  [<c101c393>] kmap+0x17/0x58
  [<c119a8d6>] i915_batchbuffer_info+0xad/0x124
  [<c10a39bf>] seq_read+0x160/0x315
  [<c108fb8c>] ? rw_verify_area+0x98/0xbb
  [<c10a385f>] ? seq_read+0x0/0x315
  [<c1090331>] vfs_read+0x75/0xa9
  [<c10903f9>] sys_read+0x3b/0x5d
  [<c1002a8f>] sysenter_do_call+0x12/0x36

The fix is relatively simple, use the atomic variants of kmap() that
avoid the potential sleep.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Miles Lane <miles.lane@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 13:33:22 -08:00
Dave Airlie
4fe9676d1a Merge branch 'drm-next' of ../drm-2.6 into drm-next 2009-11-05 08:28:54 +10:00
Linus Torvalds
91d3f9bacd Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
  drm/i915: Ironlake suspend/resume support
  drm/i915: kill warning in intel_find_pll_g4x_dp
  drm/i915: update watermarks before enabling PLLs
  drm/i915: add FIFO watermark support for G4x
  drm/i915: quiet DP i2c init
  drm/i915: fix panel fitting filter coefficient select for Ironlake
  drm/i915: fix to setup display reference clock control on Ironlake
  drm/i915: Install a fence register for fbc on g4x
  drm/i915: save/restore BLC histogram control reg across suspend/resume
  drm/i915: Fix FDI M/N setting according with correct color depth
  drm/i915: disable powersave feature for Ironlake currently
  drm/i915: Fix render reclock availability detection.
  drm/i915: Save and restore the GM45 FBC regs on suspend and resume.
  drm/i915: Set the LVDS_BORDER when using LVDS scaling mode
  drm/i915: disable FBC for Pineview, fixing a boot hang.
2009-11-04 07:05:43 -08:00
Alex Deucher
e29649db3b drm/radeon/kms/r700: fix some typos in chip init
Noticed by Andre on IRC.

Also fix up some minor whitespace issues.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-04 13:39:17 +10:00
Alex Deucher
6fa8d66af8 drm/radeon/kms: remove some misleading debugging output
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-04 13:38:02 +10:00
Dave Airlie
4d357abb89 drm/radeon/kms: stop putting VRAM at 0 in MC space on r600s.
The Lenovo W500 laptop hangs inside an SMI on brightness changes,
I thought it just needed the VGA disable but it turned out to require
slightly more work, setting the MC locations up just like the IGP
chip requirements seems to make it all happy again and I can boot
and play with brightness.

We should probably just do this for all chips and give up the VRAM
at 0x0 idea, it never seems to buy us anything but pain.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-04 12:12:44 +10:00
Dave Airlie
8a9832e89f drm/radeon/kms: disable D1VGA and D2VGA if enabled
Once kms is enabled we don't need these, and it causes a problem
with the Lenovo W500 ACPI brightness implementation, it hangs
in a loop inside an SMI.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-04 09:53:42 +10:00
Alex Deucher
d6f28938d9 drm/radeon/kms: Don't RMW CP_RB_CNTL
Immediate readback seems faulty on some chips.  I
suspect it takes a while to get through the fifo
to the actual register backbone.  There's no need
to read it back, so, just write the driver's copy
of the register's value directly.

Should fix bug 24535 and possibly 24218

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-04 09:53:25 +10:00
Dave Airlie
df67bed92f drm/radeon/kms: fix coherency issues on AGP cards.
When we are evicting from VRAM->RAM we allocate the ttm object,
but we don't set the caching policy on it before blitting into it.
This means on AGP we end up blitting into cached pages, and
the CPU later flushes out on top of them. This was mostly seen as
font corruption.

The other question is why we don't evict VRAM->GTT in a lot of cases,
this would save us some cache transitions since a lot of objects
that are evicted from VRAM will probably end up being pulled back in
a few operations later, and evicting them to system memory involves
2 unnecessary cache transitions.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-11-04 09:53:14 +10:00
Linus Torvalds
c9354c85c1 i915: fix intel graphics suspend breakage due to resume/lid event confusion
In commit c1c7af6089 ("drm/i915: force
mode set at lid open time") the intel graphics driver was taught to
restore the LVDS mode on lid open.

That caused problems with interaction with the suspend/resume code,
which commonly runs at the same time (suspend is often caused by the lid
close event, while lid open is commonly a resume event), which was
worked around with in commit 06891e27a9
("drm/i915: fix suspend/resume breakage in lid notifier").

However, in the meantime the lid event code had also grown a user event
notifier (commit 06324194ee: "drm/i915:
generate a KMS uevent at lid open/close time"), and now _that_ causes
problems with suspend/resume and some versions of Xorg reacting to those
uevents by setting the mode.

So this effectively reverts that commit 06324194ee, and makes the lid
open protection logic against suspend/resume more explicit.  This fixes
at least one laptop. See

	http://bugzilla.kernel.org/show_bug.cgi?id=14484

for more details.

Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Riccardo Magliocchetti <riccardo.magliocchetti@gmail.com>
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-11-02 09:29:55 -08:00
Dave Airlie
273fad2b82 Merge branch 'drm-next' of ../drm-2.6 into drm-next 2009-10-28 16:08:41 +10:00
Dave Airlie
ea1495a627 drm/radeon/kms: fix rc410 suspend/resume.
This fixes suspend/resume on my rc410 motherboard, it restores
the memory controller setup before posting the GPU, since it seems
to need the MC_FB_LOCATION setup correctly.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-10-28 16:01:58 +10:00
Alex Deucher
fc7f7119d2 drm/radeon/kms: add quirk for hp dc5750
Doesn't have a tv-out port

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-10-28 15:52:17 +10:00
Alex Deucher
d11aa88b33 drm/radeon/kms/atom: fix potential oops in spread spectrum code
Make sure we have an LVDS encoder before casting enc_priv.

[airlied: also fix two missing cpu_to_le16 casts we noticed on irc]

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-10-28 15:30:03 +10:00
James Simmons
a2d49ae7df drm/kms: typo fix
I believe this is a typo.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-10-28 15:26:56 +10:00
Mathias Fröhlich
61c4b24b3e drm/radeon/kms/atom: Make card_info per device
Make the struct card_info, which is a per struct radeon_device dataset, a
struct member of the radeon device instead of a static per kernel module
value. This should avoid potential problems with two radeon cards installed in
one system.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-10-28 13:34:21 +10:00
Alex Deucher
d56ef9c8fd drm/radeon/kms/atom: Fix DVO support
DVO in 12 bit mode (which seems to be the most common
config) requires 2x ppll.

Fixes fdo bug 21857.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-10-28 13:34:19 +10:00
Alex Deucher
8f552a66a4 drm/radeon/kms/atom: loosen pll min output limits
Limiting the pll output range is a good thing generally as
it limits the number of possible pll combinations for a given
frequency presumably to the ones that work best on each card.
That's why the limits are in the bios tables. However, certain
duallink DVI monitors seem to like pll combinations that would
be limited by this at least on pre-DCE 3.0 r6xx hardware.  This
might need to be adjusted per family or per clock range in the
future.

See fdo bug 24727.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-10-28 13:34:18 +10:00
Dave Airlie
77de0846ae drm/kms: fix kms/fbdev colormap support properly.
This sets the fbcon to use TRUECOLOR by default, it then
only modifies the pseudo palette for fbcon, and only touches
the real palette when in 8-bit pseudo color mode.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-10-28 11:23:48 +10:00