5780 Commits

Author	SHA1	Message	Date
Sylwester Nawrocki	2f25528e4e	clk: Add clk_bulk_get_optional() function ... clk_bulk_get_optional() allows to get a group of clocks where one or more is optional. For a not available clock, e.g. not specifed in the clock consumer node in DT, its respective struct clk pointer will be NULL. This allows for operating on a group of returned clocks (struct clk_bulk_data array) with existing clk_bulk* APIs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-06-25 14:28:01 -07:00
Linus Torvalds	815d469d8c	One more patch to remove io.h from clk-provider.h. We used to need this ... include when we had clk_readl() and clk_writel(), but those are gone now so this patch pushes the dependency out to the users of clk-provider.h. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlzdx/ERHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSUeJw/+NfQU+GwmfM1mXUnClTuJthKZRlXQTt4o KzD4VtdqWOPSPWF2QNUM3oG5+FxbmzxZBMMyAfWKO4MS/hYvD3wZOdbP56KvoUe6 I75FHSGYlXFMvohm6vjPvfx30IcBn0QZcP9bhP5B5h0UbIG9annbVWWNR2qBg+/O 4p3o33CPSIO5W3IblSWrFzuEOBXNlkJKTIZW2BcV33aUCbAD3wrvqoP5l7xBbDJN U+QC+4LoZtA1RSM03qOzHleXrXNhBjWNtxRqXCIu0hkmyVdPAHDg0tb745HdLUc+ PTRCCguU21ANJMf2hD0dYiRi5fSPSLzIqQ2uZW8O6/ChSIMsOrZ43tW1TsQ7E7ZD gGEu2aj5euPyTVh0HmWKXyqEEUF/fqywJtwNQSyNTzDvQd807Pabb1YoIzZz9w2S V+/PoDVYF90IN1DsuOnbTCQ/BK0bqUb+7BtkrCzJ1ip3FpdB3017zT1b5wIzLjfI 1NO3ub5iHGAiS1qzChGa3Va56CDjspx66atMomDaeOQsBC983GdWOerBunKxL3UM US7rhr9DgPz8p9DEFPeXQXABgZUV4ToBb8nD8b2U1eFiOZthg7CO5mKSuwPGXcBQ RsWwmxc87DZJJJno2abacK/h0ii/r8f+3+C9x98vtYewJEC5RHbJygYHcr3YNjo1 LOdCMassRT4= =JjQo -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull more clk framework updates from Stephen Boyd: "One more patch to remove io.h from clk-provider.h. We used to need this include when we had clk_readl() and clk_writel(), but those are gone now so this patch pushes the dependency out to the users of clk-provider.h" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: Remove io.h from clk-provider.h	2019-05-16 19:05:35 -07:00
Linus Torvalds	dc413a90ed	ARM: SoC-related driver updates ... Various driver updates for platforms and a couple of the small driver subsystems we merge through our tree: Among the larger pieces: - Power management improvements for TI am335x and am437x (RTC suspend/wake) - Misc new additions for Amlogic (socinfo updates) - ZynqMP FPGA manager - Nvidia improvements for reset/powergate handling - PMIC wrapper for Mediatek MT8516 - Misc fixes/improvements for ARM SCMI, TEE, NXP i.MX SCU drivers -----BEGIN PGP SIGNATURE----- iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlzc+9QPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx3o3sQAIJ2SZnITy/ycvkbhKe+V/806P+aoqMpbZDw 7ldBQFoIMQqVIoeSSeml+9B86ZGyK4CGTgnvsfAI/Zt2fZSHczjqLP5InbEnvB5M 4naf0nSjSlkb5F4p24wXQ7WTI8IO45SwqG4hCi/WW6MakxN21cwdMWHBn+TRZWQu +AlJdwyDFJoMRXcq8xvLHOBNVAqD3LyvlECbLKqn3+UPwwYw0Ti1dsLwaMLOYDbc o/1dC2O8111kg2DgO0OM4Tl7jdbpmGA5MeixbVnmu3t4b2s26trG33eXqK2yWqaV XigD85R74GAq/wmgnzjdiNaIgZjlPPitVYaTE4L6Od39zMgXemnsqMlh/byPeO2y JvRRLEIciNay9q9uq+8H2zRWwa2wLqAewjssTTMM0RJNQWUtonVCkD8DAx4GLDof 6Ej42XGbtxnqpf0g854mBJ4zaPfZLN4xK//1Llx9HkM8mhLZLJ7BQvgvW1JzniSa XKnmjqK7SySiJ4bbjn+aFk5EkX7Oh5aXno18tVNKXdxc8nWoEw4PHMUmCCHOFPye /1oxc95Ux8P/lV+B0ZjiI0yTAX/IpDkEszAYmgdy6pWh1hXnYUr/Rpm7cGUG8kzk SbtyB8JOI/DFQ7QMDfPp6e6bcB8zTbUuF9H2MXwPN5TqGzP/mya88DC5Iv1jY4jc 0oWv/uhj =YSfu -----END PGP SIGNATURE----- Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms and a couple of the small driver subsystems we merge through our tree: Among the larger pieces: - Power management improvements for TI am335x and am437x (RTC suspend/wake) - Misc new additions for Amlogic (socinfo updates) - ZynqMP FPGA manager - Nvidia improvements for reset/powergate handling - PMIC wrapper for Mediatek MT8516 - Misc fixes/improvements for ARM SCMI, TEE, NXP i.MX SCU drivers" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits) soc: aspeed: fix Kconfig soc: add aspeed folder and misc drivers spi: zynqmp: Fix build break soc: imx: Add generic i.MX8 SoC driver MAINTAINERS: Update email for Qualcomm SoC maintainer memory: tegra: Fix a typos for "fdcdwr2" mc client Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+" memory: tegra: Replace readl-writel with mc_readl-mc_writel memory: tegra: Fix integer overflow on tick value calculation memory: tegra: Fix missed registers values latching ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30 optee: allow to work without static shared memory soc/tegra: pmc: Move powergate initialisation to probe soc/tegra: pmc: Remove reset sysfs entries on error soc/tegra: pmc: Fix reset sources and levels soc: amlogic: meson-gx-pwrc-vpu: Add support for G12A soc: amlogic: meson-gx-pwrc-vpu: Fix power on/off register bitmask fpga manager: Adding FPGA Manager support for Xilinx zynqmp dt-bindings: fpga: Add bindings for ZynqMP fpga driver firmware: xilinx: Add fpga API's ...	2019-05-16 09:19:14 -07:00
Stephen Boyd	62e59c4e69	clk: Remove io.h from clk-provider.h ... Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-15 13:21:37 -07:00
Stephen Boyd	c1157f60d7	Merge branch 'clk-parent-rewrite-1' into clk-next ... - Rewrite how clk parents can be specified to be DT/clkdev based instead of just string based * clk-parent-rewrite-1: clk: Cache core in clk_fetch_parent_index() without names clk: fixed-factor: Initialize clk_init_data on stack clk: fixed-factor: Let clk framework find parent clk: Allow parents to be specified via clkspec index clk: Look for parents with clkdev based clk_lookups clk: Allow parents to be specified without string names clk: Add of_clk_hw_register() API for early clk drivers driver core: Let dev_of_node() accept a NULL dev clk: Prepare for clk registration API that uses DT nodes clkdev: Move clk creation outside of 'clocks_mutex'	2019-05-07 11:46:13 -07:00
Stephen Boyd	0caf000817	Merge branch 'clk-ti' into clk-next ... * clk-ti: clk: Remove CLK_IS_BASIC clk flag clk: ti: dra7: disable the RNG and TIMER12 clkctrl clocks on HS devices clk: ti: dra7x: prevent non-existing clkctrl clocks from registering ARM: omap2+: hwmod: drop CLK_IS_BASIC flag usage clk: ti: export the omap2_clk_is_hw_omap call	2019-05-07 11:46:02 -07:00
Stephen Boyd	ff060019f4	Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next ... - Support for STM32F769 - Rework AT91 sckc DT bindings - Fix slow RC oscillator issue on sama5d3 - AT91 sam9x60 PMC support - SiFive FU540 PRCI and PLL support * clk-stm32f4: clk: stm32mp1: Add ddrperfm clock clk: stm32: Introduce clocks of STM32F769 board * clk-tegra: clk: tegra: divider: Mark Memory Controller clock as read-only clk: tegra: emc: Replace BUG() with WARN_ONCE() clk: tegra: emc: Fix EMC max-rate clamping clk: tegra: emc: Support multiple RAM codes clk: tegra: emc: Don't enable EMC clock manually clk: tegra124: Remove lock-enable bit from PLLM clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider clk: tegra: Don't enable already enabled PLLs * clk-at91: clk: at91: Mark struct clk_range as const clk: at91: add sam9x60 pmc driver dt-bindings: clk: at91: add bindings for SAM9X60 pmc clk: at91: add sam9x60 PLL driver clk: at91: master: Add sam9x60 support clk: at91: usb: Add sam9x60 support clk: at91: allow configuring generated PCR layout clk: at91: allow configuring peripheral PCR layout clk: at91: sckc: handle different RC startup time clk: at91: modernize sckc binding dt-bindings: clock: at91: new sckc bindings * clk-sifive-fu540: clk: sifive: add a driver for the SiFive FU540 PRCI IP block clk: analogbits: add Wide-Range PLL library dt-bindings: clk: add documentation for the SiFive PRCI driver * clk-spdx: clk: sunxi-ng: Use the correct style for SPDX License Identifier clk: sprd: Use the correct style for SPDX License Identifier clk: renesas: Use the correct style for SPDX License Identifier clk: qcom: Use the correct style for SPDX License Identifier clk: davinci: Use the correct style for SPDX License Identifier clk: actions: Use the correct style for SPDX License Identifier	2019-05-07 11:45:29 -07:00
Stephen Boyd	5816b74581	Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' and 'clk-qoriq' into clk-next ... - Mark UFS clk as critical on Hi-Silicon hi3660 SoCs - Support for Cirrus Logic Lochnagar clks * clk-hisi: clk: hi3660: Mark clk_gate_ufs_subsys as critical * clk-lochnagar: clk: lochnagar: Add support for the Cirrus Logic Lochnagar clk: lochnagar: Add initial binding documentation * clk-allwinner: clk: sunxi-ng: sun5i: Export the MBUS clock clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate clk: sunxi-ng: h6: Preset hdmi-cec clock parent clk: sunxi: Add Kconfig options clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset clk: sunxi-ng: Allow DE clock to set parent rate * clk-rockchip: clk: rockchip: undo several noc and special clocks as critical on rk3288 clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288 clk: rockchip: Limit use of USB PHY clock to USB on rk3288 clk: rockchip: Fix video codec clocks on rk3288 clk: rockchip: Make rkpwm a critical clock on rk3288 clk: rockchip: fix wrong clock definitions for rk3328 * clk-qoriq: clk: qoriq: increase array size of cmux_to_group dt-bindings: qoriq-clock: Add ls1028a chip compatible string clk: qoriq: Add ls1028a clock configuration clk: qoriq: add more PLL divider clocks support dt-bindings: qoriq-clock: add more PLL divider clocks support	2019-05-07 11:45:13 -07:00
Stephen Boyd	7e9c62bdb4	Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-zynq' into clk-next ... - Various static analysis fixes/finds - Video Engine (ECLK) support on Aspeed SoCs - Xilinx ZynqMP Versal platform support - Convert Xilinx ZynqMP driver to be struct oriented * clk-sa: clk: mvebu: fix spelling mistake "gatable" -> "gateable" clk: ux500: add range to usleep_range clk: tegra: Make tegra_clk_super_mux_ops static clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5 * clk-aspeed: clk: Aspeed: Setup video engine clocking * clk-samsung: clk: samsung: exynos5410: Add gate clock for ADC clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410 clk: samsung: dt-bindings: Put CLK_UART3 in order * clk-ingenic: clk: ingenic: jz4725b: Add UDC PHY clock dt-bindings: clock: jz4725b-cgu: Add UDC PHY clock * clk-zynq: clk: zynqmp: use structs for clk query responses clk: zynqmp: fix check for fractional clock clk: zynqmp: do not export zynqmp_clk_register_* functions clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents drivers: clk: Update clock driver to handle clock attribute drivers: clk: zynqmp: Allow zero divisor value	2019-05-07 11:44:56 -07:00
Stephen Boyd	f6111b9d79	Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be' into clk-next ... - Remove clk_readl() and introduce BE versions of basic clk types * clk-doc: clk: Drop duplicate clk_register() documentation clk: Document and simplify clk_core_get_rate_nolock() clk: Remove 'flags' member of struct clk_fixed_rate clk: nxp: Drop 'flags' on fixed_rate clk macro clk: Document __clk_mux_determine_rate() clk: Document CLK_MUX_READ_ONLY mux flag clk: Document deprecated things clk: Collapse gpio clk kerneldoc * clk-more-critical: clk: highbank: Convert to CLK_IS_CRITICAL * clk-meson: (21 commits) clk: meson: axg-audio: add g12a support clk: meson: axg-audio: don't register inputs in the onecell data clk: meson: axg_audio: replace prefix axg by aud dt-bindings: clk: axg-audio: add g12a support clk: meson: meson8b: add the video decoder clock trees clk: meson: meson8b: add the VPU clock trees clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2 clk: meson: meson8b: use a separate clock table for Meson8m2 dt-bindings: clock: meson8b: export the video decoder clocks clk: meson-g12a: add video decoder clocks dt-bindings: clock: meson8b: export the VPU clock clk: meson-g12a: add PCIE PLL clocks dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL dt-bindings: clock: meson8b: drop the "ABP" clock definition clk: meson: g12a: add cpu clocks dt-bindings: clk: g12a-clkc: add VDEC clock IDs dt-bindings: clock: axg-audio: unexpose controller inputs dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id ... * clk-basic-be: clk: core: replace clk_{readl,writel} with {readl,writel} clk: core: remove powerpc special handling powerpc/512x: mark clocks as big endian clk: mux: add explicit big endian support clk: multiplier: add explicit big endian support clk: gate: add explicit big endian support clk: fractional-divider: add explicit big endian support clk: divider: add explicit big endian support	2019-05-07 11:44:42 -07:00
Stephen Boyd	2ed3b9103a	Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-imx' into clk-next ... - Qualcomm QCS404 CDSP clk support - Qualcomm QCS404 Turing clk support - Mediatek MT8183 clock support - Mediatek MT8516 clock support - Milbeaut M10V clk controller support * clk-renesas: clk: renesas: rcar-gen3: Remove unused variable clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value clk: renesas: r8a77980: Fix RPC-IF module clock's parent clk: renesas: rcar-gen3: Rename DRIF clocks clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC clk: renesas: rcar-gen3: Correct parent clock of HS-USB clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI clk: renesas: r8a774c0: Add Z2 clock clk: renesas: r8a77990: Add Z2 clock clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents math64: New DIV64_U64_ROUND_CLOSEST helper clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor clk: renesas: r9a06g032: Add missing PCI USB clock clk: renesas: r7s9210: Always use readl() clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() * clk-qcom: clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998 clk: qcom: Add QCS404 TuringCC clk: qcom: branch: Add AON clock ops dt-bindings: clock: Introduce Qualcomm Turing Clock controller clk: qcom: gcc-qcs404: Add CDSP related clocks and resets * clk-mtk: clk: mediatek: add clock driver for MT8516 dt-bindings: mediatek: apmixedsys: add support for MT8516 dt-bindings: mediatek: infracfg: add support for MT8516 dt-bindings: mediatek: topckgen: add support for MT8516 clk: mediatek: Allow changing PLL rate when it is off clk: mediatek: Add MT8183 clock support clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data clk: mediatek: Add dt-bindings for MT8183 clocks dt-bindings: ARM: Mediatek: Document bindings for MT8183 clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data clk: mediatek: Add new clkmux register API clk: mediatek: Disable tuner_en before change PLL rate * clk-milbeaut: clock: milbeaut: Add Milbeaut M10V clock controller dt-bindings: clock: milbeaut: add Milbeaut clock description * clk-imx: clk: imx: correct pfdv2 gate_bit/vld_bit operations clk: imx: clk-pllv3: mark expected switch fall-throughs clk: imx8mq: Add dsi_ipg_div clk: imx: pllv4: add fractional-N pll support clk: imx: keep uart clock on during system boot clk: imx: correct i.MX7D AV PLL num/denom offset clk: imx6sll: Fix mispelling uart4_serial as serail clk: imx: pll14xx: drop unused variable clk: imx: rename clk-imx51-imx53.c to clk-imx5.c clk: imx5: Fix i.MX50 ESDHC clock registers clk: imx5: Fix i.MX50 mainbus clock registers clk: imx: Remove unused imx_get_clk_hw_fixed dt-bindings: clock: imx7ulp: remove SNVS clock clk: imx7ulp: remove snvs clock	2019-05-07 11:44:21 -07:00
Stephen Boyd	1a079560b1	clk: Cache core in clk_fetch_parent_index() without names ... If a clk has specified parents via clk_hw pointers it won't specify the globally unique names for the parents. Without the unique names, we can't fallback to comparing them against the name of the 'parent' pointer here. Therefore, do a pointer comparison against the clk_hw pointers too and cache the clk_core structure if they match. This fixes parent lookup code for clks that only specify clk_hw pointers and nothing else, like muxes that are purely inside a clk controller. Similarly, if the parent pointer isn't cached after trying to match clk_core or clk_hw pointers, lookup the pointer from DT or via clkdev lookups instead of relying purely on the globally unique clk name match. This should allow us to move away from having to specify global names for clk parents entirely. While we're in the area, add some comments so it's clearer what's going on. The if statements don't lend themselves to much clarity in their raw form. Fixes: fc0c209c14 ("clk: Allow parents to be specified without string names") Reported-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-03 10:38:01 -07:00
Anson Huang	a5a627c676	clk: imx: correct pfdv2 gate_bit/vld_bit operations ... The operations of pfdv2 gate_bit/valid_bit are incorrect, they are defined as u8 for bit offset, but gate_bit is actually assigned as mask which could be 32 bit long and it causes overflow, and vld_bit is assigned as bit offset based on incorrect gate_bit value, it causes incorrect pfd clock gate status in clock tree, this patch fixes the issue by assigning them as correct bit offset. Fixes: 9fcb6be3b6 ("clk: imx: add pfdv2 support") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-03 09:31:54 -07:00
Paul Walmsley	30b8e27e3b	clk: sifive: add a driver for the SiFive FU540 PRCI IP block ... Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com>: 999529edf5 Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. This version includes several changes requested by Stephen Boyd <sboyd@kernel.org>. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Wesley W. Terpstra <wesley@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Megan Wachs <megan@sifive.com> Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-clk@vger.kernel.org [sboyd@kernel.org: Fix some const and ARRAY_SIZE() issues, make makefile only descend if CLK_SIFIVE=y] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-03 09:20:56 -07:00
Paul Walmsley	7b9487a9a5	clk: analogbits: add Wide-Range PLL library ... Add common library code for the Analog Bits Wide-Range PLL (WRPLL) IP block, as implemented in TSMC CLN28HPC. There is no bus interface or register target associated with this PLL. This library is intended to be used by drivers for IP blocks that expose registers connected to the PLL configuration and status signals. Based on code originally written by Wesley Terpstra <wesley@sifive.com>: 999529edf5 This version incorporates several changes requested by Stephen Boyd <sboyd@kernel.org>. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Wesley Terpstra <wesley@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Megan Wachs <megan@sifive.com> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org [sboyd@kernel.org: Fix some const issues] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-03 09:20:48 -07:00
Gustavo A. R. Silva	53dd5c709b	clk: imx: clk-pllv3: mark expected switch fall-throughs ... In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/clk/imx/clk-pllv3.c: In function ‘imx_clk_pllv3’: drivers/clk/imx/clk-pllv3.c:446:18: warning: this statement may fall through [-Wimplicit-fallthrough=] pll->div_shift = 1; ~~~~~~~~~~~~~~~^~~ drivers/clk/imx/clk-pllv3.c:447:2: note: here case IMX_PLLV3_USB: ^~~~ drivers/clk/imx/clk-pllv3.c:453:21: warning: this statement may fall through [-Wimplicit-fallthrough=] pll->denom_offset = PLL_IMX7_DENOM_OFFSET; ^ drivers/clk/imx/clk-pllv3.c:454:2: note: here case IMX_PLLV3_AV: ^~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enable -Wimplicit-fallthrough. Fixes: b4a4cb5a04 ("clk: imx: correct i.MX7D AV PLL num/denom offset") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-03 09:02:13 -07:00
Guido Günther	4d13c67adf	clk: imx8mq: Add dsi_ipg_div ... It's defined in imx8mq-clock.h but wasn't assigned yet. It's used as clk_tx_esc in the nwl dsi host controller (i.MX8MQ RM, Rev. 0, 01/2018 Sect. 13.5.3.7.4). Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-02 13:26:38 -07:00
Anson Huang	a048fe996b	clk: imx: pllv4: add fractional-N pll support ... The pllv4 supports fractional-N function, the formula is: PLL output freq = input * (mult + num/denom), This patch adds fractional-N function support, including clock round rate, calculate rate and set rate, with this patch, the clock rate of APLL in clock tree is more accurate than before: Without fraction: apll_pre_sel 1 1 1 24000000 0 0 50000 apll_pre_div 1 1 2 24000000 0 0 50000 apll 1 1 2 528000000 0 0 50000 apll_pfd3 0 0 0 792000000 0 0 50000 apll_pfd2 0 0 0 339428571 0 0 50000 apll_pfd1 0 0 0 352000000 0 0 50000 usdhc0 0 0 0 352000000 0 0 50000 apll_pfd0 1 1 1 352000000 0 0 50000 With fraction: apll_pre_sel 1 1 1 24000000 0 0 50000 apll_pre_div 1 1 2 24000000 0 0 50000 apll 1 1 2 529200000 0 0 50000 apll_pfd3 0 0 0 793800000 0 0 50000 apll_pfd2 0 0 0 340200000 0 0 50000 apll_pfd1 0 0 0 352800000 0 0 50000 usdhc0 0 0 0 352800000 0 0 50000 apll_pfd0 1 1 1 352800000 0 0 50000 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>	2019-05-01 14:01:45 -07:00
Nishad Kamdar	d65530ca86	clk: sunxi-ng: Use the correct style for SPDX License Identifier ... This patch corrects the SPDX License Identifier style in header files related to Clock Drivers for Allwinner SoCs. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used) Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46 Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-01 13:01:26 -07:00
Nishad Kamdar	7a12f838e4	clk: sprd: Use the correct style for SPDX License Identifier ... This patch corrects the SPDX License Identifier style in header files related to Clock Drivers for Spreadtrum SoCs. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used) Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46 Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-01 13:01:23 -07:00
Nishad Kamdar	596c5ea465	clk: renesas: Use the correct style for SPDX License Identifier ... This patch corrects the SPDX License Identifier style in header files related to Clock Drivers for Renesas Socs. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used) Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46 Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-01 13:01:18 -07:00
Nishad Kamdar	ddc9e569f1	clk: qcom: Use the correct style for SPDX License Identifier ... This patch corrects the SPDX License Identifier style in clk-regmap-mux-div.h. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used) Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46 Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-01 13:01:13 -07:00
Nishad Kamdar	41d591750e	clk: davinci: Use the correct style for SPDX License Identifier ... This patch corrects the SPDX License Identifier style in header files related to Clock Drivers for Davinci Socs. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used) Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46 Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-01 13:01:11 -07:00
Nishad Kamdar	ddd3e8b976	clk: actions: Use the correct style for SPDX License Identifier ... This patch corrects the SPDX License Identifier style in header files related to Clock Drivers for Actions Semi Socs. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used) Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46 Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-05-01 13:01:07 -07:00
Jacky Bai	8cd117e712	clk: imx: keep uart clock on during system boot ... Keep uart clocks enabled when earlyprintk or earlycon is active. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-29 16:02:01 -07:00
Anson Huang	b4a4cb5a04	clk: imx: correct i.MX7D AV PLL num/denom offset ... According reference manual, i.MX7D's audio/video PLL's num/denom register offset are 0x20/0x30, they are different from i.MX6's audio/video PLL, correct it by introducing new offset variables for audio/video PLL and using runtime assignment based on PLL type. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-29 16:01:50 -07:00
Gabriel Fernandez	b06df56bad	clk: stm32mp1: Add ddrperfm clock ... Add ddrperfm clock for DDR Performance Monitor driver Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Gerald Baeza <gerald.baeza@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-29 11:13:23 -07:00
Stephen Boyd	90b6c5c73c	clk: Remove CLK_IS_BASIC clk flag ... This flag was historically used to indicate that a clk is a "basic" type of clk like a mux, divider, gate, etc. This never turned out to be very useful though because it was hard to cleanly split "basic" clks from other clks in a system. This one flag was a way for type introspection and it just didn't scale. If anything, it was used by the TI clk driver to indicate that a clk_hw wasn't contained in the SoC specific clk structure. We can get rid of this define now that TI is finding those clks a different way. Cc: Tero Kristo <t-kristo@ti.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: <linux-mips@vger.kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Kevin Hilman <khilman@baylibre.com> Cc: <linux-pwm@vger.kernel.org> Cc: <linux-amlogic@lists.infradead.org> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-26 10:40:49 -07:00
Sugaya Taichi	6a6ba5b55a	clock: milbeaut: Add Milbeaut M10V clock controller ... The M10V of the Milbeaut SoCs has an on-chip controller that derive mostly clocks from a single external clock, using PLLs, dividers, multiplexers and gates. Since the PLLs have already been started and will not stop / restart, they are fixed factor. The gates will be added in later patch (all of the gates are off state now). Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 16:43:37 -07:00
Leonard Crestez	6ff46d77ca	clk: imx6sll: Fix mispelling uart4_serial as serail ... This looks like a copy-paste error. This string is not referenced anywhere so it's safe to rename it. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 14:46:01 -07:00
Peng Fan	a3c9e13ff0	clk: imx: pll14xx: drop unused variable ... It does not make sense to only get value from pll->base and assign to a local variable when recalc_rate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 14:42:02 -07:00
Fabien Parent	db077febb7	clk: mediatek: add clock driver for MT8516 ... Add the clock driver for the MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 14:36:58 -07:00
Stephen Boyd	7b4c162e03	clk: at91: Mark struct clk_range as const ... It's just some static data that doesn't get changed after being used. Mark it const everywhere. Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 14:16:26 -07:00
Alexandre Belloni	01e2113de9	clk: at91: add sam9x60 pmc driver ... Add a driver for the PMC clocks of the sam9c60. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [sboyd@kernel.org: Staticize spinlock] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 14:15:53 -07:00
Dmitry Osipenko	e71f4d3858	clk: tegra: divider: Mark Memory Controller clock as read-only ... The Memory Controller (MC) clock rate can't be simply changed and nothing in kernel need to change the rate, hence let's make the clock read-only. This id also needed for the EMC driver because timing configuration may require the MC clock diver to be disabled, that is handled by the EMC clock / EMC driver integration and CLK framework shall not touch the MC divider configuration on the EMC clock rate change. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 13:54:23 -07:00
Dmitry Osipenko	f4037654a8	clk: tegra: emc: Replace BUG() with WARN_ONCE() ... There is no justification for the BUG() in this code. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 13:54:22 -07:00
Dmitry Osipenko	913c3072eb	clk: tegra: emc: Fix EMC max-rate clamping ... When a clk user requests rate that is higher than the maximum possible, the rate shall be clamped to the maximum and not to the current value. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 13:54:20 -07:00
Dmitry Osipenko	888ca40e28	clk: tegra: emc: Support multiple RAM codes ... The timings parser doesn't append timings, but instead it parses only the first timing and hence doesn't store all of the timings when device-tree has timings for multiple RAM codes. In a result EMC scaling doesn't work if timings are missing. Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 13:54:20 -07:00
Dmitry Osipenko	924ee3d551	clk: tegra: emc: Don't enable EMC clock manually ... The EMC clock marked as critical, hence it is already enabled at the registration time. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 13:54:19 -07:00
Alexandre Belloni	a436c2a447	clk: at91: add sam9x60 PLL driver ... The PLLs on the sam9x60 (PLLA and USB PLL) use a different register set and programming model than the previous SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 12:34:06 -07:00
Alexandre Belloni	e5be537064	clk: at91: master: Add sam9x60 support ... The sam9x60 cpu clock is located at a different offset but is otherwise similar to the master clock. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 12:34:05 -07:00
Alexandre Belloni	2423eeaead	clk: at91: usb: Add sam9x60 support ... The sam9x60 USB clock supports four different parents, ensure they can be selected. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 12:34:04 -07:00
Alexandre Belloni	e4cfb823bd	clk: at91: allow configuring generated PCR layout ... The PCR register layout for GCLKCSS is changing for the future SoCs, allow configuring it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 12:34:03 -07:00
Alexandre Belloni	cb4f4949b1	clk: at91: allow configuring peripheral PCR layout ... The PCR register actually changed layout for each SoC. By chance, this didn't have impact on sama5d[2-4] support but since sama5d3, PID is seven bits wide and sama5d4 and sama5d2 don't have DIV. For the DT backward compatibility, keep the layout as is. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 12:34:03 -07:00
Gabriel Fernandez	936289f047	clk: stm32: Introduce clocks of STM32F769 board ... STM32F769 clocks are derived from STM32746 clocks. main differences are: - new source clock for SAI1 and SAI2 (HSI or HSE) - Add DFSDM & DSI clocks Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 11:46:36 -07:00
Alexandre Belloni	5c16ffa795	clk: at91: sckc: handle different RC startup time ... The sama5d3 slow RC oscillator as a different startup time than all the previous SoCs. Handle that using its own compatible. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 11:43:15 -07:00
Alexandre Belloni	45b5ec8498	clk: at91: modernize sckc binding ... Remove the need for child nodes in the sckc binding and register the whole sckc tree (3 clocks in total) from the sckc node. DT backward compatibility is kept by looking for properties in child nodes when they are not present in the sckc node. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 11:42:10 -07:00
Yogesh Gaur	42614b5bd9	clk: qoriq: increase array size of cmux_to_group ... Increase size of cmux_to_group array, to accomdate entry of -1 termination. Added -1, terminated, entry for 4080_cmux_grpX. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 11:41:18 -07:00
Yuantian Tang	95089f6a9e	clk: qoriq: Add ls1028a clock configuration ... Enable clock driver by adding clock configuration for ls1028a chip. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 11:23:10 -07:00
Yuantian Tang	cc61ab9ba2	clk: qoriq: add more PLL divider clocks support ... More PLL divider clocks are needed by clock consumer IP. So enlarge the PLL divider array to accommodate more divider clocks. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2019-04-25 11:22:46 -07:00