3 Commits

Author	SHA1	Message	Date
Laurent Pinchart	c896c132b0	iommu: io-pgtable-arm: add non-secure quirk ... The quirk causes the Non-Secure bit to be set in all page table entries. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Will Deacon <will.deacon@arm.com>	2015-01-19 14:46:45 +00:00
Will Deacon	e1d3c0fd70	iommu: add ARM LPAE page table allocator ... A number of IOMMUs found in ARM SoCs can walk architecture-compatible page tables. This patch adds a generic allocator for Stage-1 and Stage-2 v7/v8 long-descriptor page tables. 4k, 16k and 64k pages are supported, with up to 4-levels of walk to cover a 48-bit address space. Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Will Deacon <will.deacon@arm.com>	2015-01-19 14:46:44 +00:00
Will Deacon	fdb1d7be7c	iommu: introduce generic page table allocation framework ... This patch introduces a generic framework for allocating page tables for an IOMMU. There are a number of reasons we want to do this: - It avoids duplication of complex table management code in IOMMU drivers that use the same page table format - It removes any coupling with the CPU table format (and even the architecture!) - It defines an API for IOMMU TLB maintenance Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Will Deacon <will.deacon@arm.com>	2015-01-19 14:46:43 +00:00