In some situations, the pen_release store in platform_secondary_init()
may stay forever in the write buffer while the CPU is waiting on the
boot_lock to be released in boot_secondary(). The primary CPU could
never see the pen_release update without the barriers.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch enables the L220 on the RealView/EB MPCore platform.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The kernel originally supported revB only. This patch enables revC by
default and adds a config option for building the kernel for the revB
platform. Since the SCU base address was hard-coded in the proc-v6.S
file (and only valid for RealView/EB revB), this patch also adds a
more generic support for defining the SCU information.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
MPCore platform
This patch adds the registration of the secondary GIC on the
baseboard, together with the IRQ chaining setup.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The current implementation only assumes one GIC to be present in the
system. However, there are platforms with more than one cascaded interrupt
controllers (RealView/EB MPCore for example).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds the support for the L210/L220 (outer) cache
controller. The cache range operations are done by index/way since L2
cache controller only accepts physical addresses.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Other platforms other than SMP may have an outer cache. For these, we
also need to mark the page table walks outer cacheable. Since marking
the walks always outer cacheable apparantly has no side effects, we
might as well always mark them so.
However, we continue to only mark PTWs shared if we have SMP enabled.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
In consistent_sync(), start + size can end up pointing one byte
beyond the end of the direct RAM mapping. We shouldn't BUG() when
this happens.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The DMA cache handling functions take virtual addresses, but in the
form of unsigned long arguments. This leads to a little confusion
about what exactly they take. So, convert them to take const void *
instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The outer cache can be L2 as on RealView/EB MPCore platform or even L3
or further on ARMv7 cores. This patch adds the generic support for
flushing the outer cache in the DMA operations.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Memory allocated by the coherent memory allocators will be marked
uncacheable, which means it's pointless calling consistent_sync()
to perform cache maintainence on this memory; it's just a waste of
CPU cycles.
Moreover, with the (subsequent) merge of outer cache support, it
actually breaks things to call consistent_sync() on anything but
direct-mapped memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The architecture specification states that TLB operations are
guaranteed to be complete only after the execution of a DSB (Data
Synchronisation Barrier, former Data Write Barrier or Drain Write
Buffer). The branch target cache invalidation is also needed. The ISB
(Instruction Synchronisation Barrier, formerly Prefetch Flush) is
needed unless there will be a return from exception before the
corresponding mapping is used (i.e. user mappings).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
On newer architectures (ARMv6, ARMv7), the depth of the prefetch and
branch prediction is implementation defined and there is a small risk
of wrong ASID tagging when changing TTBR0 before setting the new
context id. The recommended solution is to set a reserved ASID during
TTBR changing. This patch reserves ASID 0.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
bad_mode() currently prints the mode which caused the exception, and
then causes an oops dump to be printed which again displays this
information (since the CPSR in the struct pt_regs is correct.) This
leads to processor_modes[] being shared between traps.c and process.c
with a local declaration of it.
We can clean this up by moving processor_modes[] to process.c and
removing the duplication, resulting in processor_modes[] becoming
static.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds the platform resources required to support the
ixp4xx-pata-cf libata driver on Avila Gateworks boards.
Signed-off-by: Alessandro Zummo <a.zummo@towertech.it>
Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk>
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds support for the Gateworks Avila Network Platform in
a separate set of setup files to the IXDP425. This is necessary now
that a driver for the Avila CF card slot is available. It also adds
support for a minor variant on the Avila board known as the Loft,
which has a different number of maximum PCI devices.
Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk>
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch removes references to the Gateworks Avila Network
Platform in the ixdp425 setup code. Avila setup should occur
separately now that a CF ATA device driver is available.
Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk>
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add the glue for ARM11 SMP oprofile support, which also supports the
performance monitor in the coherency unit.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add oprofile glue for ARM11 (ARMv6) oprofile support. This
connects the ARM11 core profiling support to the oprofile code
for uniprocessor configurations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add basic support for the ARM11 profiling hardware. This is shared
between the ARM11 UP and ARM11 SMP oprofile support code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The S3C2412 DMA selection code has the
arguments to writel() the wrong way around.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The current lazy saving of the VFP registers is no longer possible
with thread migration on SMP. This patch implements a per-CPU
vfp-state pointer and the saving of the VFP registers at every context
switch. The registers restoring is still performed in a lazy way.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Supersections do not have a field for the domain and it is always
0. This patch prevents the creation of supersections during ioremap
when DOMAIN_IO is not zero (i.e. !defined(CONFIG_IO_36)).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patchs allows the offset to the first page of
physical memory to be on any 2MB boundary
whereas the previous code could only handle psysical
offset to any 16MB boundary (0xNN000000) or any 1MB
boundary below 0x01000000 (e.g. 0x00N00000). The
problem is a consequence of the orr one-byte syntax,
so we fix this and we can place the first bank of
memory at 0x28e00000. I have also included an explicit
check that disallow compilation when PHYS_OFFSET is
not on a 2MiB boundary. head.S would be the proper place
to have this at since this is the first file that
attempts to use PHYS_OFFSET during compile.
Signed-off-by: Linus Walleij <triad@df.lth.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
cosmetic fix so iop333 is not reported as ixp46x
iop333 cpuid = 0x69054210
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show_mem() was assuming incorrectly that the mem_map for any
node started at PFN 0. This is obviously wrong; fix it to
take account of node_start_pfn.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The s3c2410_gpio_getcfg() currently returns
a value which is dependant on the GPIO no
passed in. Now we have more generic constants
it is sensible to use those as return codes
so that any function dealing with >1 GPIO
does not need to do it's own number processing.
Since this function is only currently used in
pm.c, it is easy to fixup (and correct pm.c
to use the generic constants)
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
GPIO bank A can only be output or a special
function, and the regs-gpio.h header has
mistakenly got this as input or output.
The mistake is carried on into the gpio.c
s3c2410_gpio_cfgpin() call which will set the
wrong value if S3C2410_GPIO_OUTPUT is passed.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The transition latency has to be defined and reasonably
small to allow on-demand and conservative governors.
The value has been defined according to manual.
The imx_set_target() protected against seen out of range
requests now.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cleanup of at91 platform level gpio wake and suspend/resume logic.
The GPIO core now delegates wakeups to the parent AIC by refcounting,
and delegates clock management to the clock API. This makes these
system modules more independent of each other, which is cleaner and will
also help with the AT91SAM9263 (where some GPIO controllers share the
same irq and clock).
Original patch by David Brownell.
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch implements CPU and peripheral reset on AT91SAM9260 and
AT91SAM9261.
Original patch from Wojtek Kaniewski.
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
A couple of whitespace cleanups, mainly in the AT91 header files.
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the legacy CONFIG_DEBUG_WAITQ from the SAM9260-EK and SAM9261-EK
default configuration files.
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Current sched_clock() implementations on ARM cause unbootable kernels
with PRINTK_TIME support enabled. To avoid this, provide a basic
printk_clock() implementation which avoids sched_clock() being called
before the page tables have been set up.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
fuse does not work on ARM due to cache incoherency issues - fuse wants
to use get_user_pages() to copy data from the current process into
kernel space. However, since this accesses userspace via the kernel
mapping, the kernel mapping can be out of date wrt data written to
userspace.
This can lead to unpredictable behaviour (in the case of fuse) or data
corruption for direct-IO.
This resolves debian bug #402876
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
If the kernel attempts to execute a CP1 or CP2 instruction and it
aborts, and a FP emulator is not loaded, we try to return as if to
a user context, instead of the proper kernel context. Since the
fault came from kernel mode, we must use the kernel return paths.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Include <asm/io.h> to fix the warning:
arch/arm/kernel/traps.c:647:6: warning: symbol '__readwrite_bug' was not declared. Should it be static?
Include <linux/mc146818rtc.h> to fix the warning:
arch/arm/kernel/time.c:42:1: warning: symbol 'rtc_lock' was not declared. Should it be static?
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When we install the handlers for context switching, we must enable
VFP on all CPU cores, otherwise undefined (and random) effects
occur.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix apollon board compiler error
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Fix GPMC compiler errors on OMAP2
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
If PG_dcache_dirty is set for a page, we need to flush the source page
before performing any copypage operation using a different virtual address.
This fixes the copypage implementations for XScale, StrongARM and ARMv6.
This patch fixes segmentation faults seen in the dynamic linker under
the usage patterns in glibc 2.4/2.5.
Signed-off-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since iop13xx defines the PCI I/O spaces with physical resource addresses
the __io macro needs to perform the physical to virtual conversion. I
incorrectly assumed that this would be handled by ioremap, but drivers
(like e1000) directly dereference the address returned from __io.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The commit 505788cccb in linus kernel tree
introduced some printks (for debugging ?) which are flooding the logs on
my h1940. This patch replace them with pr_debug calls.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Both CONFIG_MACH_OSIRIS and CONFIG_MACH_ANUBIS
should select CONFIG_PM_SIMTEC.
This patch moves the selection of CONFIG_PM_SIMTEC
to the machines that require it, as currently done
with other machines in the S3C2410 architecture.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
