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clk: renesas: Updates for v4.8 (take two)
- Add support for R-Car V2H, - Add FDP1, DRIF, and thermal clocks on R-Car H3, - Correct a wrong parent clock. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXa+vcAAoJEEgEtLw/Ve77ZXYP/2Sdr+g7sfIOsjgS8FIEaEnM l7zvU73l39kpnPxIG5deCAcYd9lyIfTSwlCiK4/xbWFyteEhnltt0LfYterLUump zu1JLdpJjdd476M57QiwiaBxNvkQ2DCLab4oc3N0fMK3/Yc7HzrfS/uQKWvBGDHR xYhWEyE2YrmPmphI1KAiAV1r55lhHJ0+6EBAv3J2+zloNhmS/c7jdE2jKZkTuSle 6sR1qzbcHFd1vSWZmzHuFOwYni2LmYUptzKUEYGuWKFeLsO6kIPVAs3Aa02jpmDz yl7N8cGYD+5JVIv/xnLOa3Gz2iXNhSjWMPGgI0o/PHMZxAg4oUiHGZXgx9rC9sXg AryADX+I5Bw0srs4sUQiBgLxQoW6Ti4U+i3wiYDAy/z9DnKTUiVnj1FHllkXeRKD SsEfgPLQBdZ9HxBE2zgI75R32uO69J3e0F/8AoWe2ga+wagrUVVbGR9KTJQp6/vB tgPPGaJGCevIBFivro/BWJEyXQmqgHTK8PiBvzcC0pztnWLVDNwR7HRyqhVDMPC5 RO4Zi4vAydj+SuLyEVcTfRnL9S4M7101QlrGGF/JqQVOv5zTRDdC9Y4aaVXhFdcW 5aYtFEPke8rIChMm8ps6FHIgG0i09hKuTx1B1W+1HYY8HFCGuJY2LPKWJGcPqVkq LObPH/YM7oCfrIhoGSQo =sXDx -----END PGP SIGNATURE----- Merge tag 'clk-renesas-for-v4.8-tag2' into HEAD clk: renesas: Updates for v4.8 (take two) - Add support for R-Car V2H, - Add FDP1, DRIF, and thermal clocks on R-Car H3, - Correct a wrong parent clock.
This commit is contained in:
Simon Horman
commit
fffae950cf
@ -13,7 +13,8 @@ They provide the following functionalities:
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Required Properties:
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- compatible: Must be one of:
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- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC
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- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
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- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
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- reg: Base address and length of the memory resource used by the CPG/MSSR
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block
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@ -21,8 +22,8 @@ Required Properties:
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- clocks: References to external parent clocks, one entry for each entry in
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clock-names
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- clock-names: List of external parent clock names. Valid names are:
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- "extal" (r8a7795)
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- "extalr" (r8a7795)
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- "extal" (r8a7795, r8a7796)
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- "extalr" (r8a7795, r8a7796)
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- #clock-cells: Must be 2
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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@ -17,6 +17,7 @@ Required Properties:
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- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
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- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
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- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
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- "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks
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- "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
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- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
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- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
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@ -10,6 +10,7 @@ Required Properties:
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- compatible: Must be one of
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- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
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- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
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- "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
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- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
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- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
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and "renesas,rcar-gen2-cpg-clocks" as a fallback.
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@ -1,6 +1,7 @@
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config CLK_RENESAS_CPG_MSSR
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bool
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default y if ARCH_R8A7795
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default y if ARCH_R8A7796
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config CLK_RENESAS_CPG_MSTP
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bool
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@ -11,6 +12,7 @@ config CLK_RENESAS_CPG_MSTP
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default y if ARCH_R8A7779
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default y if ARCH_R8A7790
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default y if ARCH_R8A7791
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default y if ARCH_R8A7792
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default y if ARCH_R8A7793
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default y if ARCH_R8A7794
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default y if ARCH_SH73A0
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@ -6,9 +6,11 @@ obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
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obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7792) += clk-rcar-gen2.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o
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obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o rcar-gen3-cpg.o
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obj-$(CONFIG_ARCH_R8A7796) += r8a7796-cpg-mssr.o rcar-gen3-cpg.o
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obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-div6.o
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obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o
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@ -12,22 +12,14 @@
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/bug.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#define CPG_RCKCR 0x240
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#include "rcar-gen3-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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@ -58,20 +50,6 @@ enum clk_ids {
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MOD_CLK_BASE
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};
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enum r8a7795_clk_types {
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CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_GEN3_PLL0,
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CLK_TYPE_GEN3_PLL1,
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CLK_TYPE_GEN3_PLL2,
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CLK_TYPE_GEN3_PLL3,
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CLK_TYPE_GEN3_PLL4,
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CLK_TYPE_GEN3_SD,
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CLK_TYPE_GEN3_R,
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};
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#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
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static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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@ -129,6 +107,9 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
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};
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static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1),
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DEF_MOD("fdp1-1", 118, R8A7795_CLK_S2D1),
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DEF_MOD("fdp1-0", 119, R8A7795_CLK_S2D1),
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DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
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DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
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DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
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@ -157,11 +138,20 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
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DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
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DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4),
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DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
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DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
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DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
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DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
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DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
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DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
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DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
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DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
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DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
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DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
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DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
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DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
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DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
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DEF_MOD("thermal", 522, R8A7795_CLK_CP),
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DEF_MOD("pwm", 523, R8A7795_CLK_S3D4),
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DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1),
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DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1),
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@ -199,7 +189,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
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DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
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DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
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DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
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DEF_MOD("lvds", 727, R8A7795_CLK_S2D1),
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DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
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DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
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DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
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DEF_MOD("vin7", 804, R8A7795_CLK_S2D1),
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@ -262,225 +252,6 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
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MOD_CLK_ID(408), /* INTC-AP (GIC) */
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};
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/* -----------------------------------------------------------------------------
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* SDn Clock
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*
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*/
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#define CPG_SD_STP_HCK BIT(9)
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#define CPG_SD_STP_CK BIT(8)
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#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
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#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
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#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
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{ \
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.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
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((stp_ck) ? CPG_SD_STP_CK : 0) | \
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((sd_srcfc) << 2) | \
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((sd_fc) << 0), \
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.div = (sd_div), \
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}
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struct sd_div_table {
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u32 val;
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unsigned int div;
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};
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struct sd_clock {
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struct clk_hw hw;
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void __iomem *reg;
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const struct sd_div_table *div_table;
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unsigned int div_num;
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unsigned int div_min;
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unsigned int div_max;
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};
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/* SDn divider
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* sd_srcfc sd_fc div
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* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
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*-------------------------------------------------------------------
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* 0 0 0 (1) 1 (4) 4
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* 0 0 1 (2) 1 (4) 8
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* 1 0 2 (4) 1 (4) 16
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* 1 0 3 (8) 1 (4) 32
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* 1 0 4 (16) 1 (4) 64
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* 0 0 0 (1) 0 (2) 2
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* 0 0 1 (2) 0 (2) 4
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* 1 0 2 (4) 0 (2) 8
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* 1 0 3 (8) 0 (2) 16
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* 1 0 4 (16) 0 (2) 32
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*/
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static const struct sd_div_table cpg_sd_div_table[] = {
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/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
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CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
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CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
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CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
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CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
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CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
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CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
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CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
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CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
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CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
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CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
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};
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#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
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static int cpg_sd_clock_enable(struct clk_hw *hw)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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u32 val, sd_fc;
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unsigned int i;
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val = clk_readl(clock->reg);
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sd_fc = val & CPG_SD_FC_MASK;
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for (i = 0; i < clock->div_num; i++)
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if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
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break;
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if (i >= clock->div_num)
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return -EINVAL;
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val &= ~(CPG_SD_STP_MASK);
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val |= clock->div_table[i].val & CPG_SD_STP_MASK;
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clk_writel(val, clock->reg);
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return 0;
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}
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static void cpg_sd_clock_disable(struct clk_hw *hw)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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clk_writel(clk_readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
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}
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static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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return !(clk_readl(clock->reg) & CPG_SD_STP_MASK);
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}
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static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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unsigned long rate = parent_rate;
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u32 val, sd_fc;
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unsigned int i;
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val = clk_readl(clock->reg);
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sd_fc = val & CPG_SD_FC_MASK;
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for (i = 0; i < clock->div_num; i++)
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if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
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break;
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if (i >= clock->div_num)
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return -EINVAL;
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return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
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}
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static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
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unsigned long rate,
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unsigned long parent_rate)
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{
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unsigned int div;
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if (!rate)
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rate = 1;
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div = DIV_ROUND_CLOSEST(parent_rate, rate);
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return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
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}
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static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
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return DIV_ROUND_CLOSEST(*parent_rate, div);
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}
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static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
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u32 val;
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unsigned int i;
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for (i = 0; i < clock->div_num; i++)
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if (div == clock->div_table[i].div)
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break;
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if (i >= clock->div_num)
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return -EINVAL;
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val = clk_readl(clock->reg);
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val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
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val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
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clk_writel(val, clock->reg);
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return 0;
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}
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static const struct clk_ops cpg_sd_clock_ops = {
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.enable = cpg_sd_clock_enable,
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.disable = cpg_sd_clock_disable,
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.is_enabled = cpg_sd_clock_is_enabled,
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.recalc_rate = cpg_sd_clock_recalc_rate,
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.round_rate = cpg_sd_clock_round_rate,
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.set_rate = cpg_sd_clock_set_rate,
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};
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static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
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void __iomem *base,
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const char *parent_name)
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{
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struct clk_init_data init;
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struct sd_clock *clock;
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struct clk *clk;
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unsigned int i;
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||||
|
||||
clock = kzalloc(sizeof(*clock), GFP_KERNEL);
|
||||
if (!clock)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = core->name;
|
||||
init.ops = &cpg_sd_clock_ops;
|
||||
init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
clock->reg = base + core->offset;
|
||||
clock->hw.init = &init;
|
||||
clock->div_table = cpg_sd_div_table;
|
||||
clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
|
||||
|
||||
clock->div_max = clock->div_table[0].div;
|
||||
clock->div_min = clock->div_max;
|
||||
for (i = 1; i < clock->div_num; i++) {
|
||||
clock->div_max = max(clock->div_max, clock->div_table[i].div);
|
||||
clock->div_min = min(clock->div_min, clock->div_table[i].div);
|
||||
}
|
||||
|
||||
clk = clk_register(NULL, &clock->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(clock);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
#define CPG_PLL0CR 0x00d8
|
||||
#define CPG_PLL2CR 0x002c
|
||||
#define CPG_PLL4CR 0x01f4
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
@ -512,13 +283,7 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
struct cpg_pll_config {
|
||||
unsigned int extal_div;
|
||||
unsigned int pll1_mult;
|
||||
unsigned int pll3_mult;
|
||||
};
|
||||
|
||||
static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
/* EXTAL div PLL1 mult PLL3 mult */
|
||||
{ 1, 192, 192, },
|
||||
{ 1, 192, 128, },
|
||||
@ -538,112 +303,9 @@ static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
{ 2, 192, 192, },
|
||||
};
|
||||
|
||||
static const struct cpg_pll_config *cpg_pll_config __initdata;
|
||||
|
||||
static
|
||||
struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core,
|
||||
const struct cpg_mssr_info *info,
|
||||
struct clk **clks,
|
||||
void __iomem *base)
|
||||
{
|
||||
const struct clk *parent;
|
||||
unsigned int mult = 1;
|
||||
unsigned int div = 1;
|
||||
u32 value;
|
||||
|
||||
parent = clks[core->parent];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_GEN3_MAIN:
|
||||
div = cpg_pll_config->extal_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL0:
|
||||
/*
|
||||
* PLL0 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
value = readl(base + CPG_PLL0CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL1:
|
||||
mult = cpg_pll_config->pll1_mult;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL2:
|
||||
/*
|
||||
* PLL2 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
value = readl(base + CPG_PLL2CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL3:
|
||||
mult = cpg_pll_config->pll3_mult;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL4:
|
||||
/*
|
||||
* PLL4 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
value = readl(base + CPG_PLL4CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_SD:
|
||||
return cpg_sd_clk_register(core, base, __clk_get_name(parent));
|
||||
|
||||
case CLK_TYPE_GEN3_R:
|
||||
/* RINT is default. Only if EXTALR is populated, we switch to it */
|
||||
value = readl(base + CPG_RCKCR) & 0x3f;
|
||||
|
||||
if (clk_get_rate(clks[CLK_EXTALR])) {
|
||||
parent = clks[CLK_EXTALR];
|
||||
value |= BIT(15);
|
||||
}
|
||||
|
||||
writel(value, base + CPG_RCKCR);
|
||||
break;
|
||||
|
||||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return clk_register_fixed_factor(NULL, core->name,
|
||||
__clk_get_name(parent), 0, mult, div);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset register definitions.
|
||||
*/
|
||||
#define MODEMR 0xe6160060
|
||||
|
||||
static u32 rcar_gen3_read_mode_pins(void)
|
||||
{
|
||||
void __iomem *modemr = ioremap_nocache(MODEMR, 4);
|
||||
u32 mode;
|
||||
|
||||
BUG_ON(!modemr);
|
||||
mode = ioread32(modemr);
|
||||
iounmap(modemr);
|
||||
|
||||
return mode;
|
||||
}
|
||||
|
||||
static int __init r8a7795_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode = rcar_gen3_read_mode_pins();
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
@ -652,7 +314,7 @@ static int __init r8a7795_cpg_mssr_init(struct device *dev)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
|
||||
@ -673,5 +335,5 @@ const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a7795_cpg_mssr_init,
|
||||
.cpg_clk_register = r8a7795_cpg_clk_register,
|
||||
.cpg_clk_register = rcar_gen3_cpg_clk_register,
|
||||
};
|
||||
|
||||
192
drivers/clk/renesas/r8a7796-cpg-mssr.c
Normal file
192
drivers/clk/renesas/r8a7796-cpg-mssr.c
Normal file
@ -0,0 +1,192 @@
|
||||
/*
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_SSPSRC,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
|
||||
DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
|
||||
};
|
||||
|
||||
static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
/* EXTAL div PLL1 mult PLL3 mult */
|
||||
{ 1, 192, 192, },
|
||||
{ 1, 192, 128, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 192, },
|
||||
{ 1, 160, 160, },
|
||||
{ 1, 160, 106, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 160, },
|
||||
{ 1, 128, 128, },
|
||||
{ 1, 128, 84, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 128, },
|
||||
{ 2, 192, 192, },
|
||||
{ 2, 192, 128, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 192, },
|
||||
};
|
||||
|
||||
static int __init r8a7796_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode = rcar_gen3_read_mode_pins();
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
if (!cpg_pll_config->extal_div) {
|
||||
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a7796_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a7796_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a7796_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a7796_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a7796_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a7796_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a7796_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen3_cpg_clk_register,
|
||||
};
|
||||
359
drivers/clk/renesas/rcar-gen3-cpg.c
Normal file
359
drivers/clk/renesas/rcar-gen3-cpg.c
Normal file
@ -0,0 +1,359 @@
|
||||
/*
|
||||
* R-Car Gen3 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2015-2016 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen3.c
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
#define CPG_PLL0CR 0x00d8
|
||||
#define CPG_PLL2CR 0x002c
|
||||
#define CPG_PLL4CR 0x01f4
|
||||
|
||||
|
||||
/*
|
||||
* SDn Clock
|
||||
*/
|
||||
#define CPG_SD_STP_HCK BIT(9)
|
||||
#define CPG_SD_STP_CK BIT(8)
|
||||
|
||||
#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
|
||||
#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
|
||||
|
||||
#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
|
||||
{ \
|
||||
.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
|
||||
((stp_ck) ? CPG_SD_STP_CK : 0) | \
|
||||
((sd_srcfc) << 2) | \
|
||||
((sd_fc) << 0), \
|
||||
.div = (sd_div), \
|
||||
}
|
||||
|
||||
struct sd_div_table {
|
||||
u32 val;
|
||||
unsigned int div;
|
||||
};
|
||||
|
||||
struct sd_clock {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
const struct sd_div_table *div_table;
|
||||
unsigned int div_num;
|
||||
unsigned int div_min;
|
||||
unsigned int div_max;
|
||||
};
|
||||
|
||||
/* SDn divider
|
||||
* sd_srcfc sd_fc div
|
||||
* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 (1) 1 (4) 4
|
||||
* 0 0 1 (2) 1 (4) 8
|
||||
* 1 0 2 (4) 1 (4) 16
|
||||
* 1 0 3 (8) 1 (4) 32
|
||||
* 1 0 4 (16) 1 (4) 64
|
||||
* 0 0 0 (1) 0 (2) 2
|
||||
* 0 0 1 (2) 0 (2) 4
|
||||
* 1 0 2 (4) 0 (2) 8
|
||||
* 1 0 3 (8) 0 (2) 16
|
||||
* 1 0 4 (16) 0 (2) 32
|
||||
*/
|
||||
static const struct sd_div_table cpg_sd_div_table[] = {
|
||||
/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
|
||||
CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
|
||||
CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
|
||||
};
|
||||
|
||||
#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
|
||||
|
||||
static int cpg_sd_clock_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
u32 val, sd_fc;
|
||||
unsigned int i;
|
||||
|
||||
val = clk_readl(clock->reg);
|
||||
|
||||
sd_fc = val & CPG_SD_FC_MASK;
|
||||
for (i = 0; i < clock->div_num; i++)
|
||||
if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
|
||||
break;
|
||||
|
||||
if (i >= clock->div_num)
|
||||
return -EINVAL;
|
||||
|
||||
val &= ~(CPG_SD_STP_MASK);
|
||||
val |= clock->div_table[i].val & CPG_SD_STP_MASK;
|
||||
|
||||
clk_writel(val, clock->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void cpg_sd_clock_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
|
||||
clk_writel(clk_readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
|
||||
}
|
||||
|
||||
static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
|
||||
return !(clk_readl(clock->reg) & CPG_SD_STP_MASK);
|
||||
}
|
||||
|
||||
static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
unsigned long rate = parent_rate;
|
||||
u32 val, sd_fc;
|
||||
unsigned int i;
|
||||
|
||||
val = clk_readl(clock->reg);
|
||||
|
||||
sd_fc = val & CPG_SD_FC_MASK;
|
||||
for (i = 0; i < clock->div_num; i++)
|
||||
if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
|
||||
break;
|
||||
|
||||
if (i >= clock->div_num)
|
||||
return -EINVAL;
|
||||
|
||||
return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
|
||||
}
|
||||
|
||||
static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned int div;
|
||||
|
||||
if (!rate)
|
||||
rate = 1;
|
||||
|
||||
div = DIV_ROUND_CLOSEST(parent_rate, rate);
|
||||
|
||||
return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
|
||||
}
|
||||
|
||||
static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
|
||||
|
||||
return DIV_ROUND_CLOSEST(*parent_rate, div);
|
||||
}
|
||||
|
||||
static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
|
||||
u32 val;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < clock->div_num; i++)
|
||||
if (div == clock->div_table[i].div)
|
||||
break;
|
||||
|
||||
if (i >= clock->div_num)
|
||||
return -EINVAL;
|
||||
|
||||
val = clk_readl(clock->reg);
|
||||
val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
|
||||
val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
|
||||
clk_writel(val, clock->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops cpg_sd_clock_ops = {
|
||||
.enable = cpg_sd_clock_enable,
|
||||
.disable = cpg_sd_clock_disable,
|
||||
.is_enabled = cpg_sd_clock_is_enabled,
|
||||
.recalc_rate = cpg_sd_clock_recalc_rate,
|
||||
.round_rate = cpg_sd_clock_round_rate,
|
||||
.set_rate = cpg_sd_clock_set_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
|
||||
void __iomem *base,
|
||||
const char *parent_name)
|
||||
{
|
||||
struct clk_init_data init;
|
||||
struct sd_clock *clock;
|
||||
struct clk *clk;
|
||||
unsigned int i;
|
||||
|
||||
clock = kzalloc(sizeof(*clock), GFP_KERNEL);
|
||||
if (!clock)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = core->name;
|
||||
init.ops = &cpg_sd_clock_ops;
|
||||
init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
clock->reg = base + core->offset;
|
||||
clock->hw.init = &init;
|
||||
clock->div_table = cpg_sd_div_table;
|
||||
clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
|
||||
|
||||
clock->div_max = clock->div_table[0].div;
|
||||
clock->div_min = clock->div_max;
|
||||
for (i = 1; i < clock->div_num; i++) {
|
||||
clock->div_max = max(clock->div_max, clock->div_table[i].div);
|
||||
clock->div_min = min(clock->div_min, clock->div_table[i].div);
|
||||
}
|
||||
|
||||
clk = clk_register(NULL, &clock->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(clock);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
|
||||
static unsigned int cpg_clk_extalr __initdata;
|
||||
|
||||
struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
||||
struct clk **clks, void __iomem *base)
|
||||
{
|
||||
const struct clk *parent;
|
||||
unsigned int mult = 1;
|
||||
unsigned int div = 1;
|
||||
u32 value;
|
||||
|
||||
parent = clks[core->parent];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_GEN3_MAIN:
|
||||
div = cpg_pll_config->extal_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL0:
|
||||
/*
|
||||
* PLL0 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
value = readl(base + CPG_PLL0CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL1:
|
||||
mult = cpg_pll_config->pll1_mult;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL2:
|
||||
/*
|
||||
* PLL2 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
value = readl(base + CPG_PLL2CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL3:
|
||||
mult = cpg_pll_config->pll3_mult;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL4:
|
||||
/*
|
||||
* PLL4 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
value = readl(base + CPG_PLL4CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_SD:
|
||||
return cpg_sd_clk_register(core, base, __clk_get_name(parent));
|
||||
|
||||
case CLK_TYPE_GEN3_R:
|
||||
/*
|
||||
* RINT is default.
|
||||
* Only if EXTALR is populated, we switch to it.
|
||||
*/
|
||||
value = readl(base + CPG_RCKCR) & 0x3f;
|
||||
|
||||
if (clk_get_rate(clks[cpg_clk_extalr])) {
|
||||
parent = clks[cpg_clk_extalr];
|
||||
value |= BIT(15);
|
||||
}
|
||||
|
||||
writel(value, base + CPG_RCKCR);
|
||||
break;
|
||||
|
||||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return clk_register_fixed_factor(NULL, core->name,
|
||||
__clk_get_name(parent), 0, mult, div);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset register definitions.
|
||||
*/
|
||||
#define MODEMR 0xe6160060
|
||||
|
||||
u32 __init rcar_gen3_read_mode_pins(void)
|
||||
{
|
||||
void __iomem *modemr = ioremap_nocache(MODEMR, 4);
|
||||
u32 mode;
|
||||
|
||||
BUG_ON(!modemr);
|
||||
mode = ioread32(modemr);
|
||||
iounmap(modemr);
|
||||
|
||||
return mode;
|
||||
}
|
||||
|
||||
int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
|
||||
unsigned int clk_extalr)
|
||||
{
|
||||
cpg_pll_config = config;
|
||||
cpg_clk_extalr = clk_extalr;
|
||||
return 0;
|
||||
}
|
||||
43
drivers/clk/renesas/rcar-gen3-cpg.h
Normal file
43
drivers/clk/renesas/rcar-gen3-cpg.h
Normal file
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* R-Car Gen3 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2015-2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
||||
#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
||||
|
||||
enum rcar_gen3_clk_types {
|
||||
CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
|
||||
CLK_TYPE_GEN3_PLL0,
|
||||
CLK_TYPE_GEN3_PLL1,
|
||||
CLK_TYPE_GEN3_PLL2,
|
||||
CLK_TYPE_GEN3_PLL3,
|
||||
CLK_TYPE_GEN3_PLL4,
|
||||
CLK_TYPE_GEN3_SD,
|
||||
CLK_TYPE_GEN3_R,
|
||||
};
|
||||
|
||||
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
||||
|
||||
struct rcar_gen3_cpg_pll_config {
|
||||
unsigned int extal_div;
|
||||
unsigned int pll1_mult;
|
||||
unsigned int pll3_mult;
|
||||
};
|
||||
|
||||
#define CPG_RCKCR 0x240
|
||||
|
||||
u32 rcar_gen3_read_mode_pins(void);
|
||||
struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
||||
struct clk **clks, void __iomem *base);
|
||||
int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
|
||||
unsigned int clk_extalr);
|
||||
|
||||
#endif
|
||||
@ -508,6 +508,12 @@ static const struct of_device_id cpg_mssr_match[] = {
|
||||
.compatible = "renesas,r8a7795-cpg-mssr",
|
||||
.data = &r8a7795_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A7796
|
||||
{
|
||||
.compatible = "renesas,r8a7796-cpg-mssr",
|
||||
.data = &r8a7796_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
@ -131,4 +131,5 @@ struct cpg_mssr_info {
|
||||
};
|
||||
|
||||
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
|
||||
#endif
|
||||
|
||||
69
include/dt-bindings/clock/r8a7796-cpg-mssr.h
Normal file
69
include/dt-bindings/clock/r8a7796-cpg-mssr.h
Normal file
@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a7796 CPG Core Clocks */
|
||||
#define R8A7796_CLK_Z 0
|
||||
#define R8A7796_CLK_Z2 1
|
||||
#define R8A7796_CLK_ZR 2
|
||||
#define R8A7796_CLK_ZG 3
|
||||
#define R8A7796_CLK_ZTR 4
|
||||
#define R8A7796_CLK_ZTRD2 5
|
||||
#define R8A7796_CLK_ZT 6
|
||||
#define R8A7796_CLK_ZX 7
|
||||
#define R8A7796_CLK_S0D1 8
|
||||
#define R8A7796_CLK_S0D2 9
|
||||
#define R8A7796_CLK_S0D3 10
|
||||
#define R8A7796_CLK_S0D4 11
|
||||
#define R8A7796_CLK_S0D6 12
|
||||
#define R8A7796_CLK_S0D8 13
|
||||
#define R8A7796_CLK_S0D12 14
|
||||
#define R8A7796_CLK_S1D1 15
|
||||
#define R8A7796_CLK_S1D2 16
|
||||
#define R8A7796_CLK_S1D4 17
|
||||
#define R8A7796_CLK_S2D1 18
|
||||
#define R8A7796_CLK_S2D2 19
|
||||
#define R8A7796_CLK_S2D4 20
|
||||
#define R8A7796_CLK_S3D1 21
|
||||
#define R8A7796_CLK_S3D2 22
|
||||
#define R8A7796_CLK_S3D4 23
|
||||
#define R8A7796_CLK_LB 24
|
||||
#define R8A7796_CLK_CL 25
|
||||
#define R8A7796_CLK_ZB3 26
|
||||
#define R8A7796_CLK_ZB3D2 27
|
||||
#define R8A7796_CLK_ZB3D4 28
|
||||
#define R8A7796_CLK_CR 29
|
||||
#define R8A7796_CLK_CRD2 30
|
||||
#define R8A7796_CLK_SD0H 31
|
||||
#define R8A7796_CLK_SD0 32
|
||||
#define R8A7796_CLK_SD1H 33
|
||||
#define R8A7796_CLK_SD1 34
|
||||
#define R8A7796_CLK_SD2H 35
|
||||
#define R8A7796_CLK_SD2 36
|
||||
#define R8A7796_CLK_SD3H 37
|
||||
#define R8A7796_CLK_SD3 38
|
||||
#define R8A7796_CLK_SSP2 39
|
||||
#define R8A7796_CLK_SSP1 40
|
||||
#define R8A7796_CLK_SSPRS 41
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||||
#define R8A7796_CLK_RPC 42
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#define R8A7796_CLK_RPCD2 43
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#define R8A7796_CLK_MSO 44
|
||||
#define R8A7796_CLK_CANFD 45
|
||||
#define R8A7796_CLK_HDMI 46
|
||||
#define R8A7796_CLK_CSI0 47
|
||||
#define R8A7796_CLK_CSIREF 48
|
||||
#define R8A7796_CLK_CP 49
|
||||
#define R8A7796_CLK_CPEX 50
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#define R8A7796_CLK_R 51
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||||
#define R8A7796_CLK_OSC 52
|
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|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */
|
||||
Loading…
Reference in New Issue
Block a user