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Merge branch 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull RAS updates from Borislav Petkov: - Support for varying MCA bank numbers per CPU: this is in preparation for future CPU enablement (Yazen Ghannam) - MCA banks read race fix (Tony Luck) - Facility to filter MCEs which should not be logged (Yazen Ghannam) - The usual round of cleanups and fixes * 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/MCE/AMD: Don't report L1 BTB MCA errors on some family 17h models x86/MCE: Add an MCE-record filtering function RAS/CEC: Increment cec_entered under the mutex lock x86/mce: Fix debugfs_simple_attr.cocci warnings x86/mce: Remove mce_report_event() x86/mce: Handle varying MCA bank counts x86/mce: Fix machine_check_poll() tests for error types MAINTAINERS: Fix file pattern for X86 MCE INFRASTRUCTURE x86/MCE: Group AMD function prototypes in <asm/mce.h>
This commit is contained in:
Linus Torvalds
commit
ffa6f55eb6
@ -16941,7 +16941,7 @@ M: Tony Luck <tony.luck@intel.com>
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M: Borislav Petkov <bp@alien8.de>
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L: linux-edac@vger.kernel.org
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S: Maintained
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F: arch/x86/kernel/cpu/mcheck/*
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F: arch/x86/kernel/cpu/mce/*
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X86 MICROCODE UPDATE SUPPORT
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M: Borislav Petkov <bp@alien8.de>
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@ -210,16 +210,6 @@ static inline void cmci_rediscover(void) {}
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static inline void cmci_recheck(void) {}
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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void mce_amd_feature_init(struct cpuinfo_x86 *c);
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int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
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#else
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
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static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
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#endif
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static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
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int mce_available(struct cpuinfo_x86 *c);
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bool mce_is_memory_error(struct mce *m);
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bool mce_is_correctable(struct mce *m);
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@ -345,12 +335,19 @@ extern bool amd_mce_is_memory_error(struct mce *m);
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extern int mce_threshold_create_device(unsigned int cpu);
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extern int mce_threshold_remove_device(unsigned int cpu);
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void mce_amd_feature_init(struct cpuinfo_x86 *c);
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int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
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#else
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static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
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static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
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static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
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static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
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static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
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static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
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static inline int
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umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
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#endif
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static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
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#endif /* _ASM_X86_MCE_H */
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@ -563,33 +563,59 @@ out:
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return offset;
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}
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/*
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* Turn off MC4_MISC thresholding banks on all family 0x15 models since
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* they're not supported there.
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*/
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void disable_err_thresholding(struct cpuinfo_x86 *c)
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bool amd_filter_mce(struct mce *m)
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{
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int i;
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enum smca_bank_types bank_type = smca_get_bank_type(m->bank);
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struct cpuinfo_x86 *c = &boot_cpu_data;
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u8 xec = (m->status >> 16) & 0x3F;
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/* See Family 17h Models 10h-2Fh Erratum #1114. */
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if (c->x86 == 0x17 &&
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c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
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bank_type == SMCA_IF && xec == 10)
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return true;
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return false;
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}
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/*
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* Turn off thresholding banks for the following conditions:
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* - MC4_MISC thresholding is not supported on Family 0x15.
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* - Prevent possible spurious interrupts from the IF bank on Family 0x17
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* Models 0x10-0x2F due to Erratum #1114.
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*/
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void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
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{
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int i, num_msrs;
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u64 hwcr;
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bool need_toggle;
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u32 msrs[] = {
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0x00000413, /* MC4_MISC0 */
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0xc0000408, /* MC4_MISC1 */
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};
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u32 msrs[NR_BLOCKS];
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if (c->x86 != 0x15)
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if (c->x86 == 0x15 && bank == 4) {
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msrs[0] = 0x00000413; /* MC4_MISC0 */
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msrs[1] = 0xc0000408; /* MC4_MISC1 */
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num_msrs = 2;
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} else if (c->x86 == 0x17 &&
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(c->x86_model >= 0x10 && c->x86_model <= 0x2F)) {
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if (smca_get_bank_type(bank) != SMCA_IF)
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return;
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msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);
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num_msrs = 1;
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} else {
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return;
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}
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rdmsrl(MSR_K7_HWCR, hwcr);
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/* McStatusWrEn has to be set */
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need_toggle = !(hwcr & BIT(18));
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if (need_toggle)
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wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
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/* Clear CntP bit safely */
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for (i = 0; i < ARRAY_SIZE(msrs); i++)
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for (i = 0; i < num_msrs; i++)
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msr_clear_bit(msrs[i], 62);
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/* restore old settings */
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@ -604,12 +630,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
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unsigned int bank, block, cpu = smp_processor_id();
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int offset = -1;
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disable_err_thresholding(c);
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for (bank = 0; bank < mca_cfg.banks; ++bank) {
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if (mce_flags.smca)
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smca_configure(bank, cpu);
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disable_err_thresholding(c, bank);
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for (block = 0; block < NR_BLOCKS; ++block) {
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address = get_block_address(address, low, high, bank, block);
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if (!address)
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@ -460,23 +460,6 @@ static void mce_irq_work_cb(struct irq_work *entry)
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mce_schedule_work();
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}
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static void mce_report_event(struct pt_regs *regs)
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{
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if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
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mce_notify_irq();
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/*
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* Triggering the work queue here is just an insurance
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* policy in case the syscall exit notify handler
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* doesn't run soon enough or ends up running on the
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* wrong CPU (can happen when audit sleeps)
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*/
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mce_schedule_work();
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return;
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}
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irq_work_queue(&mce_irq_work);
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}
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/*
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* Check if the address reported by the CPU is in a format we can parse.
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* It would be possible to add code for most other cases, but all would
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@ -712,19 +695,49 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
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barrier();
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m.status = mce_rdmsrl(msr_ops.status(i));
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/* If this entry is not valid, ignore it */
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if (!(m.status & MCI_STATUS_VAL))
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continue;
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/*
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* Uncorrected or signalled events are handled by the exception
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* handler when it is enabled, so don't process those here.
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*
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* TBD do the same check for MCI_STATUS_EN here?
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* If we are logging everything (at CPU online) or this
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* is a corrected error, then we must log it.
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*/
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if (!(flags & MCP_UC) &&
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(m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
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continue;
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if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
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goto log_it;
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/*
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* Newer Intel systems that support software error
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* recovery need to make additional checks. Other
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* CPUs should skip over uncorrected errors, but log
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* everything else.
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*/
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if (!mca_cfg.ser) {
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if (m.status & MCI_STATUS_UC)
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continue;
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goto log_it;
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}
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/* Log "not enabled" (speculative) errors */
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if (!(m.status & MCI_STATUS_EN))
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goto log_it;
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/*
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* Log UCNA (SDM: 15.6.3 "UCR Error Classification")
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* UC == 1 && PCC == 0 && S == 0
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*/
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if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
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goto log_it;
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/*
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* Skip anything else. Presumption is that our read of this
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* bank is racing with a machine check. Leave the log alone
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* for do_machine_check() to deal with it.
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*/
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continue;
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log_it:
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error_seen = true;
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mce_read_aux(&m, i);
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@ -1301,7 +1314,8 @@ void do_machine_check(struct pt_regs *regs, long error_code)
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mce_panic("Fatal machine check on current CPU", &m, msg);
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if (worst > 0)
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mce_report_event(regs);
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irq_work_queue(&mce_irq_work);
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mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
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sync_core();
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@ -1451,13 +1465,12 @@ EXPORT_SYMBOL_GPL(mce_notify_irq);
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static int __mcheck_cpu_mce_banks_init(void)
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{
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int i;
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u8 num_banks = mca_cfg.banks;
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mce_banks = kcalloc(num_banks, sizeof(struct mce_bank), GFP_KERNEL);
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mce_banks = kcalloc(MAX_NR_BANKS, sizeof(struct mce_bank), GFP_KERNEL);
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if (!mce_banks)
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return -ENOMEM;
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for (i = 0; i < num_banks; i++) {
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for (i = 0; i < MAX_NR_BANKS; i++) {
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struct mce_bank *b = &mce_banks[i];
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b->ctl = -1ULL;
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@ -1471,28 +1484,19 @@ static int __mcheck_cpu_mce_banks_init(void)
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*/
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static int __mcheck_cpu_cap_init(void)
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{
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unsigned b;
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u64 cap;
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u8 b;
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rdmsrl(MSR_IA32_MCG_CAP, cap);
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b = cap & MCG_BANKCNT_MASK;
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if (!mca_cfg.banks)
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pr_info("CPU supports %d MCE banks\n", b);
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if (b > MAX_NR_BANKS) {
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pr_warn("Using only %u machine check banks out of %u\n",
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MAX_NR_BANKS, b);
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if (WARN_ON_ONCE(b > MAX_NR_BANKS))
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b = MAX_NR_BANKS;
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}
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/* Don't support asymmetric configurations today */
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WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks);
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mca_cfg.banks = b;
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mca_cfg.banks = max(mca_cfg.banks, b);
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if (!mce_banks) {
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int err = __mcheck_cpu_mce_banks_init();
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if (err)
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return err;
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}
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@ -1771,6 +1775,14 @@ static void __mcheck_cpu_init_timer(void)
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mce_start_timer(t);
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}
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bool filter_mce(struct mce *m)
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{
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
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return amd_filter_mce(m);
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return false;
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}
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/* Handle unconfigured int18 (should never happen) */
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static void unexpected_machine_check(struct pt_regs *regs, long error_code)
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{
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@ -2425,8 +2437,8 @@ static int fake_panic_set(void *data, u64 val)
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
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fake_panic_set, "%llu\n");
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DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set,
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"%llu\n");
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static int __init mcheck_debugfs_init(void)
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{
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@ -2435,8 +2447,8 @@ static int __init mcheck_debugfs_init(void)
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dmce = mce_get_debugfs_dir();
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if (!dmce)
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return -ENOMEM;
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ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
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&fake_panic_fops);
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ffake_panic = debugfs_create_file_unsafe("fake_panic", 0444, dmce,
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NULL, &fake_panic_fops);
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if (!ffake_panic)
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return -ENOMEM;
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@ -2451,6 +2463,8 @@ EXPORT_SYMBOL_GPL(mcsafe_key);
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static int __init mcheck_late_init(void)
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{
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pr_info("Using %d MCE banks\n", mca_cfg.banks);
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if (mca_cfg.recovery)
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static_branch_inc(&mcsafe_key);
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@ -99,6 +99,9 @@ int mce_gen_pool_add(struct mce *mce)
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{
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struct mce_evt_llist *node;
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if (filter_mce(mce))
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return -EINVAL;
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if (!mce_evt_pool)
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return -EINVAL;
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@ -46,8 +46,6 @@
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static struct mce i_mce;
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static struct dentry *dfs_inj;
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static u8 n_banks;
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#define MAX_FLAG_OPT_SIZE 4
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#define NBCFG 0x44
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@ -570,9 +568,15 @@ err:
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static int inj_bank_set(void *data, u64 val)
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{
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struct mce *m = (struct mce *)data;
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u8 n_banks;
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u64 cap;
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/* Get bank count on target CPU so we can handle non-uniform values. */
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rdmsrl_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap);
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n_banks = cap & MCG_BANKCNT_MASK;
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if (val >= n_banks) {
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pr_err("Non-existent MCE bank: %llu\n", val);
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pr_err("MCA bank %llu non-existent on CPU%d\n", val, m->extcpu);
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return -EINVAL;
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}
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@ -665,10 +669,6 @@ static struct dfs_node {
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static int __init debugfs_init(void)
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{
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unsigned int i;
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u64 cap;
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rdmsrl(MSR_IA32_MCG_CAP, cap);
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n_banks = cap & MCG_BANKCNT_MASK;
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dfs_inj = debugfs_create_dir("mce-inject", NULL);
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if (!dfs_inj)
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@ -173,4 +173,13 @@ struct mca_msr_regs {
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extern struct mca_msr_regs msr_ops;
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/* Decide whether to add MCE record to MCE event pool or filter it out. */
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extern bool filter_mce(struct mce *m);
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#ifdef CONFIG_X86_MCE_AMD
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extern bool amd_filter_mce(struct mce *m);
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#else
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static inline bool amd_filter_mce(struct mce *m) { return false; };
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#endif
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#endif /* __X86_MCE_INTERNAL_H__ */
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@ -1004,7 +1004,7 @@ static inline void amd_decode_err_code(u16 ec)
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/*
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* Filter out unwanted MCE signatures here.
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*/
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static bool amd_filter_mce(struct mce *m)
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static bool ignore_mce(struct mce *m)
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{
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/*
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* NB GART TLB error reporting is disabled by default.
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@ -1038,7 +1038,7 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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unsigned int fam = x86_family(m->cpuid);
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int ecc;
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if (amd_filter_mce(m))
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if (ignore_mce(m))
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return NOTIFY_STOP;
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pr_emerg(HW_ERR "%s\n", decode_error_status(m));
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@ -286,10 +286,10 @@ int cec_add_elem(u64 pfn)
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if (!ce_arr.array || ce_arr.disabled)
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return -ENODEV;
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ca->ces_entered++;
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mutex_lock(&ce_mutex);
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ca->ces_entered++;
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if (ca->n == MAX_ELEMS)
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WARN_ON(!del_lru_elem_unlocked(ca));
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|
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