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ARM: dts: dra7: add support for parallel NAND flash
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used for accessing externel NAND flash device. This patch: - adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines - adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm *Important* On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch So following board settings are required for NAND device detection: SW5.9 (GPMC_WPN) = LOW SW5.1 (NAND_BOOTn) = HIGH Signed-off-by: Minal Shah <minalkshah@gmail.com> Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Minal Shah
Tony Lindgren
parent
7b25babf6e
commit
ff66a3c86e
@ -120,6 +120,37 @@
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0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
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>;
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};
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nand_flash_x16: nand_flash_x16 {
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/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
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* So NAND flash requires following switch settings:
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* SW5.9 (GPMC_WPN) = LOW
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* SW5.1 (NAND_BOOTn) = HIGH */
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pinctrl-single,pins = <
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0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
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0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
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0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
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0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
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0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
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0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
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0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
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0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
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0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
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0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
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0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
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0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
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0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
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0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
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0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
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0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
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0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
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0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
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0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
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0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
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0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
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0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
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>;
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};
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};
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&i2c1 {
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@ -377,3 +408,90 @@
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pinctrl-names = "default";
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pinctrl-0 = <&usb2_pins>;
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};
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&elm {
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status = "okay";
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};
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&gpmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&nand_flash_x16>;
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ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
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nand@0,0 {
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reg = <0 0 4>; /* device IO registers */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <40>;
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gpmc,cs-wr-off-ns = <40>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <30>;
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gpmc,adv-wr-off-ns = <30>;
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gpmc,we-on-ns = <5>;
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gpmc,we-off-ns = <25>;
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gpmc,oe-on-ns = <2>;
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gpmc,oe-off-ns = <20>;
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gpmc,access-ns = <20>;
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gpmc,wr-access-ns = <40>;
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gpmc,rd-cycle-ns = <40>;
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gpmc,wr-cycle-ns = <40>;
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gpmc,wait-pin = <0>;
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gpmc,wait-on-read;
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gpmc,wait-on-write;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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/* All SPL-* partitions are sized to minimal length
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* which can be independently programmable. For
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* NAND flash this is equal to size of erase-block */
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "NAND.SPL";
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reg = <0x00000000 0x000020000>;
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};
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partition@1 {
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label = "NAND.SPL.backup1";
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reg = <0x00020000 0x00020000>;
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};
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partition@2 {
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label = "NAND.SPL.backup2";
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reg = <0x00040000 0x00020000>;
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};
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partition@3 {
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label = "NAND.SPL.backup3";
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reg = <0x00060000 0x00020000>;
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};
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partition@4 {
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label = "NAND.u-boot-spl-os";
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reg = <0x00080000 0x00040000>;
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};
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partition@5 {
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label = "NAND.u-boot";
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reg = <0x000c0000 0x00100000>;
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};
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partition@6 {
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label = "NAND.u-boot-env";
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reg = <0x001c0000 0x00020000>;
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};
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partition@7 {
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label = "NAND.u-boot-env";
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reg = <0x001e0000 0x00020000>;
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};
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partition@8 {
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label = "NAND.kernel";
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reg = <0x00200000 0x00800000>;
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};
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partition@9 {
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label = "NAND.file-system";
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reg = <0x00a00000 0x0f600000>;
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};
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};
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};
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@ -964,6 +964,26 @@
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dr_mode = "otg";
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};
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};
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elm: elm@48078000 {
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compatible = "ti,am3352-elm";
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reg = <0x48078000 0xfc0>; /* device IO registers */
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "elm";
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status = "disabled";
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};
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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reg = <0x50000000 0x37c>; /* device IO registers */
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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status = "disabled";
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};
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};
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};
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