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tools/power/turbostat: Adjust cstate for has_slv_msrs() models

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Disable PC2/PC3/PC7 and enable PC6 for has_slv_msrs() models.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
This commit is contained in:
Zhang Rui 2023-08-27 14:07:08 +08:00
parent 192cbf0468
commit ff20614955
1 changed files with 1 additions and 5 deletions
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6
tools/power/x86/turbostat/turbostat.c
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@ -635,7 +635,7 @@ static const struct platform_features spr_features = {
static const struct platform_features slv_features = {
.has_nhm_msrs = 1,
.bclk_freq = BCLK_SLV,
.supported_cstates = CC1 | CC3 | CC6 | PC3 | PC6,
.supported_cstates = CC1 | CC3 | CC6 | PC6,
.cst_limit = CST_LIMIT_SLV,
.trl_msrs = TRL_ATOM,
.rapl_msrs = RAPL_PKG | RAPL_CORE,
@ -5829,10 +5829,6 @@ void process_cpuid()
do_irtl_snb = has_snb_msrs(family, model);
if (has_slv_msrs(family, model)) {
BIC_NOT_PRESENT(BIC_Pkgpc2);
BIC_NOT_PRESENT(BIC_Pkgpc3);
BIC_PRESENT(BIC_Pkgpc6);
BIC_NOT_PRESENT(BIC_Pkgpc7);
BIC_PRESENT(BIC_Mod_c6);
use_c1_residency_msr = 1;
}