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ARM: davinci: dm355: Remove legacy clock init
This removes the unused legacy clock init code from arch/arm/mach-davinci/dm355.c. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
David Lechner
Sekhar Nori
parent
9cc247b82d
commit
feee4eda2d
@ -35,11 +35,6 @@
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#include "davinci.h"
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#include "mux.h"
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#ifndef CONFIG_COMMON_CLK
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#include "clock.h"
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#include "psc.h"
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#endif
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#define DM355_UART2_BASE (IO_PHYS + 0x206000)
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#define DM355_OSD_BASE (IO_PHYS + 0x70200)
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#define DM355_VENC_BASE (IO_PHYS + 0x70400)
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@ -49,349 +44,6 @@
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*/
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#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
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#ifndef CONFIG_COMMON_CLK
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static struct pll_data pll1_data = {
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.num = 1,
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.phys_base = DAVINCI_PLL1_BASE,
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.flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
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};
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static struct pll_data pll2_data = {
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.num = 2,
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.phys_base = DAVINCI_PLL2_BASE,
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.flags = PLL_HAS_PREDIV,
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};
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static struct clk ref_clk = {
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.name = "ref_clk",
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/* FIXME -- crystal rate is board-specific */
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.rate = DM355_REF_FREQ,
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};
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static struct clk pll1_clk = {
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.name = "pll1",
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.parent = &ref_clk,
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.flags = CLK_PLL,
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.pll_data = &pll1_data,
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};
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static struct clk pll1_aux_clk = {
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.name = "pll1_aux_clk",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk pll1_sysclk1 = {
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.name = "pll1_sysclk1",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll1_sysclk2 = {
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.name = "pll1_sysclk2",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV2,
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};
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static struct clk pll1_sysclk3 = {
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.name = "pll1_sysclk3",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV3,
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};
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static struct clk pll1_sysclk4 = {
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.name = "pll1_sysclk4",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV4,
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};
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static struct clk pll1_sysclkbp = {
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.name = "pll1_sysclkbp",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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.div_reg = BPDIV
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};
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static struct clk vpss_dac_clk = {
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.name = "vpss_dac",
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.parent = &pll1_sysclk3,
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.lpsc = DM355_LPSC_VPSS_DAC,
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};
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static struct clk vpss_master_clk = {
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.name = "vpss_master",
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.parent = &pll1_sysclk4,
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.lpsc = DAVINCI_LPSC_VPSSMSTR,
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.flags = CLK_PSC,
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};
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static struct clk vpss_slave_clk = {
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.name = "vpss_slave",
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.parent = &pll1_sysclk4,
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.lpsc = DAVINCI_LPSC_VPSSSLV,
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};
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static struct clk clkout1_clk = {
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.name = "clkout1",
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.parent = &pll1_aux_clk,
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/* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
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};
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static struct clk clkout2_clk = {
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.name = "clkout2",
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.parent = &pll1_sysclkbp,
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};
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static struct clk pll2_clk = {
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.name = "pll2",
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.parent = &ref_clk,
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.flags = CLK_PLL,
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.pll_data = &pll2_data,
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};
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static struct clk pll2_sysclk1 = {
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.name = "pll2_sysclk1",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll2_sysclkbp = {
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.name = "pll2_sysclkbp",
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.parent = &pll2_clk,
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.flags = CLK_PLL | PRE_PLL,
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.div_reg = BPDIV
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};
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static struct clk clkout3_clk = {
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.name = "clkout3",
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.parent = &pll2_sysclkbp,
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/* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
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};
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static struct clk arm_clk = {
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.name = "arm_clk",
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.parent = &pll1_sysclk1,
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.lpsc = DAVINCI_LPSC_ARM,
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.flags = ALWAYS_ENABLED,
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};
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/*
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* NOT LISTED below, and not touched by Linux
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* - in SyncReset state by default
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* .lpsc = DAVINCI_LPSC_TPCC,
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* .lpsc = DAVINCI_LPSC_TPTC0,
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* .lpsc = DAVINCI_LPSC_TPTC1,
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* .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
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* .lpsc = DAVINCI_LPSC_MEMSTICK,
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* - in Enabled state by default
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* .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
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* .lpsc = DAVINCI_LPSC_SCR2, // "bus"
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* .lpsc = DAVINCI_LPSC_SCR3, // "bus"
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* .lpsc = DAVINCI_LPSC_SCR4, // "bus"
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* .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
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* .lpsc = DAVINCI_LPSC_CFG27, // "test"
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* .lpsc = DAVINCI_LPSC_CFG3, // "test"
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* .lpsc = DAVINCI_LPSC_CFG5, // "test"
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*/
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static struct clk mjcp_clk = {
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.name = "mjcp",
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.parent = &pll1_sysclk1,
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.lpsc = DAVINCI_LPSC_IMCOP,
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};
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static struct clk uart0_clk = {
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.name = "uart0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_UART0,
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};
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static struct clk uart1_clk = {
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.name = "uart1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_UART1,
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};
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static struct clk uart2_clk = {
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.name = "uart2",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_UART2,
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};
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static struct clk i2c_clk = {
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.name = "i2c",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_I2C,
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};
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static struct clk asp0_clk = {
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.name = "asp0",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_McBSP,
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};
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static struct clk asp1_clk = {
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.name = "asp1",
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.parent = &pll1_sysclk2,
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.lpsc = DM355_LPSC_McBSP1,
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};
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static struct clk mmcsd0_clk = {
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.name = "mmcsd0",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_MMC_SD,
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};
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static struct clk mmcsd1_clk = {
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.name = "mmcsd1",
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.parent = &pll1_sysclk2,
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.lpsc = DM355_LPSC_MMC_SD1,
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};
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static struct clk spi0_clk = {
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.name = "spi0",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_SPI,
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};
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static struct clk spi1_clk = {
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.name = "spi1",
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.parent = &pll1_sysclk2,
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.lpsc = DM355_LPSC_SPI1,
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};
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static struct clk spi2_clk = {
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.name = "spi2",
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.parent = &pll1_sysclk2,
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.lpsc = DM355_LPSC_SPI2,
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};
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static struct clk gpio_clk = {
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.name = "gpio",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_GPIO,
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};
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static struct clk aemif_clk = {
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.name = "aemif",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_AEMIF,
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};
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static struct clk pwm0_clk = {
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.name = "pwm0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM0,
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};
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static struct clk pwm1_clk = {
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.name = "pwm1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM1,
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};
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static struct clk pwm2_clk = {
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.name = "pwm2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM2,
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};
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static struct clk pwm3_clk = {
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.name = "pwm3",
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.parent = &pll1_aux_clk,
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.lpsc = DM355_LPSC_PWM3,
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};
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static struct clk timer0_clk = {
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.name = "timer0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER0,
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};
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static struct clk timer1_clk = {
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.name = "timer1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER1,
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};
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static struct clk timer2_clk = {
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.name = "timer2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER2,
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.usecount = 1, /* REVISIT: why can't this be disabled? */
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};
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static struct clk timer3_clk = {
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.name = "timer3",
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.parent = &pll1_aux_clk,
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.lpsc = DM355_LPSC_TIMER3,
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};
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static struct clk rto_clk = {
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.name = "rto",
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.parent = &pll1_aux_clk,
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.lpsc = DM355_LPSC_RTO,
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};
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static struct clk usb_clk = {
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.name = "usb",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_USB,
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};
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static struct clk_lookup dm355_clks[] = {
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CLK(NULL, "ref", &ref_clk),
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CLK(NULL, "pll1", &pll1_clk),
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CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
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CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
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CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
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CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
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CLK(NULL, "pll1_aux", &pll1_aux_clk),
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CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
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CLK(NULL, "vpss_dac", &vpss_dac_clk),
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CLK("vpss", "master", &vpss_master_clk),
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CLK("vpss", "slave", &vpss_slave_clk),
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CLK(NULL, "clkout1", &clkout1_clk),
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CLK(NULL, "clkout2", &clkout2_clk),
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CLK(NULL, "pll2", &pll2_clk),
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CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
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CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
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CLK(NULL, "clkout3", &clkout3_clk),
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CLK(NULL, "arm", &arm_clk),
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CLK(NULL, "mjcp", &mjcp_clk),
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CLK("serial8250.0", NULL, &uart0_clk),
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CLK("serial8250.1", NULL, &uart1_clk),
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CLK("serial8250.2", NULL, &uart2_clk),
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CLK("i2c_davinci.1", NULL, &i2c_clk),
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CLK("davinci-mcbsp.0", NULL, &asp0_clk),
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CLK("davinci-mcbsp.1", NULL, &asp1_clk),
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CLK("dm6441-mmc.0", NULL, &mmcsd0_clk),
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CLK("dm6441-mmc.1", NULL, &mmcsd1_clk),
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CLK("spi_davinci.0", NULL, &spi0_clk),
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CLK("spi_davinci.1", NULL, &spi1_clk),
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CLK("spi_davinci.2", NULL, &spi2_clk),
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CLK(NULL, "gpio", &gpio_clk),
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CLK(NULL, "aemif", &aemif_clk),
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CLK(NULL, "pwm0", &pwm0_clk),
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CLK(NULL, "pwm1", &pwm1_clk),
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CLK(NULL, "pwm2", &pwm2_clk),
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CLK(NULL, "pwm3", &pwm3_clk),
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CLK(NULL, "timer0", &timer0_clk),
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CLK(NULL, "timer1", &timer1_clk),
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CLK("davinci-wdt", NULL, &timer2_clk),
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CLK(NULL, "timer3", &timer3_clk),
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CLK(NULL, "rto", &rto_clk),
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CLK(NULL, "usb", &usb_clk),
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CLK(NULL, NULL, NULL),
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};
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#endif
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/*----------------------------------------------------------------------*/
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static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
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static struct resource dm355_spi0_resources[] = {
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@ -933,8 +585,6 @@ static struct davinci_id dm355_ids[] = {
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},
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};
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static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
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/*
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* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
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* T0_TOP: Timer 0, top : clocksource for generic timekeeping
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@ -1019,8 +669,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = {
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.jtag_id_reg = 0x01c40028,
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.ids = dm355_ids,
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.ids_num = ARRAY_SIZE(dm355_ids),
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.psc_bases = dm355_psc_bases,
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.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
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.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
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.pinmux_pins = dm355_pins,
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.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
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@ -1053,7 +701,6 @@ void __init dm355_init(void)
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void __init dm355_init_time(void)
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{
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#ifdef CONFIG_COMMON_CLK
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void __iomem *pll1, *psc;
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struct clk *clk;
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@ -1068,10 +715,6 @@ void __init dm355_init_time(void)
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clk = clk_get(NULL, "timer0");
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davinci_timer_init(clk);
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#else
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davinci_clk_init(dm355_clks);
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davinci_timer_init(&timer0_clk);
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#endif
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}
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static struct resource dm355_pll2_resources[] = {
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