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ARM: OMAP2+: PRCM: split PRCM module init to their own driver files
Splits the clock related provider module inits under their own driver files. Previously this was done for all modules under the common PRM driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -70,6 +70,7 @@ int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
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int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
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extern int cm_register(struct cm_ll_data *cld);
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extern int cm_unregister(struct cm_ll_data *cld);
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int omap_cm_init(void);
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# endif
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@ -15,10 +15,13 @@
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/bug.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "cm2xxx.h"
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#include "cm3xxx.h"
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#include "cm44xx.h"
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#include "clock.h"
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/*
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* cm_ll_data: function pointers to SoC-specific implementations of
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@ -212,3 +215,51 @@ int cm_unregister(struct cm_ll_data *cld)
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return 0;
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}
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static struct omap_prcm_init_data cm_data = {
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.index = TI_CLKM_CM,
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};
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static struct omap_prcm_init_data cm2_data = {
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.index = TI_CLKM_CM2,
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};
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static const struct of_device_id omap_cm_dt_match_table[] = {
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{ .compatible = "ti,omap3-cm", .data = &cm_data },
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{ .compatible = "ti,omap4-cm1", .data = &cm_data },
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{ .compatible = "ti,omap4-cm2", .data = &cm2_data },
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{ .compatible = "ti,omap5-cm-core-aon", .data = &cm_data },
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{ .compatible = "ti,omap5-cm-core", .data = &cm2_data },
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{ .compatible = "ti,dra7-cm-core-aon", .data = &cm_data },
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{ .compatible = "ti,dra7-cm-core", .data = &cm2_data },
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{ }
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};
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/**
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* omap_cm_init - low level init for the CM drivers
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*
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* Initializes the low level clock infrastructure for CM drivers.
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* Returns 0 in success, negative error value in failure.
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*/
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int __init omap_cm_init(void)
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{
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struct device_node *np;
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void __iomem *mem;
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const struct of_device_id *match;
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const struct omap_prcm_init_data *data;
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int ret;
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for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
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data = match->data;
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mem = of_iomap(np, 0);
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if (!mem)
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return -ENOMEM;
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ret = omap2_clk_provider_init(np, data->index, mem);
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if (ret)
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return ret;
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}
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return 0;
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}
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@ -14,6 +14,7 @@
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include "soc.h"
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#include "iomap.h"
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@ -25,6 +26,7 @@
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#include "sdrc.h"
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#include "pm.h"
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#include "control.h"
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#include "clock.h"
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/* Used by omap3_ctrl_save_padconf() */
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#define START_PADCONF_SAVE 0x2
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@ -611,3 +613,48 @@ void __init omap3_ctrl_init(void)
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omap3_ctrl_setup_d2d_padconf();
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}
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#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
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struct control_init_data {
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int index;
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};
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static struct control_init_data ctrl_data = {
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.index = TI_CLKM_CTRL,
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};
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static const struct of_device_id omap_scrm_dt_match_table[] = {
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{ .compatible = "ti,am3-scrm", .data = &ctrl_data },
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{ .compatible = "ti,am4-scrm", .data = &ctrl_data },
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{ .compatible = "ti,omap2-scrm", .data = &ctrl_data },
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{ .compatible = "ti,omap3-scrm", .data = &ctrl_data },
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{ }
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};
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/**
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* omap_control_init - low level init for the control driver
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*
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* Initializes the low level clock infrastructure for control driver.
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* Returns 0 in success, negative error value in failure.
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*/
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int __init omap_control_init(void)
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{
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struct device_node *np;
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void __iomem *mem;
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const struct of_device_id *match;
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const struct omap_prcm_init_data *data;
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int ret;
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for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
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data = match->data;
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mem = of_iomap(np, 0);
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if (!mem)
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return -ENOMEM;
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ret = omap2_clk_provider_init(np, data->index, mem);
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if (ret)
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return ret;
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}
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return 0;
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}
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@ -464,6 +464,7 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
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extern void omap3630_ctrl_disable_rta(void);
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extern int omap3_ctrl_save_padconf(void);
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void omap3_ctrl_init(void);
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int omap_control_init(void);
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extern void omap2_set_globals_control(void __iomem *ctrl,
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void __iomem *ctrl_pad);
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#else
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@ -756,6 +756,10 @@ int __init omap_clk_init(void)
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ti_clk_init_features();
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if (of_have_populated_dt()) {
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ret = omap_control_init();
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if (ret)
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return ret;
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ret = omap_prcm_init();
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if (ret)
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return ret;
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@ -637,43 +637,22 @@ static struct omap_prcm_init_data prm_data = {
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.index = TI_CLKM_PRM,
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};
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static struct omap_prcm_init_data cm_data = {
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.index = TI_CLKM_CM,
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};
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static struct omap_prcm_init_data cm2_data = {
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.index = TI_CLKM_CM2,
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};
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static struct omap_prcm_init_data scrm_data = {
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.index = TI_CLKM_SCRM,
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};
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static const struct of_device_id omap_prcm_dt_match_table[] = {
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{ .compatible = "ti,am3-prcm", .data = &prm_data },
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{ .compatible = "ti,am3-scrm", .data = &scrm_data },
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{ .compatible = "ti,am4-prcm", .data = &prm_data },
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{ .compatible = "ti,am4-scrm", .data = &scrm_data },
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{ .compatible = "ti,dm814-prcm", .data = &prm_data },
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{ .compatible = "ti,dm814-scrm", .data = &scrm_data },
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{ .compatible = "ti,dm816-prcm", .data = &prm_data },
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{ .compatible = "ti,dm816-scrm", .data = &scrm_data },
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{ .compatible = "ti,omap2-prcm", .data = &prm_data },
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{ .compatible = "ti,omap2-scrm", .data = &scrm_data },
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{ .compatible = "ti,omap3-prm", .data = &prm_data },
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{ .compatible = "ti,omap3-cm", .data = &cm_data },
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{ .compatible = "ti,omap3-scrm", .data = &scrm_data },
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{ .compatible = "ti,omap4-cm1", .data = &cm_data },
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{ .compatible = "ti,omap4-prm", .data = &prm_data },
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{ .compatible = "ti,omap4-cm2", .data = &cm2_data },
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{ .compatible = "ti,omap4-scrm", .data = &scrm_data },
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{ .compatible = "ti,omap5-prm", .data = &prm_data },
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{ .compatible = "ti,omap5-cm-core-aon", .data = &cm_data },
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{ .compatible = "ti,omap5-scrm", .data = &scrm_data },
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{ .compatible = "ti,omap5-cm-core", .data = &cm2_data },
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{ .compatible = "ti,dra7-prm", .data = &prm_data },
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{ .compatible = "ti,dra7-cm-core-aon", .data = &cm_data },
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{ .compatible = "ti,dra7-cm-core", .data = &cm2_data },
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{ }
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};
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@ -703,6 +682,8 @@ int __init omap_prcm_init(void)
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return ret;
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}
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omap_cm_init();
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return 0;
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}
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@ -215,15 +215,14 @@ struct ti_dt_clk {
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.node_name = name, \
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}
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/* Maximum number of clock memmaps */
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#define CLK_MAX_MEMMAPS 4
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/* Static memmap indices */
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enum {
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TI_CLKM_CM = 0,
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TI_CLKM_CM2,
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TI_CLKM_PRM,
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TI_CLKM_SCRM,
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TI_CLKM_CTRL,
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CLK_MAX_MEMMAPS
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};
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typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
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