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ARM: shmobile: sh73a0: add a TWD clock
Add a TWD clock on sh73a0 for the smp_twd driver to properly update the clock's frequency upon cpufreq events. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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parent
0b7d782022
commit
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@ -288,6 +288,20 @@ static struct clk div4_clks[DIV4_NR] = {
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[DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
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};
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static unsigned long twd_recalc(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / 4;
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}
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static struct sh_clk_ops twd_clk_ops = {
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.recalc = twd_recalc,
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};
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static struct clk twd_clk = {
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.parent = &div4_clks[DIV4_Z],
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.ops = &twd_clk_ops,
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};
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enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
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DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
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DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
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@ -482,6 +496,7 @@ static struct clk dsi1phy_clk = {
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static struct clk *late_main_clks[] = {
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&dsi0phy_clk,
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&dsi1phy_clk,
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&twd_clk,
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};
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enum { MSTP001,
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@ -546,6 +561,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("r_clk", &r_clk),
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CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
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/* DIV6 clocks */
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CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
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