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spi: Fixes for v6.12
Some driver specific fixes that came in during the merge window. Lorenzo Bianconi did some extra testing on the recently added arioha driver and found some issues, Alexander Dahl fixed some issues with signal delays in the Atmel QSPI driver and Jinjie Ruan has been fixing some nits with runtime PM cleanup. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmbz0NIACgkQJNaLcl1U h9B1KQf/fcq8ApnJCgD9EykeE9ekziI6PRwxc3XqI+DCws7CN2n4EbIsJxCeiygl d4vWcnBssQGxVv6IbSl3Vgqr6PSAxBxibpBgmANR0HJ8YLFjxoaDTk9ufnJevOEm pMgAtzvt3Ral1VwspKsz3puXEVoJaIoELfEQRB7D8XCX26ypD7+sZSN/AjMATp/N zla5mPjQfGIX7dOis1kaRCQ0ysxoEdZ9zsyFlGs+VZkFIhHbu3KTLhlfADruOa7k RKuVABAIJwqPz6Gew82xlh4hQPP+aecWNdwCSK6+4FZkZLgvUz2rx7evVj3U5+xd Hc3jQmoGnVMYqeuK4BC8T0frnlp6eA== =iJa9 -----END PGP SIGNATURE----- Merge tag 'spi-fix-v6.12-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "Some driver specific fixes that came in during the merge window. Lorenzo Bianconi did some extra testing on the recently added arioha driver and found some issues, Alexander Dahl fixed some issues with signal delays in the Atmel QSPI driver and Jinjie Ruan has been fixing some nits with runtime PM cleanup" * tag 'spi-fix-v6.12-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: atmel-quadspi: Avoid overwriting delay register settings spi: airoha: remove read cache in airoha_snand_dirmap_read() spi: spi-fsl-lpspi: Undo runtime PM changes at driver exit time spi: atmel-quadspi: Undo runtime PM changes at driver exit time spi: airoha: fix airoha_snand_{write,read}_data data_len estimation spi: airoha: fix dirmap_{read,write} operations
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commit
fe29393877
@ -375,9 +375,9 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
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* If the QSPI controller is set in regular SPI mode, set it in
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* If the QSPI controller is set in regular SPI mode, set it in
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* Serial Memory Mode (SMM).
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* Serial Memory Mode (SMM).
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*/
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*/
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if (aq->mr != QSPI_MR_SMM) {
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if (!(aq->mr & QSPI_MR_SMM)) {
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atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
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aq->mr |= QSPI_MR_SMM;
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aq->mr = QSPI_MR_SMM;
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atmel_qspi_write(aq->scr, aq, QSPI_MR);
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}
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}
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/* Clear pending interrupts */
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/* Clear pending interrupts */
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@ -501,7 +501,8 @@ static int atmel_qspi_setup(struct spi_device *spi)
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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aq->scr = QSPI_SCR_SCBR(scbr);
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aq->scr &= ~QSPI_SCR_SCBR_MASK;
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aq->scr |= QSPI_SCR_SCBR(scbr);
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atmel_qspi_write(aq->scr, aq, QSPI_SCR);
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atmel_qspi_write(aq->scr, aq, QSPI_SCR);
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pm_runtime_mark_last_busy(ctrl->dev.parent);
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pm_runtime_mark_last_busy(ctrl->dev.parent);
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@ -534,6 +535,7 @@ static int atmel_qspi_set_cs_timing(struct spi_device *spi)
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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aq->scr &= ~QSPI_SCR_DLYBS_MASK;
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aq->scr |= QSPI_SCR_DLYBS(cs_setup);
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aq->scr |= QSPI_SCR_DLYBS(cs_setup);
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atmel_qspi_write(aq->scr, aq, QSPI_SCR);
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atmel_qspi_write(aq->scr, aq, QSPI_SCR);
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@ -549,8 +551,8 @@ static void atmel_qspi_init(struct atmel_qspi *aq)
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atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
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atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
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/* Set the QSPI controller by default in Serial Memory Mode */
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/* Set the QSPI controller by default in Serial Memory Mode */
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atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
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aq->mr |= QSPI_MR_SMM;
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aq->mr = QSPI_MR_SMM;
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atmel_qspi_write(aq->mr, aq, QSPI_MR);
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/* Enable the QSPI controller */
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/* Enable the QSPI controller */
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atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
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atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
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@ -721,6 +723,7 @@ static void atmel_qspi_remove(struct platform_device *pdev)
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clk_unprepare(aq->pclk);
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clk_unprepare(aq->pclk);
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pm_runtime_disable(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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pm_runtime_dont_use_autosuspend(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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}
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}
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@ -211,9 +211,6 @@ struct airoha_snand_dev {
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u8 *txrx_buf;
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u8 *txrx_buf;
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dma_addr_t dma_addr;
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dma_addr_t dma_addr;
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u64 cur_page_num;
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bool data_need_update;
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};
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};
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struct airoha_snand_ctrl {
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struct airoha_snand_ctrl {
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@ -405,7 +402,7 @@ static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
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for (i = 0; i < len; i += data_len) {
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for (i = 0; i < len; i += data_len) {
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int err;
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int err;
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data_len = min(len, SPI_MAX_TRANSFER_SIZE);
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data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
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err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
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err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
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if (err)
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if (err)
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return err;
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return err;
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@ -427,7 +424,7 @@ static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data,
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for (i = 0; i < len; i += data_len) {
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for (i = 0; i < len; i += data_len) {
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int err;
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int err;
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data_len = min(len, SPI_MAX_TRANSFER_SIZE);
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data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
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err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);
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err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);
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if (err)
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if (err)
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return err;
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return err;
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@ -644,11 +641,6 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
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u32 val, rd_mode;
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u32 val, rd_mode;
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int err;
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int err;
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if (!as_dev->data_need_update)
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return len;
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as_dev->data_need_update = false;
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switch (op->cmd.opcode) {
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switch (op->cmd.opcode) {
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case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
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case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
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rd_mode = 1;
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rd_mode = 1;
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@ -739,8 +731,13 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
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if (err)
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if (err)
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return err;
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return err;
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err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
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/*
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SPI_NFI_READ_FROM_CACHE_DONE);
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* SPI_NFI_READ_FROM_CACHE_DONE bit must be written at the end
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* of dirmap_read operation even if it is already set.
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*/
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err = regmap_write_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
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SPI_NFI_READ_FROM_CACHE_DONE,
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SPI_NFI_READ_FROM_CACHE_DONE);
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if (err)
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if (err)
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return err;
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return err;
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@ -870,8 +867,13 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
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if (err)
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if (err)
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return err;
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return err;
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err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
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/*
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SPI_NFI_LOAD_TO_CACHE_DONE);
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* SPI_NFI_LOAD_TO_CACHE_DONE bit must be written at the end
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* of dirmap_write operation even if it is already set.
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*/
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err = regmap_write_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
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SPI_NFI_LOAD_TO_CACHE_DONE,
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SPI_NFI_LOAD_TO_CACHE_DONE);
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if (err)
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if (err)
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return err;
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return err;
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@ -885,23 +887,11 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
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static int airoha_snand_exec_op(struct spi_mem *mem,
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static int airoha_snand_exec_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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const struct spi_mem_op *op)
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{
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{
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struct airoha_snand_dev *as_dev = spi_get_ctldata(mem->spi);
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u8 data[8], cmd, opcode = op->cmd.opcode;
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u8 data[8], cmd, opcode = op->cmd.opcode;
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struct airoha_snand_ctrl *as_ctrl;
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struct airoha_snand_ctrl *as_ctrl;
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int i, err;
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int i, err;
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as_ctrl = spi_controller_get_devdata(mem->spi->controller);
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as_ctrl = spi_controller_get_devdata(mem->spi->controller);
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if (opcode == SPI_NAND_OP_PROGRAM_EXECUTE &&
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op->addr.val == as_dev->cur_page_num) {
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as_dev->data_need_update = true;
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} else if (opcode == SPI_NAND_OP_PAGE_READ) {
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if (!as_dev->data_need_update &&
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op->addr.val == as_dev->cur_page_num)
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return 0;
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as_dev->data_need_update = true;
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as_dev->cur_page_num = op->addr.val;
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}
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/* switch to manual mode */
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/* switch to manual mode */
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err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
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err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
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@ -986,7 +976,6 @@ static int airoha_snand_setup(struct spi_device *spi)
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if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr))
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if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr))
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return -ENOMEM;
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return -ENOMEM;
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as_dev->data_need_update = true;
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spi_set_ctldata(spi, as_dev);
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spi_set_ctldata(spi, as_dev);
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return 0;
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return 0;
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@ -986,6 +986,7 @@ static void fsl_lpspi_remove(struct platform_device *pdev)
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fsl_lpspi_dma_exit(controller);
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fsl_lpspi_dma_exit(controller);
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pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
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pm_runtime_disable(fsl_lpspi->dev);
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pm_runtime_disable(fsl_lpspi->dev);
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}
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}
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