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pinctrl: Ingenic: Add pinctrl driver for X1000 and X1000E.
Add support for probing the pinctrl-ingenic driver on the X1000 Soc and the X1000E Soc from Ingenic. Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com> Link: https://lore.kernel.org/r/1563076436-5338-5-git-send-email-zhouyanjie@zoho.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Zhou Yanjie
Linus Walleij
parent
6835ad5473
commit
fe1ad5eedc
@ -41,6 +41,9 @@
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#define JZ4760_GPIO_FLAG 0x50
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#define JZ4760_GPIO_PEN 0x70
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#define X1000_GPIO_PZ_BASE 0x700
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#define X1000_GPIO_PZ_GID2LD 0x7f0
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#define REG_SET(x) ((x) + 0x4)
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#define REG_CLEAR(x) ((x) + 0x8)
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@ -53,6 +56,8 @@ enum jz_version {
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ID_JZ4760B,
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ID_JZ4770,
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ID_JZ4780,
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ID_X1000,
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ID_X1000E,
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};
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struct ingenic_chip_info {
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@ -1009,6 +1014,210 @@ static const struct ingenic_chip_info jz4780_chip_info = {
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.pull_downs = jz4770_pull_downs,
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};
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static const u32 x1000_pull_ups[4] = {
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0xffffffff, 0x8dffffff, 0x7d3fffff, 0xffffffff,
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};
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static const u32 x1000_pull_downs[4] = {
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0x00000000, 0x02000000, 0x02000000, 0x00000000,
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};
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static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
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static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
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static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
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static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
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static int x1000_uart1_hwflow_d_pins[] = { 0x64, 0x65, };
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static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
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static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
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static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
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static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
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static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
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static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
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static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
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static int x1000_nemc_8bit_data_pins[] = {
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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};
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static int x1000_nemc_16bit_data_pins[] = {
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0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
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};
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static int x1000_nemc_addr_pins[] = {
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0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
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0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
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};
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static int x1000_nemc_rd_we_pins[] = { 0x30, 0x31, };
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static int x1000_nemc_wait_pins[] = { 0x34, };
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static int x1000_nemc_cs1_pins[] = { 0x32, };
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static int x1000_nemc_cs2_pins[] = { 0x33, };
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static int x1000_i2c0_pins[] = { 0x38, 0x37, };
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static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
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static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
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static int x1000_i2c2_pins[] = { 0x61, 0x60, };
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static int x1000_cim_pins[] = {
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0x08, 0x09, 0x0a, 0x0b,
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0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
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};
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static int x1000_lcd_8bit_pins[] = {
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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0x30, 0x31, 0x32, 0x33, 0x34,
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};
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static int x1000_lcd_16bit_pins[] = {
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0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
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};
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static int x1000_pwm_pwm0_pins[] = { 0x59, };
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static int x1000_pwm_pwm1_pins[] = { 0x5a, };
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static int x1000_pwm_pwm2_pins[] = { 0x5b, };
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static int x1000_pwm_pwm3_pins[] = { 0x26, };
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static int x1000_pwm_pwm4_pins[] = { 0x58, };
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static int x1000_mac_pins[] = {
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0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
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};
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static int x1000_uart0_data_funcs[] = { 0, 0, };
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static int x1000_uart0_hwflow_funcs[] = { 0, 0, };
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static int x1000_uart1_data_a_funcs[] = { 2, 2, };
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static int x1000_uart1_data_d_funcs[] = { 1, 1, };
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static int x1000_uart1_hwflow_d_funcs[] = { 1, 1, };
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static int x1000_uart2_data_a_funcs[] = { 2, 2, };
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static int x1000_uart2_data_d_funcs[] = { 0, 0, };
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static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, };
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static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, };
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static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, };
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static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, };
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static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, };
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static int x1000_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
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static int x1000_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
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static int x1000_nemc_addr_funcs[] = {
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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};
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static int x1000_nemc_rd_we_funcs[] = { 0, 0, };
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static int x1000_nemc_wait_funcs[] = { 0, };
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static int x1000_nemc_cs1_funcs[] = { 0, };
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static int x1000_nemc_cs2_funcs[] = { 0, };
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static int x1000_i2c0_funcs[] = { 0, 0, };
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static int x1000_i2c1_a_funcs[] = { 2, 2, };
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static int x1000_i2c1_c_funcs[] = { 0, 0, };
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static int x1000_i2c2_funcs[] = { 1, 1, };
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static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
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static int x1000_lcd_8bit_funcs[] = {
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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};
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static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
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static int x1000_pwm_pwm0_funcs[] = { 0, };
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static int x1000_pwm_pwm1_funcs[] = { 1, };
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static int x1000_pwm_pwm2_funcs[] = { 1, };
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static int x1000_pwm_pwm3_funcs[] = { 2, };
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static int x1000_pwm_pwm4_funcs[] = { 0, };
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static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
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static const struct group_desc x1000_groups[] = {
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INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data),
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INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),
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INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),
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INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),
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INGENIC_PIN_GROUP("uart1-hwflow-d", x1000_uart1_hwflow_d),
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INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),
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INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),
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INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),
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INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),
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INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),
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INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),
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INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),
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INGENIC_PIN_GROUP("nemc-8bit-data", x1000_nemc_8bit_data),
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INGENIC_PIN_GROUP("nemc-16bit-data", x1000_nemc_16bit_data),
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INGENIC_PIN_GROUP("nemc-addr", x1000_nemc_addr),
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INGENIC_PIN_GROUP("nemc-rd-we", x1000_nemc_rd_we),
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INGENIC_PIN_GROUP("nemc-wait", x1000_nemc_wait),
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INGENIC_PIN_GROUP("nemc-cs1", x1000_nemc_cs1),
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INGENIC_PIN_GROUP("nemc-cs2", x1000_nemc_cs2),
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INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),
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INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
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INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
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INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2),
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INGENIC_PIN_GROUP("cim-data", x1000_cim),
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INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit),
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INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit),
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{ "lcd-no-pins", },
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INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0),
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INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1),
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INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2),
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INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3),
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INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4),
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INGENIC_PIN_GROUP("mac", x1000_mac),
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};
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static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
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static const char *x1000_uart1_groups[] = {
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"uart1-data-a", "uart1-data-d", "uart1-hwflow-d",
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};
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static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
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static const char *x1000_mmc0_groups[] = {
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"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
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};
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static const char *x1000_mmc1_groups[] = {
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"mmc1-1bit-e", "mmc1-4bit-e",
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};
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static const char *x1000_nemc_groups[] = {
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"nemc-8bit-data", "nemc-16bit-data",
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"nemc-addr", "nemc-rd-we", "nemc-wait",
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};
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static const char *x1000_cs1_groups[] = { "nemc-cs1", };
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static const char *x1000_cs2_groups[] = { "nemc-cs2", };
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static const char *x1000_i2c0_groups[] = { "i2c0-data", };
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static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
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static const char *x1000_i2c2_groups[] = { "i2c2-data", };
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static const char *x1000_cim_groups[] = { "cim-data", };
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static const char *x1000_lcd_groups[] = {
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"lcd-8bit", "lcd-16bit", "lcd-no-pins",
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};
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static const char *x1000_pwm0_groups[] = { "pwm0", };
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static const char *x1000_pwm1_groups[] = { "pwm1", };
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static const char *x1000_pwm2_groups[] = { "pwm2", };
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static const char *x1000_pwm3_groups[] = { "pwm3", };
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static const char *x1000_pwm4_groups[] = { "pwm4", };
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static const char *x1000_mac_groups[] = { "mac", };
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static const struct function_desc x1000_functions[] = {
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{ "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
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{ "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
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{ "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
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{ "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
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{ "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
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{ "nemc", x1000_nemc_groups, ARRAY_SIZE(x1000_nemc_groups), },
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{ "nemc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
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{ "nemc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
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{ "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
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{ "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
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{ "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
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{ "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
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{ "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
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{ "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
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{ "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
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{ "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
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{ "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
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{ "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
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{ "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
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};
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static const struct ingenic_chip_info x1000_chip_info = {
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.num_chips = 4,
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.groups = x1000_groups,
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.num_groups = ARRAY_SIZE(x1000_groups),
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.functions = x1000_functions,
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.num_functions = ARRAY_SIZE(x1000_functions),
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.pull_ups = x1000_pull_ups,
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.pull_downs = x1000_pull_downs,
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};
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static const struct ingenic_chip_info x1000e_chip_info = {
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.num_chips = 4,
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.groups = x1000_groups,
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.num_groups = ARRAY_SIZE(x1000_groups),
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.functions = x1000_functions,
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.num_functions = ARRAY_SIZE(x1000_functions),
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.pull_ups = x1000_pull_ups,
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.pull_downs = x1000_pull_downs,
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};
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static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
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{
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unsigned int val;
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@ -1029,6 +1238,23 @@ static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
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regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
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}
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static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
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u8 reg, u8 offset, bool set)
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{
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if (set)
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reg = REG_SET(reg);
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else
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reg = REG_CLEAR(reg);
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regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset));
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}
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static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
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{
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regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_GID2LD,
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jzgc->gc.base / PINS_PER_GPIO_CHIP);
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}
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static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
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u8 offset)
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{
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@ -1061,21 +1287,45 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc,
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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ingenic_gpio_set_bit(jzgc, reg2, offset, true);
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ingenic_gpio_set_bit(jzgc, reg1, offset, true);
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if (jzgc->jzpc->version >= ID_X1000) {
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ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);
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ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);
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ingenic_gpio_shadow_set_bit_load(jzgc);
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} else {
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ingenic_gpio_set_bit(jzgc, reg2, offset, true);
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ingenic_gpio_set_bit(jzgc, reg1, offset, true);
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}
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break;
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case IRQ_TYPE_EDGE_FALLING:
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ingenic_gpio_set_bit(jzgc, reg2, offset, false);
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ingenic_gpio_set_bit(jzgc, reg1, offset, true);
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if (jzgc->jzpc->version >= ID_X1000) {
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ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);
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ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);
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ingenic_gpio_shadow_set_bit_load(jzgc);
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} else {
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ingenic_gpio_set_bit(jzgc, reg2, offset, false);
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ingenic_gpio_set_bit(jzgc, reg1, offset, true);
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}
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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ingenic_gpio_set_bit(jzgc, reg2, offset, true);
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ingenic_gpio_set_bit(jzgc, reg1, offset, false);
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if (jzgc->jzpc->version >= ID_X1000) {
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ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);
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ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);
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ingenic_gpio_shadow_set_bit_load(jzgc);
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} else {
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ingenic_gpio_set_bit(jzgc, reg2, offset, true);
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ingenic_gpio_set_bit(jzgc, reg1, offset, false);
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}
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break;
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case IRQ_TYPE_LEVEL_LOW:
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default:
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ingenic_gpio_set_bit(jzgc, reg2, offset, false);
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ingenic_gpio_set_bit(jzgc, reg1, offset, false);
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if (jzgc->jzpc->version >= ID_X1000) {
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ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);
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ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);
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ingenic_gpio_shadow_set_bit_load(jzgc);
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} else {
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ingenic_gpio_set_bit(jzgc, reg2, offset, false);
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ingenic_gpio_set_bit(jzgc, reg1, offset, false);
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}
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break;
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}
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}
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@ -1248,6 +1498,21 @@ static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
|
||||
(set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
|
||||
}
|
||||
|
||||
static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
|
||||
unsigned int pin, u8 reg, bool set)
|
||||
{
|
||||
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
|
||||
|
||||
regmap_write(jzpc->map, X1000_GPIO_PZ_BASE +
|
||||
(set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
|
||||
}
|
||||
|
||||
static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
|
||||
unsigned int pin)
|
||||
{
|
||||
regmap_write(jzpc->map, X1000_GPIO_PZ_GID2LD, pin / PINS_PER_GPIO_CHIP);
|
||||
}
|
||||
|
||||
static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
|
||||
unsigned int pin, u8 reg)
|
||||
{
|
||||
@ -1292,7 +1557,13 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
|
||||
dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
|
||||
'A' + offt, idx, func);
|
||||
|
||||
if (jzpc->version >= ID_JZ4760) {
|
||||
if (jzpc->version >= ID_X1000) {
|
||||
ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
|
||||
ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
|
||||
ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
|
||||
ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
|
||||
ingenic_shadow_config_pin_load(jzpc, pin);
|
||||
} else if (jzpc->version >= ID_JZ4760) {
|
||||
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
|
||||
ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
|
||||
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
|
||||
@ -1345,7 +1616,12 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
|
||||
dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
|
||||
'A' + offt, idx, input ? "in" : "out");
|
||||
|
||||
if (jzpc->version >= ID_JZ4760) {
|
||||
if (jzpc->version >= ID_X1000) {
|
||||
ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
|
||||
ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
|
||||
ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
|
||||
ingenic_shadow_config_pin_load(jzpc, pin);
|
||||
} else if (jzpc->version >= ID_JZ4760) {
|
||||
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
|
||||
ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
|
||||
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
|
||||
@ -1532,6 +1808,8 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = {
|
||||
{ .compatible = "ingenic,jz4760b-pinctrl", .data = (void *) ID_JZ4760B },
|
||||
{ .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 },
|
||||
{ .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 },
|
||||
{ .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 },
|
||||
{ .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E },
|
||||
{},
|
||||
};
|
||||
|
||||
@ -1540,6 +1818,7 @@ static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
|
||||
{ .compatible = "ingenic,jz4760-gpio", },
|
||||
{ .compatible = "ingenic,jz4770-gpio", },
|
||||
{ .compatible = "ingenic,jz4780-gpio", },
|
||||
{ .compatible = "ingenic,x1000-gpio", },
|
||||
{},
|
||||
};
|
||||
|
||||
@ -1655,7 +1934,11 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
|
||||
else
|
||||
jzpc->version = (enum jz_version)id->driver_data;
|
||||
|
||||
if (jzpc->version >= ID_JZ4780)
|
||||
if (jzpc->version >= ID_X1000E)
|
||||
chip_info = &x1000e_chip_info;
|
||||
else if (jzpc->version >= ID_X1000)
|
||||
chip_info = &x1000_chip_info;
|
||||
else if (jzpc->version >= ID_JZ4780)
|
||||
chip_info = &jz4780_chip_info;
|
||||
else if (jzpc->version >= ID_JZ4770)
|
||||
chip_info = &jz4770_chip_info;
|
||||
@ -1743,6 +2026,8 @@ static const struct platform_device_id ingenic_pinctrl_ids[] = {
|
||||
{ "jz4760b-pinctrl", ID_JZ4760B },
|
||||
{ "jz4770-pinctrl", ID_JZ4770 },
|
||||
{ "jz4780-pinctrl", ID_JZ4780 },
|
||||
{ "x1000-pinctrl", ID_X1000 },
|
||||
{ "x1000e-pinctrl", ID_X1000E },
|
||||
{},
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user