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fpga: dfl: fme: add power management support
This patch adds support for power management private feature under FPGA Management Engine (FME). This private feature driver registers a hwmon for power (power1_input), thresholds information, e.g. (power1_max / crit / max_alarm / crit_alarm) and also read-only sysfs interfaces for other power management information. For configuration, user could write threshold values via above power1_max / crit sysfs interface under hwmon too. Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org>
This commit is contained in:
Wu Hao
Moritz Fischer
parent
4284c65a9f
commit
fddc9fcbe6
@ -114,6 +114,7 @@ Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Only. Read this file to get the name of hwmon device, it
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supports values:
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'dfl_fme_thermal' - thermal hwmon device name
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'dfl_fme_power' - power hwmon device name
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_input
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Date: October 2019
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@ -170,3 +171,70 @@ Description: Read-Only. Read this file to get the policy of hardware threshold1
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(see 'temp1_max'). It only supports two values (policies):
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0 - AP2 state (90% throttling)
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1 - AP1 state (50% throttling)
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_input
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Only. It returns current FPGA power consumption in uW.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_max
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Write. Read this file to get current hardware power
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threshold1 in uW. If power consumption rises at or above
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this threshold, hardware starts 50% throttling.
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Write this file to set current hardware power threshold1 in uW.
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As hardware only accepts values in Watts, so input value will
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be round down per Watts (< 1 watts part will be discarded) and
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clamped within the range from 0 to 127 Watts. Write fails with
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-EINVAL if input parsing fails.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_crit
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Write. Read this file to get current hardware power
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threshold2 in uW. If power consumption rises at or above
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this threshold, hardware starts 90% throttling.
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Write this file to set current hardware power threshold2 in uW.
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As hardware only accepts values in Watts, so input value will
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be round down per Watts (< 1 watts part will be discarded) and
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clamped within the range from 0 to 127 Watts. Write fails with
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-EINVAL if input parsing fails.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_max_alarm
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. It returns 1 if power consumption is currently at or
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above hardware threshold1 (see 'power1_max'), otherwise 0.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_crit_alarm
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. It returns 1 if power consumption is currently at or
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above hardware threshold2 (see 'power1_crit'), otherwise 0.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_xeon_limit
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Only. It returns power limit for XEON in uW.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_fpga_limit
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Only. It returns power limit for FPGA in uW.
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What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_ltr
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Date: October 2019
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KernelVersion: 5.5
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. Read this file to get current Latency Tolerance
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Reporting (ltr) value. It returns 1 if all Accelerated
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Function Units (AFUs) can tolerate latency >= 40us for memory
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access or 0 if any AFU is latency sensitive (< 40us).
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@ -355,6 +355,209 @@ static const struct dfl_feature_ops fme_thermal_mgmt_ops = {
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.init = fme_thermal_mgmt_init,
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};
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#define FME_PWR_STATUS 0x8
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#define FME_LATENCY_TOLERANCE BIT_ULL(18)
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#define PWR_CONSUMED GENMASK_ULL(17, 0)
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#define FME_PWR_THRESHOLD 0x10
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#define PWR_THRESHOLD1 GENMASK_ULL(6, 0) /* in Watts */
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#define PWR_THRESHOLD2 GENMASK_ULL(14, 8) /* in Watts */
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#define PWR_THRESHOLD_MAX 0x7f /* in Watts */
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#define PWR_THRESHOLD1_STATUS BIT_ULL(16)
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#define PWR_THRESHOLD2_STATUS BIT_ULL(17)
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#define FME_PWR_XEON_LIMIT 0x18
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#define XEON_PWR_LIMIT GENMASK_ULL(14, 0) /* in 0.1 Watts */
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#define XEON_PWR_EN BIT_ULL(15)
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#define FME_PWR_FPGA_LIMIT 0x20
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#define FPGA_PWR_LIMIT GENMASK_ULL(14, 0) /* in 0.1 Watts */
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#define FPGA_PWR_EN BIT_ULL(15)
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static int power_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long *val)
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{
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struct dfl_feature *feature = dev_get_drvdata(dev);
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u64 v;
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switch (attr) {
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case hwmon_power_input:
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v = readq(feature->ioaddr + FME_PWR_STATUS);
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*val = (long)(FIELD_GET(PWR_CONSUMED, v) * 1000000);
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break;
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case hwmon_power_max:
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v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
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*val = (long)(FIELD_GET(PWR_THRESHOLD1, v) * 1000000);
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break;
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case hwmon_power_crit:
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v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
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*val = (long)(FIELD_GET(PWR_THRESHOLD2, v) * 1000000);
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break;
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case hwmon_power_max_alarm:
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v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
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*val = (long)FIELD_GET(PWR_THRESHOLD1_STATUS, v);
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break;
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case hwmon_power_crit_alarm:
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v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
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*val = (long)FIELD_GET(PWR_THRESHOLD2_STATUS, v);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int power_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long val)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev->parent);
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struct dfl_feature *feature = dev_get_drvdata(dev);
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int ret = 0;
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u64 v;
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val = clamp_val(val / 1000000, 0, PWR_THRESHOLD_MAX);
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mutex_lock(&pdata->lock);
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switch (attr) {
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case hwmon_power_max:
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v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
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v &= ~PWR_THRESHOLD1;
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v |= FIELD_PREP(PWR_THRESHOLD1, val);
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writeq(v, feature->ioaddr + FME_PWR_THRESHOLD);
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break;
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case hwmon_power_crit:
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v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
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v &= ~PWR_THRESHOLD2;
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v |= FIELD_PREP(PWR_THRESHOLD2, val);
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writeq(v, feature->ioaddr + FME_PWR_THRESHOLD);
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break;
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default:
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ret = -EOPNOTSUPP;
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break;
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}
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mutex_unlock(&pdata->lock);
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return ret;
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}
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static umode_t power_hwmon_attrs_visible(const void *drvdata,
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enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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switch (attr) {
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case hwmon_power_input:
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case hwmon_power_max_alarm:
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case hwmon_power_crit_alarm:
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return 0444;
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case hwmon_power_max:
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case hwmon_power_crit:
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return 0644;
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}
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return 0;
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}
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static const struct hwmon_ops power_hwmon_ops = {
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.is_visible = power_hwmon_attrs_visible,
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.read = power_hwmon_read,
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.write = power_hwmon_write,
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};
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static const struct hwmon_channel_info *power_hwmon_info[] = {
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HWMON_CHANNEL_INFO(power, HWMON_P_INPUT |
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HWMON_P_MAX | HWMON_P_MAX_ALARM |
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HWMON_P_CRIT | HWMON_P_CRIT_ALARM),
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NULL
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};
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static const struct hwmon_chip_info power_hwmon_chip_info = {
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.ops = &power_hwmon_ops,
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.info = power_hwmon_info,
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};
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static ssize_t power1_xeon_limit_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature *feature = dev_get_drvdata(dev);
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u16 xeon_limit = 0;
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u64 v;
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v = readq(feature->ioaddr + FME_PWR_XEON_LIMIT);
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if (FIELD_GET(XEON_PWR_EN, v))
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xeon_limit = FIELD_GET(XEON_PWR_LIMIT, v);
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return sprintf(buf, "%u\n", xeon_limit * 100000);
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}
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static ssize_t power1_fpga_limit_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature *feature = dev_get_drvdata(dev);
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u16 fpga_limit = 0;
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u64 v;
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v = readq(feature->ioaddr + FME_PWR_FPGA_LIMIT);
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if (FIELD_GET(FPGA_PWR_EN, v))
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fpga_limit = FIELD_GET(FPGA_PWR_LIMIT, v);
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return sprintf(buf, "%u\n", fpga_limit * 100000);
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}
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static ssize_t power1_ltr_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature *feature = dev_get_drvdata(dev);
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u64 v;
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v = readq(feature->ioaddr + FME_PWR_STATUS);
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return sprintf(buf, "%u\n",
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(unsigned int)FIELD_GET(FME_LATENCY_TOLERANCE, v));
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}
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static DEVICE_ATTR_RO(power1_xeon_limit);
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static DEVICE_ATTR_RO(power1_fpga_limit);
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static DEVICE_ATTR_RO(power1_ltr);
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static struct attribute *power_extra_attrs[] = {
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&dev_attr_power1_xeon_limit.attr,
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&dev_attr_power1_fpga_limit.attr,
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&dev_attr_power1_ltr.attr,
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NULL
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};
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ATTRIBUTE_GROUPS(power_extra);
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static int fme_power_mgmt_init(struct platform_device *pdev,
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struct dfl_feature *feature)
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{
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struct device *hwmon;
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hwmon = devm_hwmon_device_register_with_info(&pdev->dev,
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"dfl_fme_power", feature,
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&power_hwmon_chip_info,
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power_extra_groups);
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if (IS_ERR(hwmon)) {
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dev_err(&pdev->dev, "Fail to register power hwmon\n");
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return PTR_ERR(hwmon);
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}
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return 0;
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}
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static const struct dfl_feature_id fme_power_mgmt_id_table[] = {
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{.id = FME_FEATURE_ID_POWER_MGMT,},
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{0,}
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};
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static const struct dfl_feature_ops fme_power_mgmt_ops = {
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.init = fme_power_mgmt_init,
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};
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static struct dfl_feature_driver fme_feature_drvs[] = {
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{
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.id_table = fme_hdr_id_table,
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@ -372,6 +575,10 @@ static struct dfl_feature_driver fme_feature_drvs[] = {
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.id_table = fme_thermal_mgmt_id_table,
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.ops = &fme_thermal_mgmt_ops,
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},
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{
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.id_table = fme_power_mgmt_id_table,
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.ops = &fme_power_mgmt_ops,
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},
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{
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.ops = NULL,
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},
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