From 59d94d2ed45d598211feb52566e6a806d17f8a3f Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 25 Jan 2017 10:01:28 -0600 Subject: [PATCH 1/2] ARM: dts: watchdog0 cannot reliably trigger reset On the Arria10, because of hardware bug, watchdog0 cannot reliably trigger a reset to the CPU. The workaround would be to use watchdog1 instead. Also for watchdog1, there is a dependency on the bootloader to enable the boot_clk source to be from the cb_intosc_hs_clk/2, versus from EOSC1. This corresponds to the (SWCTRLBTCLKEN & SWCTRLBTCLKSEL) bits enabled in the control register in the clock manager module of Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 4c99c99d1752..c57e6cea0d83 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -160,6 +160,6 @@ status = "okay"; }; -&watchdog0 { +&watchdog1 { status = "okay"; }; From cda1ade6a25c85d0a7cc2001a96b0b20f6bfd3f0 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Thu, 2 Feb 2017 16:05:21 -0600 Subject: [PATCH 2/2] ARM: dts: Add EMAC AXI settings for Arria10 Add the device tree entries needed to support the EMAC AXI bus settings on the Arria10 SoCFPGA chip. Signed-off-by: Thor Thayer Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 65904db153be..6b0b7463f36f 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -408,6 +408,12 @@ }; }; + socfpga_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <0 0 0 0 16 0 0>; + }; + gmac0: ethernet@ff800000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; altr,sysmgr-syscon = <&sysmgr 0x44 0>; @@ -424,6 +430,7 @@ clock-names = "stmmaceth"; resets = <&rst EMAC0_RESET>; reset-names = "stmmaceth"; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -443,6 +450,7 @@ clock-names = "stmmaceth"; resets = <&rst EMAC1_RESET>; reset-names = "stmmaceth"; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -460,6 +468,7 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; };